CN214585758U - Port test circuit and device - Google Patents
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- CN214585758U CN214585758U CN202120352585.9U CN202120352585U CN214585758U CN 214585758 U CN214585758 U CN 214585758U CN 202120352585 U CN202120352585 U CN 202120352585U CN 214585758 U CN214585758 U CN 214585758U
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Abstract
The utility model discloses a port test circuit and a device, wherein the port test circuit comprises a port connection module, a port detection module and a level conversion module; the port connecting module is used for connecting a port to be tested of the equipment to be tested; the port detection module is used for outputting a test signal to the equipment to be tested through the port to be tested, receiving a feedback signal output by the equipment to be tested through the port to be tested according to the test signal, and determining that the port to be tested outputs a pulse signal to the level conversion module when the port to be tested is normal according to the feedback signal; the level conversion module is used for converting the pulse signal into an identification signal to the rear-end test equipment; the utility model discloses can realize treating the port function of equipment for testing and carry out automatic testing, effectively avoid the problem of examining that leaks that artifical detection exists, improve efficiency of software testing.
Description
Technical Field
The utility model relates to an electronic equipment technical field, in particular to port test circuit and device.
Background
The existing television comprises three parts, namely a liquid crystal display screen, a power panel and a core board, wherein in the production and manufacturing process, whether various indexes and standard matching functions meet normal requirements or not needs to be electrified to test each port so as to judge whether the delivery requirements are met or not; the network function and the USB function of the existing television core board are tested by adopting a traditional mode to remotely control the channel interface to check the network IP address or the USB disk, whether the connection is carried out or not is judged by human eyes, the operation steps are complicated, nearly one thousand boards need to be tested every day, the eye fatigue is easily caused to appear and the test efficiency is low.
Thus, the prior art has yet to be improved and enhanced.
SUMMERY OF THE UTILITY MODEL
In view of the foregoing prior art's weak point, an object of the utility model is to provide a port test circuit and device can effectively solve the problem that detection efficiency is low that exists when current coreboard on-line production detects.
In order to achieve the purpose, the utility model adopts the following technical proposal:
a port test circuit comprises a port connection module, a port detection module and a level conversion module; the port connecting module is used for connecting a port to be tested of the equipment to be tested; the port detection module is used for outputting a test signal to the equipment to be tested through the port to be tested, receiving a feedback signal output by the equipment to be tested through the port to be tested according to the test signal, and determining that the port to be tested outputs a pulse signal to the level conversion module when the port to be tested is normal according to the feedback signal; the level conversion module is used for converting the pulse signal into an identification signal to the rear-end test equipment.
In the port test circuit, the port connection module comprises a first test port and a second test port; the first test port is used for connecting a first port to be tested of the equipment to be tested, and the second test port is used for connecting a second port to be tested of the equipment to be tested.
In the port test circuit, the port detection module comprises a first detection unit and a second detection unit; the first detection unit is used for outputting a test signal to the equipment to be tested through the first port to be tested, receiving a feedback signal output by the equipment to be tested through the first port to be tested according to the test signal, and determining that the first port to be tested outputs a pulse signal to the level conversion module when the first port to be tested is normal according to the feedback signal; the second detection unit is used for outputting a test signal to the equipment to be tested through the second port to be tested, receiving a feedback signal output by the equipment to be tested through the second port to be tested according to the test signal, and determining that the second port to be tested outputs a pulse signal to the level conversion module when the second port to be tested is normal according to the feedback signal.
In the port test circuit, the first detection unit comprises a control chip, a 1 st pin of the control chip is connected with the level conversion module, and a 2 nd pin of the control chip is connected with the level conversion module.
In the port test circuit, the second detection unit comprises a first USB chip, a second USB chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; a pin 1 of the first USB chip is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the first capacitor and the second test port, the other end of the first capacitor is grounded, a pin 2 of the first USB chip is connected with one end of the second resistor, a pin 3 of the first USB chip is connected with the level conversion module, the other end of the second resistor is connected with one end of the second capacitor and the second test port, and the other end of the second capacitor is grounded; the 1 st pin of the second USB chip is connected with one end of the third resistor, the other end of the third resistor is connected with one end of the third capacitor and the second test port, the other end of the third capacitor is grounded, the 2 nd pin of the second USB chip is connected with one end of the fourth resistor, the 3 rd pin of the second USB chip is connected with the level conversion module, the other end of the fourth resistor is connected with one end of the fourth capacitor and the second test port, and the other end of the fourth capacitor is grounded.
In the port test circuit, the level conversion module comprises a first photoelectric coupler, a second photoelectric coupler, a third photoelectric coupler, a fourth photoelectric coupler and a level output port; the 1 st pin of the first photoelectric coupler is connected with the 2 nd pin of the control chip, the 2 nd pin of the first photoelectric coupler is connected with the level output port, the 1 st pin of the second photoelectric coupler is connected with the 1 st pin of the control chip, the 2 nd pin of the second photoelectric coupler is connected with the level output port, the 1 st pin of the third photoelectric coupler is connected with the second detection unit, the 2 nd pin of the third photoelectric coupler is connected with the level output port, the 1 st pin of the fourth photoelectric coupler is connected with the second detection unit, and the 2 nd pin of the fourth photoelectric coupler is connected with the level output port.
The port test circuit further comprises a power supply module, and the power supply module is used for supplying electric energy to the level conversion module.
In the port test circuit, the power supply module comprises a voltage stabilizer, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a fifth capacitor; the power supply end is connected to the 1 st pin of the voltage stabilizer, the 2 nd pin of the voltage stabilizer is grounded, the 3 rd pin of the voltage stabilizer is connected with one end of the fifth resistor, one end of the sixth resistor, one end of the seventh resistor, one end of the eighth resistor and one end of the fifth capacitor, the other end of the fifth capacitor is grounded, and the other end of the fifth resistor, the other end of the sixth resistor, the other end of the seventh resistor and the other end of the eighth resistor are all connected with the level conversion module.
A port test device comprises the port test circuit.
Compared with the prior art, the utility model provides a port test circuit and device, port test circuit includes port connection module, port detection module and level conversion module; the port connecting module is used for connecting a port to be tested of the equipment to be tested; the port detection module is used for outputting a test signal to the equipment to be tested through the port to be tested, receiving a feedback signal output by the equipment to be tested through the port to be tested according to the test signal, and determining that the port to be tested outputs a pulse signal to the level conversion module when the port to be tested is normal according to the feedback signal; the level conversion module is used for converting the pulse signal into an identification signal to the rear-end test equipment; the utility model discloses can realize treating the port function of equipment for testing and carry out automatic testing, effectively avoid the problem of examining that leaks that artifical detection exists, improve efficiency of software testing.
Drawings
Fig. 1 is a block diagram of a port test circuit provided by the present invention;
fig. 2 is a schematic diagram of a port test circuit provided by the present invention;
fig. 3 is a schematic diagram of the port testing apparatus provided by the present invention.
Detailed Description
The utility model provides a port test circuit and device can effectively solve the problem that detection efficiency is low that exists when current core board on-line production detects.
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the following description of the present invention will refer to the accompanying drawings and illustrate embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
Referring to fig. 1, the port test circuit provided by the present invention includes a port connection module 100, a port detection module 200 and a level conversion module 300, wherein the port connection module 100 is used for connecting a port to be tested of a device to be tested, the port connection module 100 is further connected to the port detection module 200, and the port detection module 200 is further connected to the level conversion module 300.
In specific implementation, after a device to be tested (in this embodiment, a core board of a television) is connected to the port test circuit through the port connection module 100, and the device to be tested is normally started when the power is turned on, the port detection module 200 is configured to output a test signal to the device to be tested through the port to be tested, receive a feedback signal output by the device to be tested through the port to be tested according to the test signal, and determine that the port to be tested is normally outputting a pulse signal to the level conversion module 300 according to the feedback signal, that is, the port detection module 200 performs information interaction with the device to be tested through the port to be tested, when the feedback signal received by the port detection module 200 is not abnormal with the sent test signal and the information interaction can be performed normally, it indicates that the device to be tested is normally connected through the port to be tested, that is to say, the function of the port to be tested is normal, the port detection module 200 outputs a pulse signal to the level conversion module 300; the level conversion module 300 is used for converting the pulse signal into an identification signal (a high level signal in this embodiment) to a rear-end test device, and it should be noted that the rear-end test device is an existing test device, and after the rear-end test device automatically identifies the high level signal, the function of the port to be tested is determined automatically, so that the automatic detection of the port to be tested of the device to be tested is realized, the problem of missing detection in manual detection is effectively avoided, and the test efficiency is effectively improved.
Further, the port connection module 100 includes a first test port and a second test port; the first test port is used for connecting a first port to be tested of the equipment to be tested, and the second test port is used for connecting a second port to be tested of the equipment to be tested; in this embodiment, the first test port is a network test port, the second test port is a USB test port, and then the corresponding first port to be tested is a network port, and the second interface to be tested is a USB port; the first test port is used for detecting whether the network interface is normal, and the second test port is used for detecting whether the USB port is normal. In this embodiment, the first test port and the second test port are respectively provided with two ports, and two ports are respectively provided, so as to simultaneously detect two networks and two USB functions.
Further, the port detection module 200 includes a first detection unit 210 and a second detection unit 220, and both the first detection unit 210 and the second detection unit 220 are connected to the level shift module 300; the first detecting unit 210 is configured to output a test signal to the device to be tested through the first port to be tested, receive a feedback signal output by the device to be tested through the first port to be tested according to the test signal, determine that the first port to be tested is normal according to the feedback signal, and output a pulse signal to the level converting module 300, where when the first detecting unit 210 receives the feedback signal and outputs the test signal without abnormality, it indicates that the network port is normal in function, and then the first detecting unit 210 outputs the pulse signal to the level converting module 300; on the contrary, if the first detection unit 210 receives the feedback signal and outputs the test signal, which is abnormal, it indicates that the function of the network port is abnormal, and at this time, the first detection unit 210 does not output the pulse signal, thereby implementing the automatic test of the function of the network port.
Similarly, the second detecting unit 220 is configured to output a test signal to the device under test through the second port under test, receive a feedback signal output by the device under test through the second port under test according to the test signal, determine, according to the feedback signal, that the second port under test is normal, and output a pulse signal to the level conversion module 300, where when the second detecting unit 220 receives the feedback signal and outputs the signal under test without exception, it indicates that the function of the USB port is normal, and then the second detecting unit 220 outputs the pulse signal to the level conversion module 300; when the second detection unit 220 receives the feedback signal and outputs the signal to be tested, it indicates that the function of the USB port is abnormal, and then the second detection unit 220 does not output the pulse signal, thereby implementing the automatic test of the function of the USB port.
Further, referring to fig. 2, the first detecting unit 210 includes a control chip, a pin 1 of the control chip is connected to the level shifting module 300, and a pin 2 of the control chip is connected to the level shifting module 300; the model of the control chip in this embodiment is IP3210LF, and certainly, in other embodiments, a control chip with the same function may be selected, which is not limited by the present invention.
In specific implementation, after the device to be tested is normally started by powering on, the first detection unit 210 in the port detection circuit reads MAC information written in advance by the tested end through the connection cable, the control chip completes reading and exchanging data by outputting differential pairs TXD + TXD- (when the sending enable pin of the control chip is set to be high level and the MAC information transmits data through the line and the physical layer address of the register PHY under the synchronization of the sending clock) and receiving differential pairs RXD + RXD- (when the line is the physical address transmission path of the PHY and transmits data to the MAC under the synchronization of the receiving clock signal), so that the control chip automatically decodes the output information without abnormality, judges whether the decoded information is connected with the tested end or not, and outputs an effective pulse waveform signal after the connection is established, the tested network port is indicated to be normal in function; otherwise, if an abnormal network exists in any branch of the output and input differential pairs (TXD +, TXD-, RXD + and RXD-) and no pulse waveform signal is output, the tested network port is indicated to be normal in function, and therefore the automatic test of the network port is realized.
Further, the second detection unit 220 includes a first USB chip, a second USB chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; a pin 1 of the first USB chip is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor and the second test port, the other end of the first capacitor is grounded, a pin 2 of the first USB chip is connected to one end of the second resistor, a pin 3 of the first USB chip is connected to the level conversion module 300, the other end of the second resistor is connected to one end of the second capacitor and the second test port, and the other end of the second capacitor is grounded; a pin 1 of the second USB chip is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the third capacitor and the second test port, the other end of the third capacitor is grounded, a pin 2 of the second USB chip is connected to one end of the fourth resistor, a pin 3 of the second USB chip is connected to the level conversion module 300, the other end of the fourth resistor is connected to one end of the fourth capacitor and the second test port, and the other end of the fourth capacitor is grounded; the model of the first USB chip and the second USB chip in this embodiment is STM32F103C8, but in other embodiments, chips having the same function may be selected, which is not limited in the present invention.
Specifically, the port test circuit is provided with two USB test ports, which are JB1 and JB2, respectively, and two corresponding USB chips, which are U1 and U2, respectively, each chip is correspondingly connected with one USB test interface, the first USB chip is correspondingly connected with the USB test interface JB1, and the second USB chip is correspondingly connected with the USB test interface JB 2; after the device to be tested is normally started after being powered on, the USB port to be tested outputs 5V direct current power supply through the USB test port to provide working voltage with the corresponding USB chip, at the moment, the USB chip starts to simulate the normal work of the USB disk and outputs a pulse signal to the level conversion module 300 through two input and output data pins of a D + signal end and a D-signal end, if the two ends are normally connected, the USB chip outputs the pulse signal, if the D + signal end or the D-signal end in the USB port of the core board cannot be connected when abnormality exists, the USB chip does not output the pulse signal, and therefore automatic test of the USB port is achieved.
Furthermore, the two USB test ports are connected with load resistors ROJ1 and ROJ2 respectively, and the load resistors are used for simulating the detection of the 5V power supply load capacity of the tested USB ports, so that the function of the port test device is optimized.
Further, the level conversion module 300 includes a first photo coupler UN1, a second photo coupler UN2, a third photo coupler UN3, a fourth photo coupler UN4, and a level output port CN 1; the 1 st pin of the first photocoupler UN1 is connected with the 2 nd pin of the control chip, the 2 nd pin of the first photocoupler UN1 is connected with the level output port CN1, the 1 st pin of the second photocoupler UN2 is connected with the 1 st pin of the control chip, the 2 nd pin of the second photocoupler UN2 is connected with the level output port CN1, the 1 st pin of the third photocoupler UN3 is connected with the 3 rd pin of the first USB chip, the 2 nd pin of the third photocoupler UN3 is connected with the level output port CN1, the 1 st pin of the fourth photocoupler UN4 is connected with the 3 rd pin of the second USB chip, the 2 nd pin of the fourth photocoupler UN4 is connected with the level output port CN1, and as four test ports are provided, two network test ports and two USB test ports are respectively provided, four photocouplers are correspondingly provided; the four photoelectric couplers respectively carry out isolation conversion on two paths of pulse signals output by the control chip and two paths of pulse signals output by the two USB chips and then output +5V high-level signals to the rear-end testing equipment, so that the rear-end testing equipment can effectively identify the signals.
Further, the port test circuit further includes a power supply module 400, where the power supply module 400 is configured to provide power for the level shift module 300, so as to ensure normal operation of the level shift module 300.
Further, the power supply module 400 includes a voltage regulator, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a fifth capacitor C5; a 1 st pin of the voltage regulator is connected with a power supply end, a 2 nd pin of the voltage regulator is grounded, a 3 rd pin of the voltage regulator is connected with one end of the fifth resistor R5, one end of the sixth resistor R6, one end of the seventh resistor R7, one end of the eighth resistor R8 and one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is grounded, and the other end of the fifth resistor R5, the other end of the sixth resistor R6, the other end of the seventh resistor R7 and the other end of the eighth resistor R8 are all connected with the level conversion module 300; the power supply module 400 provides working power for each photoelectric coupler in the level conversion module 300, thereby ensuring that each photoelectric coupler can work normally.
Further, please refer to fig. 3, the utility model also discloses a port testing arrangement, port testing arrangement includes the shell, be provided with PCB in the shell, be provided with foretell port test circuit on the PCB board, the surface of shell is provided with four test ports, level output port 19 and four pilot lamps, and wherein, four pilot lamps are used for instructing the operating condition of four test ports respectively, and four test ports are network test port 11, network test port 12, USB test interface 13 and USB test port 14 respectively, and four corresponding pilot lamps are pilot lamp 15, pilot lamp 16, pilot lamp 17 and pilot lamp 18 respectively, because the above is right the theory of operation of port test circuit has carried out the detailed description, no longer gives details here.
To sum up, the utility model provides a port test circuit and a device, the port test circuit comprises a port connection module, a port detection module and a level conversion module; the port connecting module is used for connecting a port to be tested of the equipment to be tested; the port detection module is used for outputting a test signal to the equipment to be tested through the port to be tested, receiving a feedback signal output by the equipment to be tested through the port to be tested according to the test signal, and determining that the port to be tested outputs a pulse signal to the level conversion module when the port to be tested is normal according to the feedback signal; the level conversion module is used for converting the pulse signal into an identification signal to the rear-end test equipment; the utility model discloses can realize treating the port function of equipment for testing and carry out automatic testing, effectively avoid the problem of examining that leaks that artifical detection exists, improve efficiency of software testing.
It should be understood that equivalent alterations and modifications can be made by those skilled in the art according to the technical solution of the present invention and the inventive concept thereof, and all such alterations and modifications should fall within the scope of the appended claims.
Claims (9)
1. A port test circuit is characterized by comprising a port connection module, a port detection module and a level conversion module; the port connecting module is used for connecting a port to be tested of the equipment to be tested; the port detection module is used for outputting a test signal to the equipment to be tested through the port to be tested, receiving a feedback signal output by the equipment to be tested through the port to be tested according to the test signal, and determining that the port to be tested outputs a pulse signal to the level conversion module when the port to be tested is normal according to the feedback signal; the level conversion module is used for converting the pulse signal into an identification signal to the rear-end test equipment.
2. The port test circuit of claim 1, wherein the port connection module comprises a first test port and a second test port; the first test port is used for connecting a first port to be tested of the equipment to be tested, and the second test port is used for connecting a second port to be tested of the equipment to be tested.
3. The port test circuit of claim 2, wherein the port test module comprises a first test unit and a second test unit; the first detection unit is used for outputting a test signal to the equipment to be tested through the first port to be tested, receiving a feedback signal output by the equipment to be tested through the first port to be tested according to the test signal, and determining that the first port to be tested outputs a pulse signal to the level conversion module when the first port to be tested is normal according to the feedback signal; the second detection unit is used for outputting a test signal to the equipment to be tested through the second port to be tested, receiving a feedback signal output by the equipment to be tested through the second port to be tested according to the test signal, and determining that the second port to be tested outputs a pulse signal to the level conversion module when the second port to be tested is normal according to the feedback signal.
4. The port test circuit of claim 3, wherein the first detection unit comprises a control chip, a pin 1 of the control chip is connected to the level shift module, and a pin 2 of the control chip is connected to the level shift module.
5. The port test circuit of claim 3, wherein the second detection unit comprises a first USB chip, a second USB chip, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; a pin 1 of the first USB chip is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the first capacitor and the second test port, the other end of the first capacitor is grounded, a pin 2 of the first USB chip is connected with one end of the second resistor, a pin 3 of the first USB chip is connected with the level conversion module, the other end of the second resistor is connected with one end of the second capacitor and the second test port, and the other end of the second capacitor is grounded; the 1 st pin of the second USB chip is connected with one end of the third resistor, the other end of the third resistor is connected with one end of the third capacitor and the second test port, the other end of the third capacitor is grounded, the 2 nd pin of the second USB chip is connected with one end of the fourth resistor, the 3 rd pin of the second USB chip is connected with the level conversion module, the other end of the fourth resistor is connected with one end of the fourth capacitor and the second test port, and the other end of the fourth capacitor is grounded.
6. The port test circuit of claim 4, wherein the level conversion module comprises a first photo coupler, a second photo coupler, a third photo coupler, a fourth photo coupler and a level output port; the 1 st pin of the first photoelectric coupler is connected with the 2 nd pin of the control chip, the 2 nd pin of the first photoelectric coupler is connected with the level output port, the 1 st pin of the second photoelectric coupler is connected with the 1 st pin of the control chip, the 2 nd pin of the second photoelectric coupler is connected with the level output port, the 1 st pin of the third photoelectric coupler is connected with the second detection unit, the 2 nd pin of the third photoelectric coupler is connected with the level output port, the 1 st pin of the fourth photoelectric coupler is connected with the second detection unit, and the 2 nd pin of the fourth photoelectric coupler is connected with the level output port.
7. The port test circuit according to any of claims 1-6, further comprising a power module for providing power to the level shifting module.
8. The port test circuit of claim 7, wherein the power supply module comprises a voltage regulator, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a fifth capacitor; the power supply end is connected to the 1 st pin of the voltage stabilizer, the 2 nd pin of the voltage stabilizer is grounded, the 3 rd pin of the voltage stabilizer is connected with one end of the fifth resistor, one end of the sixth resistor, one end of the seventh resistor, one end of the eighth resistor and one end of the fifth capacitor, the other end of the fifth capacitor is grounded, and the other end of the fifth resistor, the other end of the sixth resistor, the other end of the seventh resistor and the other end of the eighth resistor are all connected with the level conversion module.
9. A port testing device comprising the port testing circuit of any of claims 1-8.
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| CN202120352585.9U CN214585758U (en) | 2021-02-05 | 2021-02-05 | Port test circuit and device |
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| CN202120352585.9U CN214585758U (en) | 2021-02-05 | 2021-02-05 | Port test circuit and device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI835624B (en) * | 2023-04-12 | 2024-03-11 | 祥碩科技股份有限公司 | Testing system and testing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI835624B (en) * | 2023-04-12 | 2024-03-11 | 祥碩科技股份有限公司 | Testing system and testing method |
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