CN214504401U

CN214504401U - FPGA program online update failure recoverable circuit

Info

Publication number: CN214504401U
Application number: CN202120452879.9U
Authority: CN
Inventors: 韩健; 韦援丰
Original assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Current assignee: Ehiway Microelectronic Science And Technology Suzhou Co ltd
Priority date: 2021-03-02
Filing date: 2021-03-02
Publication date: 2021-10-26
Anticipated expiration: 2031-03-02

Abstract

A recoverable circuit for on-line update failure of an FPGA program enables the FPGA program to automatically realize program and state recovery after the on-line update failure of the FPGA program. The circuit comprises a main control FPGA, a first auxiliary circuit, a second auxiliary circuit and a third auxiliary circuit, wherein the first auxiliary circuit, the second auxiliary circuit and the third auxiliary circuit are respectively connected to the main control FPGA; the first auxiliary circuit executes the connection and automatic switching of the interfaces of the first FLASH storage chip and the second FLASH storage chip and the loading configuration pin of the main control FPGA; the second auxiliary circuit is connected with the first FLASH storage chip and the second FLASH storage chip, and the second auxiliary circuit executes the self reset of the main control FPGA and carries out delay storage on a reset signal; the third auxiliary circuit is connected with the upper computer through an external communication interface.

Description

FPGA program online update failure recoverable circuit

Technical Field

The utility model relates to a programmable logic device's technical field especially relates to a FPGA program online update failure recoverable circuit.

Background

An FPGA (Field-Programmable Gate Array) belongs to a semi-custom circuit in an application-specific integrated circuit, is a Programmable logic Array, and can effectively solve the problem that the number of Gate circuits of the original device is small. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core and a bottom layer embedded functional unit. The FPGA has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and is widely applied to the field of digital circuit design. The design process of the FPGA comprises algorithm design, code simulation, design and board machine debugging, wherein an algorithm framework is established by a designer and actual requirements, an EDA (electronic design automation) is used for establishing a design scheme or an HD (high definition) for compiling design codes, the code simulation is used for ensuring that the design scheme meets the actual requirements, finally, board level debugging is carried out, related files are downloaded into an FPGA chip by a configuration circuit, and the actual operation effect is verified.

In the field of FPGA chip application, online updating of a program of a device in which an FPGA is located is a common important function and requirement. The conventional program updating mode needs to open the equipment or the case shell, then the program is updated through the special programming device, online updating does not need to open the equipment or the case shell, the program can be updated directly through common external interfaces such as a serial port, the programming flow is simplified, and the efficiency is improved.

However, when the FPGA program is updated online, it is usually necessary for the original program in the Flash to support the FPGA to generate the external interface and the communication protocol, so as to erase and solidify the Flash program. In the process, if the Flash is not erased and solidified due to power failure and other reasons, the original program in the Flash is damaged, the equipment loses all functions, and the next online update cannot be performed. The reliability and the adaptability of the FPGA and the equipment where the FPGA is located are reduced. Therefore, how to automatically realize program and state recovery after failing to update the FPGA program online is a technical problem that needs to be solved by those skilled in the art at present.

Disclosure of Invention

For overcoming the defects of the prior art, the to-be-solved technical problem of the utility model is to provide a FPGA program online update failure recoverable circuit, it makes the FPGA program online update fail after, realizes program and state recovery automatically.

The FPGA program on-line update failure recoverable circuit comprises a main control FPGA, a first auxiliary circuit, a second auxiliary circuit and a third auxiliary circuit, wherein the first auxiliary circuit, the second auxiliary circuit and the third auxiliary circuit are respectively connected to the main control FPGA;

the first auxiliary circuit executes the connection and automatic switching of the interfaces of the first FLASH storage chip and the second FLASH storage chip and the loading configuration pin of the main control FPGA;

the second auxiliary circuit is connected with the first FLASH storage chip and the second FLASH storage chip, and the second auxiliary circuit executes the self reset of the main control FPGA and carries out delay storage on a reset signal;

the third auxiliary circuit is connected with the upper computer through an external communication interface.

The utility model discloses a first FLASH memory chip of second auxiliary circuit connection, second FLASH memory chip, the reset of main control FPGA self is carried out to the second auxiliary circuit, and carry out the time delay to the signal that resets and preserve, first FLASH memory chip is carried out to first auxiliary circuit, the connection and the automatic switch-over of second FLASH memory chip interface and main control FPGA's loading configuration pin, the third auxiliary circuit passes through external communication interface and host computer connection, even FLASH erases and the solidification is failed to accomplish, also can not destroy FLASH in have the procedure, the reliability and the adaptability of FPGA and place equipment have been promoted, therefore make FPGA procedure online update fail the back, realize procedure and state recovery automatically.

Drawings

Fig. 1 shows a schematic block diagram of an FPGA program online update failure recoverable circuit according to the present invention.

Fig. 2 shows a circuit diagram of a first auxiliary circuit according to the invention.

Fig. 3 shows a circuit diagram of a second auxiliary circuit according to the invention.

Detailed Description

As shown in fig. 1, the FPGA program online update failure recoverable circuit includes a main control FPGA, a first auxiliary circuit (auxiliary circuit 1), a second auxiliary circuit (auxiliary circuit 2), and a third auxiliary circuit (auxiliary circuit 3), where the first auxiliary circuit, the second auxiliary circuit, and the third auxiliary circuit are respectively connected to the main control FPGA;

the first auxiliary circuit executes the connection and automatic switching of the interfaces of a first FLASH storage chip (FLASH1) and a second FLASH storage chip (FLASH2) and the loading configuration pin of the main control FPGA;

Preferably, the main control FPGA includes an initial module and an update module, and the initial module includes: the device comprises an online updating unit, an updating state detection unit, a Flash interface switching unit and a self-resetting unit, wherein an updating module comprises the online updating unit;

the online updating unit executes: the method comprises the following steps of upper computer communication, communication instruction analysis, data protocol conversion, a Flash interface protocol and data programming;

the update state monitoring unit performs: a Flash interface protocol for reading and judging data;

the Flash interface switching unit switches the interface between the FPGA and the Flash between the first FLASH storage chip and the second FLASH storage chip, and the state comprises the following steps: an initial stage, a state monitoring stage, a monitoring completion stage and an online updating stage;

and the self-reset unit judges whether to output a reset signal to the third auxiliary circuit according to the output result of the updating state monitoring unit.

Preferably, as shown in fig. 2, the first auxiliary circuit includes a delay circuit and a hysteresis trigger circuit; the delay circuit comprises a first resistor R1(300 omega), a second resistor R2(10k omega) and a first capacitor C1(47n), and the hysteresis trigger circuit comprises an inverter S with a Schmitt trigger, a third resistor R3(10k omega) and a fourth resistor R4(10k omega); one end of a second resistor and the other end of the second resistor are grounded after the first capacitor is connected in parallel, the other end of the second resistor is connected between the first resistor and the phase inverter with the Schmitt trigger, the third resistor is connected with the input end of the phase inverter with the Schmitt trigger, the output of the phase inverter with the Schmitt trigger is connected with the reset input pin of the FPGA, and the fourth resistor is connected with the output of the phase inverter with the Schmitt trigger; the inverter with the Schmitt trigger is a chip 54LS 132;

any IO3 on the FPGA is selected to send a reset instruction signal to enter a first resistor of the delay circuit, and the delay circuit uses two resistors and a capacitor to realize the quick establishment and the slow release of a reset instruction high-level signal; then entering a hysteresis circuit, wherein the hysteresis circuit uses an inverter with a Schmitt trigger and two resistors and realizes level holding by utilizing the self threshold return difference; and finally, outputting the reset instruction after time delay and level holding to a reset input pin of the FPGA.

The first auxiliary circuit aims to realize self-reset of the FPGA, and a reset signal is required to be kept at a stable low level for a period of time in the reset process of the FPGA. The reset signal is output by the pin of the FPGA, and the pin level can change in the reset process, so that the circuit needs to have a memory holding function.

Preferably, as shown in fig. 3, the second auxiliary circuit includes two chips 54LS279, three chips 54LS132, and three resistors R5, R6, R7;

the input of each chip 54LS279 is connected with two arbitrary pins IO1 and IO2 of FPGA, the output is connected with the input of one chip 54LS132, and the fifth resistor and the seventh resistor are respectively connected with one chip

Pin IO1 corresponding to 54LS279 and pin IO2 corresponding to the other chip 54LS279, the sixth resistor is connected to the input of the third chip 54LS132, and the output of the third chip 54LS132 is connected to the inputs of the first chip 54LS132 and the second chip 54LS 132;

in Flash interface pins of the FPGA chip, three pins of CLK, SI and SO are simultaneously connected with corresponding pins of two Flash chips; an FCS chip selection pin and two arbitrary pins IO1 and IO2 of the FPGA enter the second auxiliary circuit, and CS1 and CS2 signals output by the second auxiliary circuit are respectively connected to CS pins of the two flashes; the FPGA switches the FPGA chip selection signal to the CS pins of the two flashes through different combinations of IO1 and IO2 output levels, and can keep the signal stable in the reset and loading processes of the FPGA.

The combination of IO1 and IO2 corresponds to chip select signals as shown in Table 1.

TABLE 1

Phases	IO1，IO2	FPGA interface switching to
			Initial stage	1，1	Flash1
State monitoring phase	1，0	Flash2
			Monitoring completion phase (flash2 has no complete program)	0，1	Flash1
Monitoring completion phase (flash2 with integrated program)	1，0	Flash2
			On-line update phase	1，0	Flash2

The second auxiliary circuit aims to realize the switching and holding function of chip selection signals of two Flash chips of the FPGA.

Preferably, the first FLASH memory chip is a default loading FLASH, and is programmed and cured by an equipment manufacturer in a jtag interface mode at a production debugging stage; and the second FLASH memory chip is an online updating program FLASH and is updated and solidified online through a serial port.

The present invention will be described in more detail below.

The equipment with the FPGA online updating requirement can be generally divided into a manufacturer production debugging stage and a user application stage;

production debugging phase

1) In the production debugging stage, a manufacturer uses a writer to solidify an FPGA initial program 'pro 1' into Flash in a mode of a Jtag interface and the like. Since the Flash1 chip select signal is asserted by default in the auxiliary circuit 1. "pro 1" will be loaded into Flash 1; the CS2 signal is invalid, and no program exists in the Flash 2;

2) after the device is powered on again, the FPGA reads the program 'pro 1' in the Flash1 because the default CS1 signal is valid. Thereafter the application phase is entered.

Application phase

3) And in the application stage, if an online updating program is needed, an external interface is used for connecting the upper computer and the equipment. The upper computer outputs a Flash2 updating instruction to the FPGA through an external communication tool and sends pro2 code stream data;

4) after recognizing the instruction, the FPGA updates the code stream data into Flash2 through an instruction parsing IP and a protocol conversion IP. Completing the process of the online updating program;

5) when the application stage program is loaded, the FPGA operation is executed according to the following sequence:

a) when the power is on, the default CS1 signal is valid, and the FPGA loads a program 'Pro 1' in the FLASH 1;

b) after the program is loaded, configuring the CS2 to be effective, and detecting the state of a specific flag bit in the FLASH2 through an update state monitoring unit, wherein if the address of 0x00 is 0x55AA, the flag is a write success flag;

c) if the operation detection flag bit of the b operation is valid, the FPGA executes the e operation and feeds back a curing completion signal to the upper computer; b, if the operation detection flag bit is invalid, executing the operation d and feeding back a solidification failure signal of the upper computer;

d) if the upgrading program does not exist in the Flash2 or the upgrading program fails, the state is recovered to the default CS1 valid state, and the FPGA continues to execute the 'Pro 1' application program.

e) The FPGA keeps the chip selection to be CS2, and a CS2 chip selection signal is locked by the auxiliary circuit 1 circuit;

f) the FPGA sends a reset instruction, and the reset instruction restarts the FPGA through the auxiliary circuit 2;

the FPGA loads a Pro2 code stream in the Flash2 and adopts a 'Pro 2' application program.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention in any form, and all the technical matters of the present invention are to make any simple modification, equivalent change and modification to the above embodiments, and still belong to the protection scope of the present invention.

Claims

1. A FPGA program on-line update failure recoverable circuit is characterized in that: the circuit comprises a main control FPGA, a first auxiliary circuit, a second auxiliary circuit and a third auxiliary circuit, wherein the first auxiliary circuit, the second auxiliary circuit and the third auxiliary circuit are respectively connected to the main control FPGA;

2. The FPGA program online update failure recoverable circuit of claim 1, wherein: the main control FPGA comprises an initial module and an updating module, wherein the initial module comprises: the device comprises an online updating unit, an updating state detection unit, a Flash interface switching unit and a self-resetting unit, wherein an updating module comprises the online updating unit;

3. The FPGA program online update failure recoverable circuit of claim 2, wherein:

the first auxiliary circuit comprises a delay circuit and a hysteresis trigger circuit; the delay circuit comprises a first resistor (R1), a second resistor (R2) and a first capacitor (C1), and the hysteresis trigger circuit comprises an inverter (S) with a Schmitt trigger, a third resistor (R3) and a fourth resistor (R4); one end of a second resistor and the other end of the second resistor are grounded after the first capacitor is connected in parallel, the other end of the second resistor is connected between the first resistor and the phase inverter with the Schmitt trigger, the third resistor is connected with the input end of the phase inverter with the Schmitt trigger, the output of the phase inverter with the Schmitt trigger is connected with the reset input pin of the FPGA, and the fourth resistor is connected with the output of the phase inverter with the Schmitt trigger; inverter with Schmitt trigger being chip 54LS132

4. The FPGA program online update failure recoverable circuit of claim 3, wherein: the second auxiliary circuit includes two chips 54LS279, three chips 54LS132, and three resistors (R5, R6, R7);

the input of each chip 54LS279 is connected with two arbitrary pins IO1 and IO2 of the FPGA, the output is connected with the input of one chip 54LS132, the fifth resistor and the seventh resistor are respectively connected with the pin IO1 corresponding to one chip 54LS279 and the pin IO2 corresponding to the other chip 54LS279, the sixth resistor is connected with the input of the third chip 54LS132, and the output of the third chip 54LS132 is connected with the input of the first chip 54LS132 and the input of the second chip 54LS 132;

5. The FPGA program online update failure recoverable circuit of claim 4, wherein: the first FLASH memory chip is a default loading FLASH, and is programmed and solidified by an equipment manufacturer in a JTAG interface mode at the production debugging stage; and the second FLASH memory chip is an online updating program FLASH and is updated and solidified online through a serial port.