CN214474989U

CN214474989U - Ground high-speed signal VPX acquisition processing playback board

Info

Publication number: CN214474989U
Application number: CN202120959309.9U
Authority: CN
Inventors: 吴东; 荣彬杰; 夏思宇
Original assignee: Chengdu Punuo Technology Co ltd
Current assignee: Chengdu Punuo Technology Co ltd
Priority date: 2021-05-07
Filing date: 2021-05-07
Publication date: 2021-10-22
Anticipated expiration: 2031-05-07

Abstract

The utility model discloses a ground high-speed signal VPX acquisition processing playback board, which comprises a VPX connector, an FPGA module, a DSP processing unit, a power module and a clock module; the VPX connector is provided with an A/D conversion input interface, a D/A conversion output interface, a low-frequency connector and a radio-frequency connector which are connected with the FPGA module; the FPGA module is connected with the DSP processing unit, the power supply module and the clock module. The utility model discloses have characteristics such as better high-speed transmission and EMC, realize the high reliability of data synchronous transmission under the high-speed operational environment of hardware, improved data synchronous transmission efficiency.

Description

Ground high-speed signal VPX acquisition processing playback board

Technical Field

The utility model relates to a signal acquisition technical field especially relates to return board is handled in high-speed signal VPX acquisition on ground.

Background

When the high-speed signal acquisition processing equipment is designed, characteristics such as high-speed transmission, EMC and the like are fully considered, optimization design is carried out, and the existing product cannot meet the reliability requirement of a hardware platform under a high-speed working environment.

The existing acquisition and processing equipment has low data processing speed, large noise interference and low data synchronous transmission efficiency.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the above problems and provide a ground high-speed signal VPX acquisition processing playback board, which comprises a VPX connector, an FPGA module, a DSP processing unit, a power module and a clock module; the VPX connector is provided with an A/D conversion input interface, a D/A conversion output interface, a low-frequency connector and a radio-frequency connector which are connected with the FPGA module; the FPGA module is connected with the DSP processing unit, the power supply module and the clock module.

Preferably, the low-frequency connector comprises a JTAG interface, a debug interface, an LVDS low-speed interface, an LVTTL interface, a memory interface, an external data interaction high-speed interface, and an optical fiber interface; the radio frequency connector includes an SSMA connector.

Preferably, a bidirectional isolator is connected between the LVTTL interface and the FPGA module.

Preferably, the FPGA module is provided with a GTY interface; the DSP processing unit is provided with an SRIO interface and a HyperLink interface; the FPGA module is connected with the SRIO interface, the HyperLink interface and the VPX connector.

Preferably, the power module comprises a direct current power supply, at least one buck regulator and at least one buck converter; the direct current power supply is connected with the FPGA module through the step-down voltage stabilizer; the direct current power supply is connected with the DSP processing unit through the step-down voltage stabilizer; the DC power supply is connected with the VPX connector through a voltage reduction converter.

Preferably, the DSP processing unit comprises a DSP processor, an EEPROM memory and a PROM memory; the EEPROM memory and the PROM memory are respectively connected with the DSP processor.

Preferably, the clock module comprises a clock generator and a plurality of clock buffer chips; the clock generator is connected with the FPGA module through the clock buffer chip.

Preferably, a temperature sensor is further included; the temperature sensor is connected with the FPGA module through an A/D conversion input interface.

The beneficial effects of the utility model reside in that: the utility model discloses have characteristics such as better high-speed transmission and EMC, realize the high reliability of data synchronous transmission under the high-speed operational environment of hardware, improved data synchronous transmission efficiency.

Drawings

FIG. 1 is a schematic diagram of the present invention;

FIG. 2 is a schematic diagram of an embodiment of the present invention;

FIG. 3 is a schematic diagram of a power module;

fig. 4 is a schematic diagram of a clock module.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings:

as shown in fig. 1, the utility model discloses a ground high-speed signal VPX acquisition processing playback board, including VPX connector, FPGA module, DSP processing unit, power module and clock module; the VPX connector is provided with an A/D conversion input interface, a D/A conversion output interface, a low-frequency connector and a radio-frequency connector which are connected with the FPGA module; the FPGA module is connected with the DSP processing unit, the power supply module and the clock module.

The FPGA module is connected with the DSP processing unit. The FPGA model: XCZU28DR-2FFVG 1517I; the DSP model: TMS320C6678 acppa. The FPGA module, the DSP processing unit and the clock module realize clock homology.

As shown in fig. 2, the FPGA module is connected to the a/D conversion input interface, the D/a conversion output interface, the low frequency connector, and the radio frequency connector. The low-frequency connector comprises a JTAG interface, a debugging test interface, an LVDS low-speed interface and a high-speed interface. The radio frequency connector is used for clock signal input. The VPX backboard is connected with an A/D conversion input interface, a D/A conversion output interface, a low-frequency connector and a radio-frequency connector. And a bidirectional isolator is connected between the LVTTL interface and the FPGA module.

The FPGA module is provided with a GTY interface; the DSP processing unit is provided with an SRIO interface and a HyperLink interface; the FPGA module is connected with the SRIO interface, the HyperLink interface and the VPX connector.

Interface type of VPX backplane:

a power supply interface: 12V and 5V; the high-speed interface between the high-speed processing board and the control board has the interface speed of more than or equal to 40 Gbps; the LVDS interface between the high-speed processing board and the control board receives and transmits 8 pairs of signals; 12 LVTTL interfaces between the high-speed processing board and the control board; 40 LVTTL interfaces between high-speed processing boards and frequency synthesis boards (17 paths for uplink frequency control, 17 paths for downlink frequency control, 3 paths for digital clock control and 3 paths for backup); the LVTTL interfaces between the high-speed processing boards and the channel boards are 12 (filter bank control); and 1, a clock radio frequency interface from the high-speed processing board to the frequency synthesis board.

As shown in fig. 3, the power module includes a dc power supply, at least one buck regulator, and at least one buck converter; the direct current power supply is connected with the FPGA module through the step-down voltage stabilizer; the direct current power supply is connected with the DSP processing unit through the step-down voltage stabilizer; the DC power supply is connected with the VPX connector through a voltage reduction converter. The LTC3773 chip, the TPS54620 and the TLV62130 all have independent EN pins so as to carry out power-on timing of the whole board.

As shown in fig. 4, the clock module includes a clock generator and a plurality of clock buffer chips; the clock generator is connected with the FPGA module through the clock buffer chip. Outputting a plurality of kinds of clocks by adopting a chip 844N255, wherein 100MHz adopts a chip ICS854104 to carry out FANOUT, and outputting 4 groups of 100MHzLVDS clocks; the 156.25MHz clock adopts an ICS854104 to carry out FANOUT, and 4 groups of LVDS clocks are output; the 50MHz and 125MHz clocks of the ICS844N255 direct frequency multiplication output are directly connected into the FPGA.

The radio frequency output signal can realize:

(1) channel 1 output signal characteristics: signal frequency: DC-2400 MHz; output level: 2 + -0.5 dBm; outputting standing-wave ratio: the output standing wave ratio is not more than 1.5(50 omega system test);

(2) channel 2 output signal characteristics: signal frequency: DC-2400 MHz; output level: 2 + -0.5 dBm; outputting standing-wave ratio: the output standing wave ratio is not more than 1.5(50 omega system test).

Reference clock input signal characteristics: center frequency: the method can be configured; input level: +5 dBm; inputting standing-wave ratio: the input standing wave ratio is not more than 1.5(50 omega system test); the input clock needs to be configured according to needs in the circuit, and is respectively sent to 2A/D devices, 2D/A devices and 2 main FPGAs: input clock of a/D device: configurable, up to 4.096 GHz; input clock of D/a device: configurable, up to 6.544 GHz; input clock of FPGA: two input clocks per FPGA (except for fixed 100M clocks) can be configured.

Sampling circuit characteristics: effective quantization bit number: more than or equal to 9 bit; SFDR: more than or equal to 50dBc (in a full frequency band); flatness in the band: less than or equal to 1.3 dB; the AD should support 1:1/1:2/1:4DEMUX mode sampling; HD 2: more than or equal to 68dBc (in a full frequency band); HD 3: more than or equal to 65dBc (in a full frequency band); IMD 3: ≧ 50dBc (full band).

D/a conversion circuit characteristics: SFNR: not less than 45dBc (full frequency band); DA should support 2:1/4:1MUX mode; IMD 3: not less than 65 dBc; out-of-band suppression: > 40dBc @800 MHz; and (3) inhibiting the clutter in the band: more than 45 dBc; EVM: < 3%. Harmonic suppression: > 40 dBc.

The utility model discloses have characteristics such as better high-speed transmission and EMC, realize the high reliability of data synchronous transmission under the high-speed operational environment of hardware, improved data synchronous transmission efficiency.

The technical scheme of the utility model is not limited to the restriction of above-mentioned specific embodiment, all according to the utility model discloses a technical scheme makes technical deformation, all falls into within the protection scope of the utility model.

Claims

1. The ground high-speed signal VPX acquisition processing playback board is characterized by comprising a VPX connector, an FPGA module, a DSP processing unit, a power supply module and a clock module; the VPX connector is provided with an A/D conversion input interface, a D/A conversion output interface, a low-frequency connector and a radio-frequency connector which are connected with the FPGA module; the FPGA module is connected with the DSP processing unit, the power supply module and the clock module.

2. The ground high-speed signal VPX acquisition processing playback board of claim 1, wherein the low frequency connector comprises a JTAG interface, a debugging interface, an LVDS low-speed interface, an LVTTL interface, a memory interface, an external data interaction high-speed interface and an optical fiber interface; the radio frequency connector includes an SSMA connector.

3. The ground high-speed signal VPX acquisition and processing playback board of claim 2, wherein a bidirectional isolator is connected between the LVTTL interface and the FPGA module.

4. The ground high-speed signal VPX acquisition processing playback board of claim 1, wherein the FPGA module is provided with a GTY interface; the DSP processing unit is provided with an SRIO interface and a HyperLink interface; the FPGA module is connected with the SRIO interface, the HyperLink interface and the VPX connector.

5. The ground high-speed signal VPX acquisition and processing playback board of claim 1, wherein the power module comprises a DC power supply, at least one buck regulator, at least one buck converter; the direct current power supply is connected with the FPGA module through the step-down voltage stabilizer; the direct current power supply is connected with the DSP processing unit through the step-down voltage stabilizer; the DC power supply is connected with the VPX connector through a voltage reduction converter.

6. The ground high-speed signal VPX acquisition and processing playback board of claim 1, wherein the DSP processing unit comprises a DSP processor, an EEPROM memory and a PROM memory; the EEPROM memory and the PROM memory are respectively connected with the DSP processor.

7. The ground high-speed signal VPX acquisition processing playback board of claim 1, wherein the clock module comprises a clock generator and a plurality of clock buffer chips; the clock generator is connected with the FPGA module through the clock buffer chip.

8. The ground high-speed signal VPX acquisition and processing playback board of claim 1, further comprising a temperature sensor; the temperature sensor is connected with the FPGA module through an A/D conversion input interface.