CN214381427U

CN214381427U - Digital baseband processing board

Info

Publication number: CN214381427U
Application number: CN202120766355.7U
Authority: CN
Inventors: 陈彬; 赵胜; 韩伯彦
Original assignee: Chengdu Dingwave Electronic Technology Co ltd
Current assignee: Chengdu Dingwave Electronic Technology Co ltd
Priority date: 2021-04-14
Filing date: 2021-04-14
Publication date: 2021-10-08
Anticipated expiration: 2031-04-14

Abstract

The utility model relates to a digital baseband processing board, which comprises a control module, a signal processing module, a clock module, a peripheral interface module and a power supply device; the control module is connected with the signal processing module; the peripheral interface module is connected with the control module and the signal processing module; the clock module provides an OCXO clock source and an external reference clock source to the control module and the signal processing module; the power supply device is connected with the control module, the signal processing module and the clock module through a VPX interface or an ATX interface to supply power. The utility model discloses a 6U VPX framework solves the heat dissipation of high density integrated circuit board and structural reliability problem. 3 FMC interfaces are adopted, and the expandability is high. And integrating a Zynq main control unit and a digital signal processing unit FPGA. An on-board multi-channel fiber optic interface. The digital baseband processing board with small volume, multiple channels and low power consumption is realized.

Description

Digital baseband processing board

Technical Field

The utility model relates to a signal processing technology field especially relates to a board is handled to digital baseband.

Background

The existing wireless communication system adopts a distributed base station architecture, namely the whole base station is divided into a baseband processing unit (BBU) and a radio frequency front end unit (RRU). The BBU is mainly used for completing functions of baseband processing, main control, transmission, clock and the like, the RRU is mainly used for completing functions of mutual conversion and the like between digital baseband signals and radio frequency signals, and an optical fiber interface is generally adopted between the BBU and the RRU.

The traditional baseband processing unit mainly comprises a digital signal processing unit, a clock unit, a main control unit and an optical fiber interface unit, and has the advantages of large volume, high power consumption and poor expandability.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art's shortcoming, provide a digital baseband processing board, solved the problem that traditional baseband processing unit exists.

The purpose of the utility model is realized through the following technical scheme: a digital baseband processing board comprises a control module, a signal processing module, a clock module, a peripheral interface module and a power supply device; the control module is connected with the signal processing module; the peripheral interface module is connected with the control module and the signal processing module; the clock module provides an OCXO clock source and an external reference clock source to the control module and the signal processing module; the power supply device is connected with the control module, the signal processing module and the clock module through a VPX interface or an ATX interface to supply power.

Further, the FMC interface module comprises an FMC + interface and an FMC interface; the FMC + interface is connected with the signal processing module to realize control, data transceiving and signal processing of the FMC + sub-plate; the FMC interface is connected with the control module, and control, data receiving and transmitting and signal processing of the FMC daughter board card are achieved.

Furthermore, the control module and the signal processing module are respectively provided with an Ethernet interface, the Ethernet PHY is connected with the control module and the signal processing module through an RGMII interface, and an Ethernet RJ45 interface connected to the outside of the board is provided for the control module and the signal processing module through a transformer.

Further, the peripheral interface module comprises a QSFP + optical connector and a J30J connector; the J30J connector is connected with the control module and the signal processing module after interface level conversion; and the GSFP + optical port connector is connected with the signal processing module.

Furthermore, the clock module comprises an onboard OCXO clock source, an external reference clock source SMA, an analog switch and a clock distributor; the onboard OCXO clock source and the external reference clock source SMA are connected with the analog switch, and are connected to the clock distributor after being switched by the analog switch, so that reference clocks are provided for the FMC interface, the FMC + interface, the control module and the signal processing module.

Further, the power supply device comprises a VPX interface or a power interface and a power module; the VPX interface or the power supply interface outputs 12V direct current to the FMC interface, the FMC + interface and the power supply module; and the power supply module is connected with the control module, the signal processing module and the clock module to realize power supply.

The utility model has the advantages of it is following:

1. and a 6U VPX framework is adopted, so that the problems of heat dissipation and structural reliability of the high-density board card are solved.

2. 3 FMC interfaces are adopted, and the expandability is high.

3. And integrating a Zynq main control unit and a digital signal processing unit FPGA.

4. An on-board multi-channel fiber optic interface.

5. The digital baseband processing board with small volume, multiple channels and low power consumption is realized.

6. Two gigabit Ethernet interfaces are provided, and a board management interface and a high-speed data transmission interface are provided.

Drawings

Fig. 1 is a schematic structural view of the present invention;

FIG. 2 is a schematic diagram of an Ethernet interface connection;

FIG. 3 is a schematic diagram of a QSFP + optical port connector;

FIG. 4 is a schematic diagram of a debug interface;

FIG. 5 is a schematic diagram of a clock module;

figure 6 is a schematic diagram of an OCXO control link;

FIG. 7 is a power supply topology;

fig. 8 is a schematic structural diagram of a power module.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application provided below in connection with the appended drawings is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application. The invention is further described below with reference to the accompanying drawings.

As shown in fig. 1, the present invention relates to a digital baseband processing board, which comprises a control module, a signal processing module, a clock module, a peripheral interface module and a power supply device; the control module is connected with the signal processing module; the peripheral interface module is connected with the control module and the signal processing module; the clock module provides an OCXO clock source and an external reference clock source to the control module and the signal processing module; the power supply device is connected with the control module, the signal processing module and the clock module through a VPX interface or an ATX interface to supply power.

Wherein, the control module: the cfgFPGA chip with the model number of XC7Z045 is mainly used for whole-board control, Ethernet JTAG, clock control and the like. The signal processing module: the FPGA chip with the model of XC7V690T is mainly responsible for whole-board signal processing, data exchange and the like. Peripheral interface: and high-speed data interfaces such as QSFP + optical interfaces, RJ45 and the like and control interfaces are provided. FMC + interface: two FMC + standard interfaces are provided and connected to 690T, and the FMC + daughter board card is used for achieving control, data receiving and sending and signal processing. FMC interface: and the reserved FMC standard interface is connected to XC7Z045 and is used for realizing control, data transceiving and signal processing of the FMC daughter board card. A clock module: and an OCXO clock source is provided, an external reference clock source is supported, and clocks required by work are provided for the FPGA, the optical port and other parts on the board. A power supply device: the power supply supplies power through a VPX interface or an ATX 4PIN interface, and at present, a 12V direct-current power supply is mainly used for converting the voltage required by each electric chip on a board and supplying power for FMC +, FMC and the like. And both the cfgFPGA chip and the 690T FPGA chip are configured with a Flash memory chip and a DDR3 memory.

Wherein, the FMC + and FMC interface standards provide 12V and 3.3V supply voltages, and V is provided_ADJLevel voltage for the interface. In the design, 12V voltage is directly provided by a power module, and 3.3V power supply voltage actually supplies 3.6V and V_ADJThe voltage of 1.8V is provided, and the user can directly use the voltage as the interface level voltage.

As shown in fig. 2, 690T and XC7Z045 are each an ethernet interface. The Ethernet PHY provides 690T and XC7Z045 with an Ethernet interface connected to the outside of the board, the gigabit Ethernet PHY is connected with XC7V690T through RGMII, and a data line of the Ethernet interface is connected to 690T; the gigabit ethernet PHY of ZYNQ is connected to the PS via RGMII.

As shown in fig. 3, in the form of QSFP + connectors, the QSFP + connectors are directly connected to 690T GTH, both QSFP + connectors adopt X4, a data part protocol can run Aurora or gigabit ethernet, an I2C configuration is configured by a PL part, a single channel has a typical transmission rate of 10.3125Gbps, and reference clocks of the QSFP + connectors are selectable, namely PLL and external crystal oscillator.

As shown in fig. 4, UART, GPIO and JTAG debug interfaces are reserved on two FPGA chips as external extension interfaces, the external extension interfaces are connected to the outer end of the baseband processing board, and are reserved for a user to debug and control external devices, and J30J connectors are adopted, so that there are 31 pins in total; wherein, 8 are defined as general GPIO ports: the four terminals are connected with XC7V690T and XC7Z045 respectively in a group, a user can control DIR through software to realize the GPIO input and output direction, and the level of a GPIO interface is 3.3 LVCMOS; 6 serial ports defined as RS232 level: two groups of PL terminal and PS terminal connected to XC7Z045, wherein the PS terminal is a fixed connection, RX can be connected to MIO30, and TX can be connected to MIO 31; one set is connected to XC7V690T for debug; 12 JTAG debug interfaces: JTAG debug interfaces for XC7V690T and XC7Z 045; the remaining 5 lines are referenced to ground.

As shown in fig. 5, there are two clock reference sources of the clock module, and a user can select the clock reference sources according to needs, where one clock source is an onboard OCXO and the other clock source is an external reference clock input. The clock of the baseband board is divided into three parts, one part is used for distributing the clock used for signal processing, one part is used for distributing the clock used for normal operation of the baseband board, the other part is used for distributing the clock used for 690T FPGA and cfgFPGA transceivers, and after the clock is switched through an analog switch with the model number of HMC349AMS8G, the clock provides a reference clock for PLL, FMC + and FMC through HMC 987.

As shown in fig. 6, the OCXO is used as a unique high-stability clock source on the board, and the OCXO output needs to be converted into a differential LVDS level and then sent to a clock selector, so that the output frequency can be finely adjusted by off-chip control. The adjustable range of the OCXO is +/-0.5 ppm, and the adjustable clock range is +/-5 Hz because the output frequency of the OCXO is 10 MHz. The adjustment of the OCXO frequency is controlled by using voltage, the voltage control range is 0-3.3V, and the central frequency is 1.65V. A serial DAC, AD5061BRJZ from ADI, was used as the output to adjust the OCXO. For the precision of assurance control, the utility model provides a reference voltage uses the dedicated reference voltage chip of TI, REF 5025. Since there is no 1.65V reference voltage chip, a 2.5V reference voltage is temporarily used in this design. The REF50XX series chip Pin to Pin is compatible, and chips with different reference voltages can be welded according to requirements. The DAC is connected to XC7Z045 using an SPI interface, using a 3.3V supply.

As shown in fig. 7 and 8, the whole board power supply is powered by VPX direct current 12V or an external power supply socket. Power source interface provides the required power on the board for digital baseband processing board, detain the cardboard for FMC +, FMC detains the cardboard and provides 12V power simultaneously, complete machine heat dissipation power is supplied power by quick-witted case, power according to 690T and XC7Z045 is gone up the electric time sequence requirement, and XC7Z045 PS _ POR _ B postpones XC7Z045 20ms later through TPS3808G01D behind VCCO _3.3V power, and through TPS3808G01D control delay power-on time. LMZ31530 is DC converter, ADP5054 bit voltage reducing regulator, and LTM4644 bit voltage reducing regulator.

The utility model discloses consider the heat distribution, put the temperature acquisition chip respectively in 690T and XC7Z045 each one slice, and measure the position temperature and transmit data to XC7Z045 and handle. The FPGA can be used for adjusting the difference of the LED indicating information, and four LED indicating lamps are reserved on the board card.

The utility model discloses digital baseband handles the board and uses as the BBU, integrated main control unit (Zynq SOC), digital signal processing unit (FPGA), optical fiber interface (QSFP +), FMC interface (extension interface), board year clock. And the VPX 6U structure size is adopted, so that the reliability of the equipment is ensured. And 3 FMC interfaces are adopted, so that the expandability of the baseband processing board is ensured, and the baseband processing board can be used in small-size, multi-channel and other scenes. Zynq SOC is adopted as a main control unit on the 6U VPX single board, and a control and data interface with the digital signal processing unit is provided, so that the main control single board is saved, and the system complexity and the volume power consumption are greatly reduced. Meanwhile, the Zynq main control unit and the digital signal processing unit FPGA respectively provide a gigabit Ethernet interface for system management and data transmission interfaces. In recent years, the improvement of the FPGA technology makes it possible to integrate large-scale digital signal processing resources on a high-density board card. And the VPX framework is adopted, so that the problems of system heat dissipation and structural reliability are solved.

The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A digital baseband processing board, characterized by: the device comprises a control module, a signal processing module, a clock module, a peripheral interface module and a power supply device; the control module is connected with the signal processing module; the peripheral interface module is connected with the control module and the signal processing module; the clock module provides an OCXO clock source and an external reference clock source to the control module and the signal processing module; the power supply device is connected with the control module, the signal processing module and the clock module through a VPX interface or an ATX interface to supply power.

2. A digital baseband processing board according to claim 1, wherein: the FMC interface module comprises an FMC + interface and an FMC interface; the FMC + interface is connected with the signal processing module to realize control, data transceiving and signal processing of the FMC + sub-plate; the FMC interface is connected with the control module, and control, data receiving and transmitting and signal processing of the FMC daughter board card are achieved.

3. A digital baseband processing board according to claim 1, wherein: the control module and the signal processing module are respectively provided with an Ethernet interface, the Ethernet PHY is connected with the control module and the signal processing module through an RGMII interface, and an Ethernet RJ45 interface connected to the outside of the board is provided for the control module and the signal processing module through a transformer.

4. A digital baseband processing board according to claim 1, wherein: the peripheral interface module comprises a QSFP + optical port connector and a J30J connector; the J30J connector is connected with the control module and the signal processing module after interface level conversion; and the GSFP + optical port connector is connected with the signal processing module.

5. A digital baseband processing board according to claim 2, wherein: the clock module comprises an onboard OCXO clock source, an external reference clock source SMA, an analog switch and a clock distributor; the onboard OCXO clock source and the external reference clock source SMA are connected with the analog switch, and are connected to the clock distributor after being switched by the analog switch, so that reference clocks are provided for the FMC interface, the FMC + interface, the control module and the signal processing module.

6. A digital baseband processing board according to claim 2, wherein: the power supply device comprises a VPX interface or a power interface and a power module; the VPX interface or the power supply interface outputs 12V direct current to the FMC interface, the FMC + interface and the power supply module; and the power supply module is connected with the control module, the signal processing module and the clock module to realize power supply.