CN214380826U - Power-on and power-off time sequence control circuit of GaN power amplifier - Google Patents
Power-on and power-off time sequence control circuit of GaN power amplifier Download PDFInfo
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- CN214380826U CN214380826U CN202120404093.XU CN202120404093U CN214380826U CN 214380826 U CN214380826 U CN 214380826U CN 202120404093 U CN202120404093 U CN 202120404093U CN 214380826 U CN214380826 U CN 214380826U
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Abstract
The utility model discloses a power-on and power-off time sequence control circuit of a GaN power amplifier, which comprises a main control chip, and a grid voltage switch control circuit and a leakage voltage switch control circuit which are connected with the main control chip; the grid voltage switch control circuit comprises a grid voltage logic control unit circuit and a grid voltage switch unit circuit which are connected, the grid voltage logic control unit circuit is connected with a main control chip and grid voltage control signals output by the system complete machine, and the grid voltage switch unit circuit is connected with a grid electrode; the leakage voltage switch control circuit comprises a leakage voltage logic control unit circuit and a leakage voltage switch unit circuit which are connected, the leakage voltage logic control unit circuit is connected with the main control chip, and the leakage voltage switch unit circuit is connected with the drain electrode; and a grid voltage detection unit circuit is also connected between the grid and the drain voltage logic control unit circuit. The utility model discloses can accomplish gaN power amplifier's grid and last electric power down time sequence control of drain electrode, low cost to can still effectively protect gaN power amplifier not burnt out when other devices are unusual on the circuit.
Description
Technical Field
The utility model belongs to the technical field of the electron, concretely relates to power-on and power-off sequential control circuit on GaN power amplifier.
Background
With the development of modern communication technology, the requirements on the core component power amplifier in the communication system are higher and higher: high power, high efficiency, large bandwidth, low cost and miniaturization. The conventional LDMOS power amplifier has not been able to meet the above requirements. Due to the improvement of material technology and manufacturing process, the GaN power amplifier with large bandwidth, high power and high efficiency is produced and applied to a communication system. Because the grid electrode works in a negative pressure state and has strict requirements on power-on and power-off time sequences, the GaN power amplifier is easy to damage under the condition of improper circuit design or use. Therefore, the design of the power-on and power-off timing control circuit for the gate and the drain of the GaN power amplifier is particularly important.
At present, a commonly used scheme in the industry is to use a special negative voltage chip to control the power-on and power-off time sequence of the GaN power amplifier, but the scheme is high in cost and cannot effectively avoid the condition that the GaN power amplifier is burnt down due to time sequence abnormality caused by abnormality of other devices on a circuit.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a power-down time sequence control circuit on gaN power amplifier, the power-down time sequence control on the grid of completion gaN power amplifier and drain electrode to still can effectively protect gaN power amplifier not burnt out when other devices are unusual on the circuit.
In order to solve the technical problem, the utility model discloses the technical scheme who adopts is:
a power-on and power-off time sequence control circuit of a GaN power amplifier comprises a main control chip, and a grid voltage switch control circuit and a leakage voltage switch control circuit which are connected with the main control chip;
the grid voltage switch control circuit comprises a grid voltage logic control unit circuit and a grid voltage switch unit circuit which are connected, the grid voltage logic control unit circuit is connected with a main control chip and a grid voltage control signal output by the system complete machine, and the grid voltage switch unit circuit is connected with a grid electrode of the GaN power amplifier;
the leakage voltage switch control circuit comprises a leakage voltage logic control unit circuit and a leakage voltage switch unit circuit which are connected, the leakage voltage logic control unit circuit is connected with the main control chip, and the leakage voltage switch unit circuit is connected with the drain electrode of the GaN power amplifier; and a grid voltage detection unit circuit is also connected between the grid of the GaN power amplifier and the leakage voltage logic control unit circuit.
Furthermore, the grid voltage switch control circuit also comprises a grid voltage generation unit circuit, and the grid voltage generation unit circuit is connected with the grid voltage switch unit circuit.
Furthermore, a DAC module is arranged in the main control chip and is connected with the grid voltage generation unit circuit.
Furthermore, an inverse proportion amplifier is arranged in the grid voltage generation unit circuit to invert the positive voltage value output by the DAC module.
Furthermore, the sequential control circuit also comprises a voltage conversion unit circuit which converts the power supply voltage input by the whole system into the working voltage of the sequential control circuit.
Furthermore, the negative voltage of the voltage conversion unit circuit has a power-down delay function.
Furthermore, the time sequence control circuit also comprises a power supply which provides the working voltage of the time sequence control circuit.
Further, the main control chip is an MCU.
The utility model has the advantages that: the utility model discloses a power-on and power-off sequential control circuit of GaN power amplifier can accomplish power-on and power-off sequential control on GaN power amplifier's grid and the drain electrode, low cost to can still effectively protect GaN power amplifier not burnt out when other devices are unusual on the circuit.
Drawings
Fig. 1 is the power-on and power-off sequential control circuit diagram of the GaN power amplifier of the present invention.
Fig. 2 is a circuit diagram of GaN power amplifier gate bias voltage generation and switch control.
Fig. 3 is a circuit diagram of GaN power amplifier drain bias voltage timing control and switching.
Detailed Description
The invention will be further described with reference to the accompanying drawings:
the utility model discloses a power-on and power-off time sequence control circuit is applicable to power-on and power-off time sequence control of GaN power amplifier. The time sequence control circuit reduces the cost of products by using a universal negative pressure chip, and realizes that the negative pressure of the grid electrode of the GaN power amplifier is biased firstly when the power is on under any condition, and the positive pressure of the drain electrode is biased after the negative pressure is stabilized; when power is off, the positive voltage of the drain electrode of the GaN power amplifier is powered off firstly, and the negative voltage of the grid electrode is powered off again after the positive voltage of the drain electrode is powered off to a safe range; and the GaN power amplifier can be effectively protected from being burnt out when devices in the circuit work abnormally.
The power-on and power-off time sequence control circuit of the GaN power amplifier of the embodiment of the utility model comprises a main control chip, a grid voltage switch control circuit and a leakage voltage switch control circuit, wherein the grid voltage switch control circuit and the leakage voltage switch control circuit are connected with the main control chip as shown in figure 1;
the grid voltage switch control circuit comprises a grid voltage logic control unit circuit 2 and a grid voltage switch unit circuit which are connected, the grid voltage logic control unit circuit is connected with a main control chip and grid voltage control signals output by the whole system, and the grid voltage switch unit circuit is connected with a grid electrode of the GaN power amplifier;
the leakage voltage switch control circuit comprises a leakage voltage logic control unit circuit 1 and a leakage voltage switch unit circuit which are connected, the leakage voltage logic control unit circuit is connected with the main control chip, and the leakage voltage switch unit circuit is connected with the drain electrode of the GaN power amplifier; and a grid voltage detection unit circuit is also connected between the grid of the GaN power amplifier and the leakage voltage logic control unit circuit.
Further, the grid voltage switch control circuit also comprises a grid voltage generating unit circuit which is used for generating bias voltage (negative voltage) required by the grid electrode of the GaN power amplifier; the grid voltage can be generated by the power supply conversion unit circuit and the switch control can be realized by the grid voltage switch unit circuit as the drain electrode.
Furthermore, the sequential control circuit also comprises a power supply conversion unit circuit which is used for converting the power supply voltage input by the whole system into the working voltage of the sequential control circuit; in addition, a power supply can be independently arranged for the sequential control circuit, and the working voltage required by the sequential control circuit can be directly provided without power supply conversion.
Each unit circuit mainly completes the following functions:
(1) power conversion unit circuit: the power supply voltage input by the system is converted into +5V, +3.3V and-5V voltages required by the work of the time sequence control circuit, and the converted power supply meets the requirements of corresponding devices on power supply quality and loading capacity. Meanwhile, the-5V power supply meets the requirement of power failure delay, and ensures that the positive voltage of the drain electrode of the GaN power amplifier is firstly powered off and the negative voltage of the grid electrode is then powered off when abnormal power failure occurs.
(2) A main control chip: the master control chip monitors and processes the circuit state and exception, and controls the grid voltage of the GaN power amplifier through the DAC of the master control chip, so that the normal work of the GaN power amplifier is ensured.
(3) Grid voltage and drain voltage logic control unit circuit: and logic requirements are realized, gate voltage and leakage voltage switch logic is controlled, and the GaN power amplifier is ensured to meet power-on and power-off logic requirements.
(4) Gate voltage generation unit circuit: and generating a bias voltage (negative voltage) required by the grid electrode of the GaN power amplifier under the control of the main control chip.
(5) Grid voltage switch unit circuit: and the GaN power amplifier grid voltage switch control is realized, and the switch control signal is controlled by the system complete machine and the main control chip through a grid voltage logic control unit circuit.
(6) Gate voltage detection unit circuit: and detecting whether the grid voltage is normally supplied to the grid electrode of the GaN power amplifier or not, and supplying the detection result to the drain voltage switch logic control unit. And ensuring that the grid electrode is electrified firstly and the drain electrode is electrified later in the electrifying process.
(7) Leakage voltage switch unit circuit: and the GaN power amplifier realizes the switch control of the drain voltage, and the switch control signal is controlled by the main control chip and the grid voltage detection result through the leakage voltage logic control unit circuit. The unit circuit power-down time meets the power-down time sequence requirement, is 10 times faster than the grid power-down time, and provides enough time delay guarantee for the power-down under abnormal conditions.
To better illustrate the power-on/power-off timing control circuit of the GaN power amplifier of the present invention, as shown in fig. 2 and 3, the present invention further provides a specific circuit implementation scheme. Fig. 2 includes a main control chip, a gate voltage logic control unit circuit, a partial leakage voltage logic control unit circuit, a gate voltage generation unit circuit, and a gate voltage switch unit circuit in a control block diagram. Fig. 3 includes a power conversion unit-negative voltage generation circuit, a gate voltage detection unit circuit, a remaining part leakage voltage logic control unit circuit, and a leakage voltage switch unit circuit.
As shown in fig. 2, since the main control chip and the gate voltage logic control unit include many contents irrelevant to the present invention, in order to better understand the internal logic relationship of these parts, these two parts are shown in the form of a logic block diagram. The main control chip mainly completes the following functions:
(1) the grid bias voltage which can be adjusted, stored and subjected to real-time temperature compensation is provided, and the scheme adopts a DAC (positive voltage) of the MCU. As shown in fig. 2, "DAC 1" is the positive voltage value of the gate bias voltage output by the MCU.
(2) Controlling the turn-on and turn-off of the gate bias voltage and the drain bias voltage. As shown in fig. 2, the "DrainVolt-EN-MCU" signal output by the MCU controls the on and off of the drain bias voltage (high level on, low level off), and the "PA-EN-MCU" controls the on and off of the gate bias voltage (high level on, low level off).
(3) The functions of the gate bias voltage detection, comparison and abnormal alarm turn-off can be realized by a comparator of the MCU, and the comparator is internally provided with an adjustable reference. The Vg-Det signal is a grid voltage detection signal and is input to a comparison input end of the MCU, and an internal adjustable reference can be set to be a reasonable value according to application requirements. When the input voltage is abnormal and is lower than the reference voltage, the comparator outputs a signal CMP-EN to output a low level, and a corresponding protection mechanism is started; otherwise, outputting high level and working normally.
In the logic control unit circuit 1 (leakage voltage), a signal "CMP-EN" and a signal "DrainVolt-EN-MCU" are respectively input to two input ends of an and gate chip, and a signal "DrainVolt-SW" is output after logical and. That is, "DrainVolt-SW" ═ CMP-EN "&" DrainVolt-EN-MCU ". When the signal "DrainVolt-SW" is high, the drain bias voltage is turned on, and when it is low, the drain bias voltage is turned off.
The signal "PA-EN-MCU" and the signal "PA-EN-SYS" (the grid voltage control signal output by the complete machine of the system) in the logic control unit circuit 2 (grid voltage) are respectively input to two input ends of the AND gate chip, and the signal "PA-EN" is output after logical AND. That is, "PA-EN" ═ PA-EN-MCU "& &" PA-EN-SYS ". When the signal PA-EN is high, the gate bias voltage is turned on, and when it is low, the gate bias voltage is turned off.
The grid voltage control unit circuit inverts a positive voltage DAC1 output by a DAC of the MCU through an inverse proportion amplifier formed by an operational amplifier, and outputs an inverted negative voltage DAC1-N to a grid voltage switch unit circuit formed by an analog switch U2. The U2 is an alternative switch, which is powered by a negative power supply, two input ends B1 are connected with a grid voltage DAC1-N, B0 is connected with a negative power supply-5V, an enabling signal is PA-EN (high level opens grid voltage, low level closes grid voltage), and an output end Vg is connected with a grid electrode of the GaN power amplifier to provide bias voltage for the grid electrode. The logic of U2 is: when the enable signal 'PA-EN' is at high level, the output end Vg is conducted with the DAC1-N at the end B1, and the PA is started; when the enable signal "PA-EN" is low, the output terminal Vg is turned on with the terminal-5V of B0, and PA is turned off. Several circuit units of fig. 2 accomplish the generation of gate voltage and the switching control.
As shown in FIG. 3, U1 in the negative voltage generating circuit is a negative voltage converting chip, and a negative power voltage of-5V is generated by U1 after +5V power is input. The adjustable negative pressure of C2, C3 produces time and falls the time of the negative pressure outage when falling the electricity, can adjust the appearance value according to actual demand and guarantee to fall the negative pressure hold time when falling the electricity suddenly, the utility model discloses well negative pressure hold time is 290 ms.
The gate voltage detection unit converts a gate bias voltage 'Vg' (negative voltage) into a positive voltage 'Vg-Det' through an inverse proportion amplification circuit composed of the operational amplifier U4, and supplies the positive voltage 'Vg-Det' to the analog switch U3 in the logic control unit 1. U3 is a two-way switch, its two input terminals B2 are connected to Vg-Det, B1 is connected to ground, the enable signal is "DrainVolt-SW", the output terminal "DrainVolt-EN" is connected to the drain switch unit circuit as the drain switch enable signal. The control logic of U3 is: when the enable pin is at high level, the output end is conducted with B2; when the enable pin is low, the output terminal is connected to B1. The enable pin is connected with the pull-down resistor R4 to ensure that the enable pin is at low level at the moment of power-up.
The leakage voltage switch unit circuit adopts an NPN triode Q2 and a PMOS pipe Q1 to realize the switch control of drain bias voltage. The output terminal "DrainVolt-EN" of U3 is connected to the base of Q2 through resistor R8, the source of Q1 is connected to the supply "+ 48V _ IN", and the drain of Q1 is connected to the drain of the GaN power amplifier. When "Drain volt-EN" is high, the collector and emitter of Q2 are conducted, the power supply "+ 48V _ IN" is connected IN series with R3 and R5 to ground, a voltage difference is formed between the gate and the source of Q1 (R3 and R5 are reasonably designed to ensure that the voltage difference is greater than the conduction threshold voltage), the source and the drain of Q1 are conducted, and the drain bias voltage of the GaN power amplifier is turned on. When "DrainVolt _ EN" is low, Q2 is turned off, the collector terminal of R5 connected to Q2 is equivalent to floating, Q1 is turned off, and the drain bias voltage of the GaN power amplifier is turned off.
Because the GaN power amplifier discharges slowly when the drain bias voltage is turned off, and the GaN power amplifier discharges in different conducting states for different time periods, a reliable power-off time sequence cannot be ensured, a ground resistor R2 is connected to the drain of the Q1, and a reliable discharging loop is provided for the drain bias voltage of the GaN power amplifier. The adjustable leakage voltage discharge time of resistance of adjustment R2, the utility model discloses well GaN power amplifier drain electrode offset voltage discharge time is 22 ms.
The specific working principle of the circuit is as follows:
in a normal process, after the single board is powered on, the "DrainVolt-SW" signal connected to the U3 enable pin is at a low level (both "CMP-EN" and "DrainVolt-EN-MCU" are at a low level), the output end of the U3 and the B1 are conducted and connected to the ground, the "DrainVolt-EN" signal is at a low level, both the Q2 and the Q1 are turned off, and the drain bias voltage of the GaN power amplifier is not turned on. And after the MCU detects that the grid bias voltage is normal, setting a 'DrainVolt-EN-MCU' signal to be at a high level. After the negative voltage reaches a safe value, the comparator outputs a signal 'CMP-EN' with a high level. Then the signal "DrainVolt-SW" goes high, the output of U3 is connected to B2, the signal "DrainVolt-EN" goes high, both Q2 and Q1 are connected, and the drain bias voltage of the GaN power amplifier is turned on.
If the negative power voltage-5V is abnormal before power-up, then after the single board is powered up, the gate voltage detection signal "Vg-Det" is at low level → the comparator output signal "CMP-EN" is at low level → the signal "DrainVolt-SW" is at low level → the drain bias voltage is not turned on. Even if the MCU also works abnormally, the Drain bias voltage is still not turned on because the "Drain volt-EN" signal output by U3 is still low because "Vg-Det" is low.
If the negative power supply voltage (-5V) is abnormal in the working process, the gate bias voltage detected by a comparator of the MCU is abnormal, and the signal CMP-EN is set to be low level → the signal DrainVolt-SW is set to be low level → the drain bias voltage is turned off. In the process, the response time of a comparator of the MCU is less than 5ms, the total response time is less than 30ms from the abnormal negative power supply voltage to the low level of a 'Drain volt _ EN _ MCU' signal output by the MCU and the discharge of the drain bias voltage of the GaN power amplifier. The holding time of the negative voltage of the grid electrode is far lower, so that the GaN power amplifier is still safe.
If the system is suddenly powered down during normal operation, it will quickly power down because the positive power supply is not designed to be powered down for the hold time. When the U3 power supply is cut off and cannot work, the base of the Q2 is connected with a pull-down resistor R9 and quickly changes to low level, and the drain bias voltage starts to be cut off. In the grid voltage switch circuit, the U2 can maintain normal work because the negative power supply voltage is still kept, the signal PA-EN is connected with a pull-down resistor and quickly changes into low level, the grid voltage Vg is conducted with the B0, and-5V is output. The utility model discloses through the test, under the system outage condition suddenly, about the leak voltage dropped to about 260ms behind the safe voltage, the grid negative pressure just cuts off the power supply completely, therefore GaN power amplifier is still safe.
The above embodiments and principles are only used to illustrate the design ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention, and the protection scope of the present invention is not limited to the above embodiments. Therefore, any simple modification made according to the technical essence of the present invention, equivalent changes and modifications all belong to the scope of the technical solution of the present invention.
Claims (8)
1. A power-on and power-off time sequence control circuit of a GaN power amplifier is characterized by comprising a main control chip, and a grid voltage switch control circuit and a leakage voltage switch control circuit which are connected with the main control chip;
the grid voltage switch control circuit comprises a grid voltage logic control unit circuit and a grid voltage switch unit circuit which are connected, the grid voltage logic control unit circuit is connected with a main control chip and a grid voltage control signal output by the system complete machine, and the grid voltage switch unit circuit is connected with a grid electrode of the GaN power amplifier;
the leakage voltage switch control circuit comprises a leakage voltage logic control unit circuit and a leakage voltage switch unit circuit which are connected, the leakage voltage logic control unit circuit is connected with the main control chip, and the leakage voltage switch unit circuit is connected with the drain electrode of the GaN power amplifier; and a grid voltage detection unit circuit is also connected between the grid of the GaN power amplifier and the leakage voltage logic control unit circuit.
2. The GaN power-on and power-off timing control circuit of claim 1, wherein the gate voltage switch control circuit further comprises a gate voltage generating unit circuit, and the gate voltage generating unit circuit is connected with the gate voltage switch unit circuit.
3. The power-on and power-off timing control circuit of the GaN power amplifier as claimed in claim 2, wherein a DAC module is arranged inside the main control chip, and the DAC module is connected with the gate voltage generation unit circuit.
4. The GaN power amplifier power-on and power-off timing control circuit of claim 3, wherein an inverse proportion amplifier is arranged in the gate voltage generation unit circuit to invert the positive voltage value output by the DAC module.
5. The GaN power-on/power-off timing control circuit of claim 1, further comprising a voltage conversion unit circuit for converting a power voltage inputted from the system into a working voltage of the timing control circuit.
6. The GaN power amplifier power-on and power-off timing control circuit of claim 5, wherein the negative voltage of the voltage conversion unit circuit has a power-off delay function.
7. The GaN power-on/power-off timing control circuit of claim 1 further comprising a power supply for providing an operating voltage for the timing control circuit.
8. The GaN power amplifier power-on and power-off timing control circuit of claim 1 wherein the main control chip is an MCU.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120404093.XU CN214380826U (en) | 2021-02-23 | 2021-02-23 | Power-on and power-off time sequence control circuit of GaN power amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120404093.XU CN214380826U (en) | 2021-02-23 | 2021-02-23 | Power-on and power-off time sequence control circuit of GaN power amplifier |
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| CN214380826U true CN214380826U (en) | 2021-10-08 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113794452A (en) * | 2021-11-15 | 2021-12-14 | 成都瑞迪威科技有限公司 | Negative voltage protection circuit of phased array radar antenna |
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2021
- 2021-02-23 CN CN202120404093.XU patent/CN214380826U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113794452A (en) * | 2021-11-15 | 2021-12-14 | 成都瑞迪威科技有限公司 | Negative voltage protection circuit of phased array radar antenna |
| CN113794452B (en) * | 2021-11-15 | 2022-02-08 | 成都瑞迪威科技有限公司 | Negative voltage protection circuit of phased array radar antenna |
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