CN210806841U - Time-delay power-off circuit - Google Patents
Time-delay power-off circuit Download PDFInfo
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- CN210806841U CN210806841U CN201921994945.4U CN201921994945U CN210806841U CN 210806841 U CN210806841 U CN 210806841U CN 201921994945 U CN201921994945 U CN 201921994945U CN 210806841 U CN210806841 U CN 210806841U
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Abstract
The utility model discloses a outage delay circuit, its characterized in that: the power failure detection device comprises a main power supply input end, a load power supply output end, a first switch module, a second switch module, a power failure detection module, a standby power supply and a microprocessor. The utility model discloses a microprocessor realizes time delay power-off control, and is reliable and more stable in the work.
Description
Technical Field
The utility model relates to a power field especially indicates a time delay power-off circuit.
Background
In human life, a plurality of occasions needing delayed power failure exist; for example, in the process of shutting down a computer, it takes a period of time to shut down the computer when the computer is in use. In order to protect the hardware and software of the computer from being damaged, an operator needs to wait for the computer to be shut down and then safely turn off a power switch on a power socket of the computer. For example, in places such as a warehouse, a lighting lamp is turned off when a person leaves, but the lighting lamp is required to set a proper time for the person to leave after the person presses a turn-off switch, and the lighting is turned off after the person leaves. In the prior art, in order to realize delayed power failure, a mechanical delay or power failure delay time relay and the like are generally adopted, and a mechanical delay switch is short in service life and easy to damage.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a reliable and stable operation's time delay power-off circuit.
In order to achieve the above purpose, the solution of the present invention is:
a power-off delay circuit comprises a main power supply input end, a load power supply output end, a first switch module, a second switch module, a power-off detection module, a standby power supply and a microprocessor; the first switch module comprises a resistor R1, a resistor R2, a MOS transistor Q1 and a self-locking switch SW 1; one end of the resistor R1 and the source electrode of the MOS tube Q1 are connected with a main power supply input end, the other end of the resistor R1 is connected with one end of the resistor R2 and the grid electrode of the MOS tube Q1, and the other end of the resistor R2 is grounded through a self-locking switch SW 1; the second switch module comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a diode D1, a diode D2, a diode D3, a diode D4, a triode Q2, a MOS tube Q3 and a MOS tube Q4; the positive electrode of the diode D1 is connected with the drain electrode of the MOS tube Q1, the negative electrode of the diode D1 is connected with the source electrode of the MOS tube Q3, the source electrode of the MOS tube Q4 and one end of the resistor R3, the drain electrode of the MOS tube Q3 is connected with the output end of a load power supply, the grid electrode of the MOS tube Q3 is connected with the other end of the resistor R3 and the collector electrode of the triode Q2, the emitter electrode of the triode Q2 is grounded, the base electrode of the triode Q2 is connected with one end of the resistor R6 and one end of the resistor R7, the other end of the resistor R6 is connected with the negative electrode of the diode D2 and the negative electrode of the diode D3, the other end of the resistor R7 is grounded, the positive electrode of the diode D2 is connected with the drain electrode of the MOS tube Q1, the positive electrode of the diode D3 is connected; the drain electrode of the MOS transistor Q4 is connected with the output end of the standby power supply, the gate electrode of the MOS transistor Q4 is connected with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R4 is connected with the cathode of a diode D4, the anode of a diode D4 is connected with the drain electrode of the MOS transistor Q1, and the other end of the resistor R5 is grounded; the microprocessor detects the drain voltage of the MOS tube Q1 through the power failure detection module, and when the drain voltage of the MOS tube Q1 is lower than a set threshold value, the microprocessor outputs a high level to the anode of the diode D3 within a set time.
The second switch module further comprises a polar capacitor C1 and a non-polar capacitor C2; the positive electrode of the polar capacitor C1 and one end of the nonpolar capacitor C2 are connected with the input end of the load power supply, and the negative electrode of the polar capacitor C1 and the other end of the nonpolar capacitor C2 are grounded.
The power failure detection module comprises a resistor R8, a resistor R9 and a diode D5, wherein the anode of the diode D5 is connected with the drain electrode of the MOS transistor Q1, the cathode of the diode D5 is connected with one end of a resistor R8, the other end of the resistor R8 is connected with one end of the resistor R9, and the other end of the resistor R9 is grounded; the common terminal of the resistor R8 and the resistor R9 is connected to one input terminal of the microprocessor.
The set threshold is 3.4 volts, and the set time is 2-5 milliseconds.
The standby power supply is a storage battery.
After the scheme is adopted, when the self-locking switch SW1 is closed and the main power input end has an external power input, the load power input end is supplied with power by the external power input by the main power input end; when the self-locking switch SW1 is switched off, or the self-locking switch SW1 is switched on but the drain voltage of the MOS transistor Q1 is lower than a set threshold value, the microprocessor controls the standby power supply to control the standby power supply to supply power to the input end of the load power supply within a set time, so that the effect of delayed power-off is achieved, the microprocessor realizes delayed power-off control, and the work is more stable and reliable.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
In order to further explain the technical solution of the present invention, the present invention is explained in detail by the following embodiments.
As shown in fig. 1, the utility model discloses a power-off delay circuit, it includes main power input end, load power output end, first switch module, second switch module, falls electric detection module, stand-by power supply and microprocessor.
As shown in fig. 1, the first switch module includes a resistor R1, a resistor R2, a MOS transistor Q1, and a self-locking switch SW 1; one end of the resistor R1 and the source electrode of the MOS tube Q1 are connected with a main power supply input end, the other end of the resistor R1 is connected with one end of the resistor R2 and the grid electrode of the MOS tube Q1, and the other end of the resistor R2 is grounded through a self-locking switch SW 1; the second switch module comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a diode D1, a diode D2, a diode D3, a diode D4, a triode Q2, a MOS tube Q3 and a MOS tube Q4; the positive electrode of the diode D1 is connected with the drain electrode of the MOS tube Q1, the negative electrode of the diode D1 is connected with the source electrode of the MOS tube Q3, the source electrode of the MOS tube Q4 and one end of the resistor R3, the drain electrode of the MOS tube Q3 is connected with the output end of a load power supply, the grid electrode of the MOS tube Q3 is connected with the other end of the resistor R3 and the collector electrode of the triode Q2, the emitter electrode of the triode Q2 is grounded, the base electrode of the triode Q2 is connected with one end of the resistor R6 and one end of the resistor R7, the other end of the resistor R6 is connected with the negative electrode of the diode D2 and the negative electrode of the diode D3, the other end of the resistor R7 is grounded, the positive electrode of the diode D2 is connected with the drain electrode of the MOS tube Q1, the positive electrode of the diode D3 is connected; the drain electrode of the MOS transistor Q4 is connected with the output end of the standby power supply, the gate electrode of the MOS transistor Q4 is connected with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R4 is connected with the cathode of a diode D4, the anode of a diode D4 is connected with the drain electrode of the MOS transistor Q1, and the other end of the resistor R5 is grounded; the microprocessor detects the drain voltage of the MOS tube Q1 through the power failure detection module, and when the drain voltage of the MOS tube Q1 is lower than a set threshold, the microprocessor outputs a high level to the anode of the diode D3 within a set time; the set threshold may be 3.4 volts, and the set time may be 2 to 5 milliseconds.
The utility model discloses a theory of operation does:
when an external power supply is connected to the main power supply input end, if the self-locking switch SW1 is pressed to be closed, the MOS transistor Q1 is grounded through the resistor R2, so that the MOS transistor Q1 is conducted, and the drain voltage of the MOS transistor Q1 is at a high level; on the one hand, the high level of the drain voltage of the MOS transistor Q1 makes the high level of the gate voltage of the MOS transistor Q4, at this time, the MOS transistor Q4 is turned off, and the standby power supply does not provide power; on the other hand, the drain voltage of the MOS transistor Q1 is high, so that the transistor Q2 is turned on, the collector voltage of the transistor Q2 is pulled low, and the MOS transistor Q3 is turned on; thus, the output end of the load power supply is powered by an external power supply at the moment;
when the external power supply is abnormal or the self-locking switch SW1 is turned off to turn off the MOS transistor Q1, at this time, the drain voltage of the MOS transistor Q1 is not high level, so that the gate of the MOS transistor Q4 is low level, so that the MOS transistor Q4 is turned on, and meanwhile, the microprocessor detects that the drain voltage of the MOS transistor Q1 is lower than the set threshold value through the power failure detection module, and at this time, the microprocessor outputs high level to the anode of the diode D3 within the set time. In the time when the microprocessor outputs high level to the anode of the diode D3, the triode Q2 is conducted to enable the MOS transistor Q3 to be conducted, at the moment, the output end of the load power supply is powered by a standby power supply, and the standby power supply can adopt a storage battery; after the set time is exceeded, the microprocessor does not output a high level to the anode of the diode D3, at this time, the transistor Q2 is cut off, so that the MOS transistor Q3 is cut off, and there is no voltage at the output end of the load power supply.
As shown in fig. 1, the power down detection module includes a resistor R8, a resistor R9, and a diode D5, wherein an anode of the diode D5 is connected to a drain of the MOS transistor Q1, a cathode of the diode D5 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to one end of the resistor R9, and the other end of the resistor R9 is grounded; the common terminal of the resistor R8 and the resistor R9 is connected to one input terminal of the microprocessor.
Further, as shown in fig. 1, the second switch module further includes a polar capacitor C1 and a non-polar capacitor C2; the positive electrode of the polar capacitor C1 and one end of the nonpolar capacitor C2 are connected with the input end of the load power supply, the negative electrode of the polar capacitor C1 and the other end of the nonpolar capacitor C2 are grounded, and therefore filtering is performed through the polar capacitor C1 and the nonpolar capacitor C2, and the voltage of the input end of the load power supply is guaranteed to be stable.
The above embodiments and drawings are not intended to limit the form and style of the present invention, and any suitable changes or modifications made by those skilled in the art should not be construed as departing from the scope of the present invention.
Claims (5)
1. A kind of outage delay circuit, characterized by: the power failure detection device comprises a main power supply input end, a load power supply output end, a first switch module, a second switch module, a power failure detection module, a standby power supply and a microprocessor;
the first switch module comprises a resistor R1, a resistor R2, a MOS transistor Q1 and a self-locking switch SW 1; one end of the resistor R1 and the source electrode of the MOS tube Q1 are connected with a main power supply input end, the other end of the resistor R1 is connected with one end of the resistor R2 and the grid electrode of the MOS tube Q1, and the other end of the resistor R2 is grounded through a self-locking switch SW 1;
the second switch module comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a diode D1, a diode D2, a diode D3, a diode D4, a triode Q2, a MOS tube Q3 and a MOS tube Q4; the positive electrode of the diode D1 is connected with the drain electrode of the MOS tube Q1, the negative electrode of the diode D1 is connected with the source electrode of the MOS tube Q3, the source electrode of the MOS tube Q4 and one end of the resistor R3, the drain electrode of the MOS tube Q3 is connected with the output end of a load power supply, the grid electrode of the MOS tube Q3 is connected with the other end of the resistor R3 and the collector electrode of the triode Q2, the emitter electrode of the triode Q2 is grounded, the base electrode of the triode Q2 is connected with one end of the resistor R6 and one end of the resistor R7, the other end of the resistor R6 is connected with the negative electrode of the diode D2 and the negative electrode of the diode D3, the other end of the resistor R7 is grounded, the positive electrode of the diode D2 is connected with the drain electrode of the MOS tube Q1, the positive electrode of the diode D3 is connected; the drain electrode of the MOS transistor Q4 is connected with the output end of the standby power supply, the gate electrode of the MOS transistor Q4 is connected with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R4 is connected with the cathode of a diode D4, the anode of a diode D4 is connected with the drain electrode of the MOS transistor Q1, and the other end of the resistor R5 is grounded;
the microprocessor detects the drain voltage of the MOS tube Q1 through the power failure detection module, and when the drain voltage of the MOS tube Q1 is lower than a set threshold value, the microprocessor outputs a high level to the anode of the diode D3 within a set time.
2. A power-down delay circuit as recited in claim 1, wherein: the second switch module further comprises a polar capacitor C1 and a non-polar capacitor C2; the positive electrode of the polar capacitor C1 and one end of the nonpolar capacitor C2 are connected with the input end of the load power supply, and the negative electrode of the polar capacitor C1 and the other end of the nonpolar capacitor C2 are grounded.
3. A power-down delay circuit as recited in claim 1, wherein: the power failure detection module comprises a resistor R8, a resistor R9 and a diode D5, wherein the anode of the diode D5 is connected with the drain electrode of the MOS transistor Q1, the cathode of the diode D5 is connected with one end of a resistor R8, the other end of the resistor R8 is connected with one end of the resistor R9, and the other end of the resistor R9 is grounded; the common terminal of the resistor R8 and the resistor R9 is connected to one input terminal of the microprocessor.
4. A power-down delay circuit as recited in claim 1, wherein: the set threshold is 3.4 volts, and the set time is 2-5 milliseconds.
5. A power-down delay circuit as recited in claim 1, wherein: the standby power supply is a storage battery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921994945.4U CN210806841U (en) | 2019-11-18 | 2019-11-18 | Time-delay power-off circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921994945.4U CN210806841U (en) | 2019-11-18 | 2019-11-18 | Time-delay power-off circuit |
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| CN210806841U true CN210806841U (en) | 2020-06-19 |
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| CN201921994945.4U Active CN210806841U (en) | 2019-11-18 | 2019-11-18 | Time-delay power-off circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112003363A (en) * | 2020-08-03 | 2020-11-27 | 哈尔滨新中新电子股份有限公司 | Embedded power system management circuit |
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2019
- 2019-11-18 CN CN201921994945.4U patent/CN210806841U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112003363A (en) * | 2020-08-03 | 2020-11-27 | 哈尔滨新中新电子股份有限公司 | Embedded power system management circuit |
| CN112003363B (en) * | 2020-08-03 | 2024-05-24 | 哈尔滨新中新电子股份有限公司 | Embedded power supply system management circuit |
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