CN214315299U - Device for realizing wide-band real-time phase calibration based on programmable logic device - Google Patents
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Abstract
The utility model discloses a device for realizing wide-band real-time phase calibration based on a programmable logic device, which comprises a reference clock signal, a radio frequency signal, a 0-degree power divider, a fixed phase shifter, a 0-degree phase discriminator A, a 0-degree phase discriminator B, a 0-degree bidirectional coupler, a switch and a programmable logic device, wherein the programmable logic device is used for data acquisition and analysis, carrying out logic judgment on a trigger edge and high and low levels of the programmable logic device, calculating a preset range of the phase difference, calculating a specific phase difference by combining a voltage difference value, generating a multi-bit parallel SPI control word through logic conversion, controlling a phase shifting value of a numerical control phase shifter of a main signal channel, realizing final phase calibration post-control, aiming at the urgent requirements of high frequency, high precision, high intellectualization and wide-band multi-channel, realizing accurate broadband real-time phase difference measurement and calibration, has important significance in wireless communication.
Description
Technical Field
The utility model relates to a phase detection device, concretely relates to realize device of real-time phase place calibration of wide band based on programmable logic device.
Background
In wireless communication, it is important to accurately measure the phase difference between signals, and with the wide development of various fields such as national defense, scientific research and production, the phase difference measurement and calibration technology gradually develops towards high frequency, high precision, high intelligence and broadband multi-channel.
The existing phase detection method mainly comprises the following steps: direct phase comparison, direct phase discrimination, power synthesis, phase conversion to time intervals, etc.
The direct phase comparison method usually needs a large number of high-precision phase shifters, has complex manufacturing process, high cost and narrow working frequency band, and is suitable for low-frequency and medium-frequency signals.
The direct phase discrimination method mainly uses a nonlinear device as a synchronous phase discriminator, but a single synchronous phase discriminator can only provide phase difference information of 0-180 degrees or-90 degrees to +90 degrees, and no method is available for realizing accurate measurement of the phase difference at 0-360 degrees.
The power synthesis method mainly judges the maximum value or the minimum value of the power synthesis, and realizes the measurement of the phase difference by matching with the logic operation.
The method for converting the phase into the time interval generally adopts a zero-crossing phase discrimination technology, the time interval of phase discrimination output is in direct proportion to the phase difference, the phase discrimination output has linear scales, but a phase blind area also exists, in order to avoid the blind area, two phase measuring ranges (0 degrees to-180 degrees and-180 degrees to-0 degrees) and a conversion circuit thereof need to be designed, the circuit is complex, but the method is a phase detection scheme widely adopted at present due to higher precision.
Disclosure of Invention
Present device of wide band section real-time phase calibration, the utility model discloses at radio frequency and microwave frequency channel, adopt programmable logic device to carry out phase information data acquisition and analysis, can save hardware design resource effectively to realize accurate wide band phase difference measurement and calibration in real time.
In order to achieve the above object, the technical solution of the present invention is as follows:
a device for realizing wide-band real-time phase calibration based on a programmable logic device comprises a reference clock signal, a 0-degree bidirectional coupler and a radio frequency signal, and is characterized in that: the phase shifter also comprises a 0-degree power divider, a fixed phase shifter, a 0-degree phase detector A, a 0-degree phase detector B, a switch and a programmable logic device.
The reference clock signal is connected with the input end of the 0-degree power divider, one path of the output end of the 0-degree power divider is connected with the input end of the phase discriminator A, and the other path of the output end of the 0-degree power divider is connected with the input end of the phase discriminator B;
the radio frequency signal is connected with the input end of another 0-degree power divider, one path of the output end of the 0-degree power divider is connected with the input end of a fixed phase shifter for 90-degree phase shift, the other path of the output end of the 0-degree power divider is connected with the input end of another fixed phase shifter for 180-degree phase shift, the output end of one fixed phase shifter is connected with the input end of a phase discriminator A, and the output end of the other fixed phase shifter is connected with the input end of a phase discriminator B;
the switch comprises a movable end and a fixed end, the output end of the phase discriminator A and the output end of the phase discriminator B are connected with the fixed end of the switch, the movable end of the switch is connected with the programmable logic device, and the programmable logic device generates PWM pulse signals to be added to the movable end of the switch.
Preferably, the programmable logic device adopts an FPGA.
Preferably, the 0 ° phase detector A, B ideally has a well-defined 180 ° phase difference measurement range, i.e., 0 ° -180 ° or-180 ° -0 °.
Preferably, the programmable logic device generates a PWM control waveform with a duty ratio of N:1, and alternately acquires values of phase detection output voltage U1 of phase detector a and phase detection output voltage U2 of phase detector B in M periods, where the value of N is greater than 2.
Preferably, the programmable logic device generates a duty cycle N with a value of 3.
Preferably, the period of the alternate collection of the programmable logic device is 2.
Preferably, the values of U1 and U2 collected in the M periods are processed by a weighted average method.
Preferably, the switch is a high frequency single pole double throw switch.
Compared with the prior art, the utility model discloses beneficial effect as follows:
the utility model discloses at radio frequency and microwave frequency channel, adopt programmable logic device to carry out phase information data acquisition and analysis, can save hardware design resource effectively to realize accurate wide band phase difference measurement and calibration in real time.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
fig. 2 is a flowchart illustrating the operation of the programmable logic device according to the present invention;
wherein: 1. the device comprises a reference clock signal 2, a radio frequency signal 3, a power divider 4, a fixed phase shifter 5, phase detectors A and 6, phase detectors B and 7, a switch 8 and a programmable logic device.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.
As shown in fig. 1 and 2, a device for implementing wide-band real-time phase calibration based on a programmable logic device includes a reference clock signal 1, a radio frequency signal 2, a 0 ° power divider 3, a fixed phase shifter 4, a 0 ° phase detector a5, a 0 ° phase detector B6, a 0 ° bidirectional coupler, a control switch 7, and a programmable logic device 8.
The reference clock signal 1 is U0= Acos ω t, the radio frequency signal 2 to be detected is U1= Bcos (ω t + φ), after the reference clock signal 1 is divided into two paths by the 0 ° power divider 3, one path is sent to the input end of the phase discriminator A5 to become one of the input signals of the phase discriminator A5, and the other path is sent to the input end of the phase discriminator B6 to become one of the input signals of the phase discriminator B6. After the radio frequency signal 2 to be detected is subjected to power division into two paths by the 0-degree power divider 3, one path is subjected to phase shift of 180 degrees through the fixed phase shifter 4 and enters the input end of the phase discriminator A to become one of input signals of the phase discriminator A, and the other path is subjected to phase shift of 90 degrees through the other fixed phase shifter and enters the input end of the phase discriminator B6 to become one of input signals of the phase discriminator B6.
The 0 ° power divider 3 is a device that divides one path of input signal energy into two or more paths to output equal or unequal energy, in this embodiment, one 0 ° power divider 3 divides a reference clock signal into two paths respectively, which are sent to the input ends of the phase discriminator a5 and the phase discriminator B6, and the other 0 ° power divider divides the rf signal 5 to be measured into two paths, which are sent to two fixed phase shifters respectively, one phase shifted by 180 ° and the other phase shifted by 90 °.
The fixed phase shifter 4 is a device capable of adjusting the phase of a wave, in this embodiment, one fixed phase shifter 4 phase-shifts one path of signal after the power division of the radio frequency signal to be detected by-180 degrees and sends the signal to the input end of the phase discriminator a5, and the other fixed phase shifter 4 phase-shifts the other path of signal after the power division of the radio frequency signal to be detected by 90 degrees and sends the signal to the input end of the phase discriminator B6.
In this embodiment, the switch 7 is a single-pole double-throw switch, two ports of a stationary end of the switch are respectively connected to output ends of a phase detector a5 and a phase detector B6, a moving end of the switch, that is, a handle of the switch, is connected to the programmable logic device 8, the programmable logic device 8 generates a PWM pulse control signal, and the PWM pulse control signal is applied to a control end of the switch 7 according to a duty ratio and distribution of high and low levels to control channel gating of the switch 7.
The phase discriminator is a device capable of discriminating the phase difference of input signals, and is a circuit which ensures that the phase difference between output voltage and two input signals has a definite relationship, the phase discriminator analyzes high-frequency signals through an internal operational amplifier and a phase detector, phase information is output from an output end in a current form, and the output phase difference is converted into a voltage value which can be expressed by the following formula:
wherein VPHSVoltage values, R, corresponding to phase differencesFFor the characteristic impedance of the feedback end, I phi is the characteristic slope of the phase detector in the phase detector, and R is used for different phase detectorsFI φ has different values; phi (V)INA) And phi (V)INB) Individual watchShowing the relative phase of the input terminals; vCPThe voltage of the central point preset in the phase discriminator. In the embodiment, R of the phase detector a5 and the phase detector B6FI phi has different values, the phase detection output voltage V of the phase detector a5PHSDenoted by U1, the phase detection output voltage V of the phase detector B6PHSIndicated by U2. In the present embodiment, in the phase detector a, phi (V)INA) The phase, phi (V), of the signal applied to the input of the phase detector A5 after power division of the reference clock signalINB) The phase of the signal sent to the input end of the phase discriminator A5 is obtained after the radio frequency signal is divided and is phase-shifted by a fixed phase shifter of-180 degrees. In the phase detector B6, [ phi ] (V)INA) The phase, phi (V), of the signal applied to the input of the phase detector B6 after power division of the reference clock signalINB) The phase of the signal sent to the input end of the phase discriminator B6 is obtained after the radio frequency signal is divided and is shifted by a fixed phase shifter by-90 degrees. In the embodiment, under an ideal condition, the phase detector has a definite phase difference measurement range of 180 degrees, namely 0-180 degrees and-180-0 degrees, the phase detector a generates the phase detection output voltage U1 according to the phase difference of two signals at the input end, and the phase detector B generates the phase detection output voltage U2 according to the phase difference of two signals at the input end.
The programmable logic device 8 generates a PWM pulse control signal with a duty ratio of N:1(N >2), and the PWM pulse control signal is applied to the control end of the switch 7 to control the channel gating of the switch 7 according to the duty ratio and the distribution of high and low levels. Because the switch 7 normally has a switching time of ns order, which causes the data-collected pulse to be delayed for a certain time relative to the original PWM pulse control signal, in the period of the control pulse of the switch 7, the data value needs to be repeatedly sampled for a plurality of times, the values of U1 and U2 in M periods are collected alternately, the sampling result is weighted-averaged, a new combined pulse is generated, i.e., U1 and U2 after weighted-averaging, and thus the collected new pulse combination is related to the sampling period. In this embodiment, the programmable logic device 8 is an FPGA, where N =3 and M =2, that is, a period is 2 periods, and a duty ratio of a control level of the switch 7 is 3:1, assuming that the switch 7 is at a low level in a first 3/4 period and at a high level in a second 1/4 period, the switch 7 is gated to the phase detector a5 when the control level is at the low level, the output voltage U1 of the phase detector a5 is collected, the switch 7 is gated to the phase detector B6 when the control level is at the high level, the output voltage U2 of the phase detector B6 is collected, values of U1 and U2 in the collected 2 periods are weighted and averaged, a new pulse combination (U1 and U2 after weighted average processing) is generated, and finally, the collected data is sent to the programmable logic device.
The programmable logic device program determines the state of the trigger edge of the sampling pulse, and the state of the rising edge, the falling edge and the no trigger edge can exist under normal conditions. Combining the newly generated pulses and sending the combined pulses to the programmable logic device 8, wherein the programmable logic device 8 analyzes the newly generated combined pulses, and judges the high and low level voltage values U1, U2 and V of the pulses according to respective procedures after detecting the triggering edge of the pulsesCPSubstituting the values into corresponding logic calculation formulas to finally obtain phase difference values in different states.
The determination and calculation process is as follows:
when triggered by a rising edge, U1<U2, and U2 is more than or equal to VCP(V of phase detector in validation dataCP0.9V), the phase difference is Φ = (180 × U1/Umax) °;
when the rising edge is triggered, U1 is more than or equal to 0 and more than U2 and more than VCP(V of phase detector in validation dataCP0.9V), phase difference phi =360 ° - (180 x U1/Umax) °;
when the falling edge is triggered, U2<U1, and U1 is more than or equal to VCP(V of phase detector in validation dataCP0.9V), the phase difference is phi =270 ° - (180 x U2/Umax) °;
when the falling edge is triggered, U2 is more than or equal to 0 and more than U1 and more than VCP(V of phase detector in validation dataCP0.9V), phase difference phi =270 ° + (180 x U2/Umax) °;
when no edge trigger exists, if U1= U2 ≧ VCP(V of phase detector in validation dataCP0.9V), the phase difference is Φ = (180 × U1/Umax) °;
when no edge trigger exists, if 0 is more than or equal to U1= U2 < VCP(V of phase detector in validation dataCP0.9V), the phase difference phi =360 ° - (180 x)U1/Umax)°。
After the phase difference values in different states are obtained, the programmable logic device 8 calls the obtained phase difference values to write SPI control words according to the control mode of the digital phase shifter, so that the phase shifting precision of the digital phase shifter is controlled, and the required phase calibration and control requirements are met.
The utility model discloses adopted 2 fixed phase shifters 4 before the comparison phase demodulation, the signal phase shift that will await measuring respectively 90 and 180, fixed phase shifter's precision can cause certain error influence to final phase calibration, and fixed phase shifter precision on the market at present can be controlled below 0.5. The utility model discloses a two phase discriminator carry out data acquisition, and phase discriminator is because the error of self under the normal condition, and its equivalent gain can not equal completely, and this voltage that has just caused after the phase discrimination has certain error, and generally speaking such error precision can be controlled below 0.5. The utility model discloses the non-ideality distortion of phase discriminator that well ambient temperature caused can influence the precision of phase calibration equally, and the error precision that nevertheless causes is decided by the temperature coefficient of device, through looking up the data, and the non-ideality error of device also can be controlled within 1 generally. In summary, when the method is used to realize the phase calibration of the radio frequency signal, the total phase calibration error accuracy can be controlled within Δ = =1.2 °, and the error accuracy control result is better than that of the current mainstream method.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention, so as not to limit the protection scope of the present invention, and all equivalent changes or modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
To sum up, the utility model discloses expected effect has been reached.
Claims (8)
1. A device for realizing wide-band real-time phase calibration based on a programmable logic device comprises a reference clock signal, a radio frequency signal and a 0-degree bidirectional coupler, and is characterized in that: the phase shifter also comprises a 0-degree power divider, a fixed phase shifter, a 0-degree phase discriminator A, a 0-degree phase discriminator B, a switch and a programmable logic device;
the reference clock signal is connected with the input end of the 0-degree power divider, one path of the output end of the 0-degree power divider is connected with the input end of the phase discriminator A, and the other path of the output end of the 0-degree power divider is connected with the input end of the phase discriminator B;
the radio frequency signal is connected with the input end of another 0-degree power divider, one path of the output end of the another 0-degree power divider is connected with the input end of a fixed phase shifter for 90-degree phase shift, the other path of the output end of the another 0-degree power divider is connected with the input end of another fixed phase shifter for 180-degree phase shift, the output end of the fixed phase shifter is connected with the input end of a phase discriminator A, and the output end of the another fixed phase shifter is connected with the input end of a phase discriminator B;
the switch comprises a movable end and a fixed end, the output end of the phase discriminator A and the output end of the phase discriminator B are connected with the fixed end of the switch, the movable end of the switch is connected with the programmable logic device, and the programmable logic device generates PWM pulse signals to be added to the movable end of the switch.
2. The apparatus of claim 1 for implementing wideband real-time phase calibration based on programmable logic devices, wherein: the programmable logic device adopts an FPGA.
3. The apparatus of claim 1 for implementing wideband real-time phase calibration based on programmable logic devices, wherein: the 0-degree phase discriminator A and the 0-degree phase discriminator B have a definite 180-degree phase difference measuring range under the ideal condition, namely 0-180 degrees or-180-0 degrees.
4. The apparatus of claim 1 for implementing wideband real-time phase calibration based on programmable logic devices, wherein: the programmable logic device generates a PWM control waveform with a duty ratio of N:1, the values of phase detection output voltage U1 of a phase detector A and phase detection output voltage U2 of a phase detector B in M periods are collected alternately, and the value of N is larger than 2.
5. The apparatus of claim 4 for implementing wideband real-time phase calibration based on programmable logic devices, wherein: the programmable logic device generates a duty cycle N with a value of 3.
6. The apparatus of claim 4 for implementing wideband real-time phase calibration based on programmable logic devices, wherein: the period of the alternate collection of the programmable logic device is 2.
7. The apparatus of claim 4 for implementing wideband real-time phase calibration based on programmable logic devices, wherein: and processing the values of U1 and U2 collected in the M periods by adopting a weighted average method.
8. The apparatus of claim 1 for implementing wideband real-time phase calibration based on programmable logic devices, wherein: the switch is a high-frequency single-pole double-throw switch.
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