CN214256114U - Low-cost high performance IGBT drive circuit - Google Patents

Abstract

The utility model discloses a low-cost high performance IGBT drive circuit, include: the signal input module is used for inputting a first PWM control signal and a second PWM control signal; the driving module is used for controlling the working state of an MOS upper tube according to the first PWM control signal and controlling the working state of an MOS lower tube according to the second PWM control signal; the discharging module comprises an upper tube discharging unit and a lower tube discharging unit, and the upper tube discharging unit is used for releasing the electric quantity on the grid of the MOS upper tube after the MOS upper tube is closed; the lower tube discharging unit is used for releasing the electric quantity on the grid of the MOS lower tube after the MOS lower tube is closed. The utility model provides a novel low-cost high performance well low power IGBT drive application circuit, this drive circuit is simple, has the advantage of low-cost and high reliability, has fine economy and social using value, but wide application in power electronics application technical field.

Description

Low-cost high performance IGBT drive circuit

Technical Field

The utility model relates to a power electronics uses technical field, especially relates to a low-cost high performance IGBT drive circuit.

Background

The prior patents with patent numbers of CN202020365413.0 and CN202010500180.5 describe the middle and small power IGBT driving technology in detail, the former realizes IGBT driving and protection by means of the driving chip acpl-333j + to assist the periphery, which increases the chip cost and is not good for the middle and small enterprise cost; although the latter does not use a driving chip, the latter adopts optical coupling to drive isolation, and cannot be used in occasions with higher requirements on the time-speed dynamic performance.

Interpretation of terms:

IGBT: an insulated gate bipolar transistor is a composite fully-controlled voltage-driven power semiconductor device consisting of a BJT (bipolar junction transistor) and an MOS (insulated gate field effect transistor), and has the advantages of both high input impedance of an MOSFET (metal-oxide-semiconductor field effect transistor) and low conduction voltage drop of a GTR (GTR).

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model aims at providing a low-cost high performance IGBT drive circuit.

The utility model adopts the technical proposal that:

a low-cost high-performance IGBT drive circuit, comprising:

the signal input module is used for inputting a first PWM control signal and a second PWM control signal;

the driving module is used for controlling the working state of an MOS upper tube according to the first PWM control signal and controlling the working state of an MOS lower tube according to the second PWM control signal;

the discharging module comprises an upper tube discharging unit and a lower tube discharging unit, and the upper tube discharging unit is used for releasing the electric quantity on the grid of the MOS upper tube after the MOS upper tube is closed; the lower tube discharging unit is used for releasing the electric quantity on the grid of the MOS lower tube after the MOS lower tube is closed.

Further, the signal input module comprises a first input module and a second input module;

the first input module comprises a twenty-fifth resistor, a twenty-sixth resistor and a ninth transistor;

one end of the twenty-fifth resistor is connected with a first bias voltage, the other end of the twenty-fifth resistor is connected with the base electrode of the ninth transistor, the emitter electrode of the ninth transistor is connected with one end of the twenty-sixth resistor, the other end of the twenty-sixth resistor inputs a first PWM control signal, and the collector electrode of the ninth transistor is connected with the driving module;

the second input module comprises a thirty-first resistor and a thirteenth transistor;

the base electrode of the thirteenth transistor is connected with a first bias voltage, the emitting electrode of the thirteenth transistor is connected with one end of the thirty-first resistor, the other end of the thirty-first resistor is input with a second PWM control signal, and the collector electrode of the thirteenth transistor is connected with the driving module.

Further, the driving module comprises an upper pipe driving unit and a lower pipe driving unit;

the upper tube driving unit is used for controlling the working state of an MOS upper tube, and the lower tube driving unit is used for controlling the working state of an MOS lower tube.

Further, the top tube driving unit comprises a tenth transistor, an eighth diode, a twenty-third resistor, a ninety-ninth resistor and a hundredth resistor;

a base electrode of the tenth transistor is connected with a collector electrode of the ninth transistor, a reflector electrode of the tenth transistor is connected with a second bias voltage, a collector electrode of the tenth transistor is connected with an anode electrode of the eighth diode, a cathode electrode of the eighth diode is connected with one end of the twenty-third resistor, the other end of the twenty-third resistor is respectively connected with one end of the ninety-ninth resistor and one end of the first hundred resistor, the other end of the ninety-ninth resistor is connected with a grid electrode of the fifth MOS transistor, and the other end of the first hundred resistor is connected with a grid electrode of the sixth MOS transistor;

and the fifth MOS tube and the sixth MOS tube are both MOS upper tubes.

Further, the lower tube driving unit includes an eleventh transistor, a nineteenth diode, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-eighth resistor, and a sixty-seventh resistor;

a base electrode of the eleventh transistor is connected with a collector electrode of the thirteenth transistor, an emitter electrode of the eleventh transistor is connected with a second bias voltage, a collector electrode of the eleventh transistor is connected with an anode electrode of the nineteenth diode, a cathode electrode of the nineteenth diode is connected with one end of the twenty-eighth resistor, and the other end of the twenty-eighth resistor is respectively connected with one end of the twenty-ninth resistor, one end of the thirty-fifth resistor and one end of the sixty-seventh resistor;

the other end of the twenty-ninth resistor is connected with the grid electrode of the seventh MOS tube, the other end of the thirty-eighth resistor is connected with the grid electrode of the eighth MOS tube, and the other end of the sixty-seventh resistor is connected with the grid electrode of the fourteenth MOS tube;

and the seventh MOS tube, the eighth MOS tube and the fourteenth MOS tube are all MOS lower tubes.

Further, the upper tube discharging unit comprises a sixth transistor, a forty-ninth resistor, a fifty-third resistor, a nineteenth resistor and a twenty-first capacitor;

a base electrode of the sixth transistor is connected with a collector electrode of the tenth transistor, an emitter electrode of the sixth transistor is connected with the other end of the twenty-third resistor, a collector electrode of the sixth transistor is grounded sequentially through the fifty-third resistor and the nineteenth resistor, and the forty-ninth resistor is connected in series between the base electrode and the collector electrode of the sixth transistor;

one end of the twenty-first capacitor is connected with one end of the first hundred resistor, and the other end of the twenty-first capacitor is connected with the collector electrode of the sixth transistor.

Further, the lower tube discharge unit comprises a fourteenth transistor and a nineteenth resistor;

the base of the fourteenth transistor is connected to the collector of the eleventh transistor, the emitter of the fourteenth transistor is connected to the other end of the twenty-eighth resistor, and the collector of the fourteenth transistor is grounded through the nineteenth resistor.

Further, the lower tube driving unit comprises an overcurrent protection circuit, and the overcurrent protection circuit comprises a seventy-sixth capacitor and a thirty-third resistor;

one end of the seventy-sixth capacitor is connected with one end of the nineteenth resistor, the other end of the seventy-sixth capacitor is connected with one end of the thirty-third resistor, and the other end of the thirty-third resistor is connected with the base electrode of the eleventh transistor.

Further, the lower tube driving unit further comprises a thirtieth diode, wherein the anode of the thirtieth diode is connected with the second bias voltage, and the cathode of the thirtieth diode is connected with the emitter of the eleventh transistor.

The utility model has the advantages that: the utility model provides a novel low-cost high performance well low power IGBT drive application circuit, this drive circuit is simple, has the advantage of low-cost and high reliability, has fine economy and social using value.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is an electronic circuit diagram of a low-cost high-performance IGBT driving circuit according to an embodiment of the present invention;

fig. 2 is a simulation circuit diagram of a low-cost high-performance IGBT driving circuit according to an embodiment of the present invention;

fig. 3 is a diagram illustrating simulation results of a low-cost high-performance IGBT driving circuit according to an embodiment of the present invention.

Detailed Description

This section will describe in detail the embodiments of the present invention, preferred embodiments of the present invention are shown in the attached drawings, which are used to supplement the description of the text part of the specification with figures, so that one can intuitively and vividly understand each technical feature and the whole technical solution of the present invention, but they cannot be understood as the limitation of the protection scope of the present invention.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated with respect to the orientation description, such as up, down, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, a plurality of means are one or more, a plurality of means are two or more, and the terms greater than, less than, exceeding, etc. are understood as not including the number, and the terms greater than, less than, within, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless there is an explicit limitation, the words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in combination with the specific contents of the technical solution.

As shown in fig. 1, the present embodiment provides a low-cost high-performance IGBT driving circuit including:

the signal input module is used for inputting a first PWM control signal and a second PWM control signal;

the driving module is used for controlling the working state of an MOS upper tube according to the first PWM control signal and controlling the working state of an MOS lower tube according to the second PWM control signal;

the discharging module comprises an upper tube discharging unit and a lower tube discharging unit, and the upper tube discharging unit is used for releasing the electric quantity on the grid of the MOS upper tube after the MOS upper tube is closed; the lower tube discharging unit is used for releasing the electric quantity on the grid of the MOS lower tube after the MOS lower tube is closed.

As a further optional implementation, the signal input module includes a first input module and a second input module;

the first input module comprises a twenty-fifth resistor R25, a twenty-fifth resistor R26 and a ninth transistor Q9;

one end of the twenty-fifth resistor R25 is connected to a first bias voltage, the other end of the twenty-fifth resistor R25 is connected to a base of the ninth transistor Q9, an emitter of the ninth transistor Q9 is connected to one end of the twenty-fifth resistor R26, the other end of the twenty-fifth resistor R26 inputs a first PWM control signal, and a collector of the ninth transistor Q9 is connected to the driving module;

the second input module comprises a thirty-first resistor R31 and a thirteenth transistor Q13;

the base of the thirteenth transistor Q13 is connected to a first bias voltage, the emitter of the thirteenth transistor Q13 is connected to one end of the thirty-first resistor R31, the other end of the thirty-first resistor R31 is inputted with a second PWM control signal, and the collector of the thirteenth transistor Q13 is connected to the driving module.

As a further optional implementation, the driving module includes an upper tube driving unit and a lower tube driving unit;

the upper tube driving unit is used for controlling the working state of an MOS upper tube, and the lower tube driving unit is used for controlling the working state of an MOS lower tube.

Further as an optional embodiment, the top tube driving unit includes a tenth transistor Q13, an eighth diode D8, a twenty-third resistor R23, a ninety-ninth resistor R99, and a first hundred resistor R100;

a base electrode of the tenth transistor Q13 is connected to a collector electrode of the ninth transistor Q9, a reflector electrode of the tenth transistor Q13 is connected to the second bias voltage, a collector electrode of the tenth transistor Q13 is connected to an anode electrode of the eighth diode D8, a cathode electrode of the eighth diode D8 is connected to one end of the twenty-third resistor R23, the other end of the twenty-third resistor R23 is connected to one end of the ninety-ninth resistor R99 and one end of the first hundred resistor R100, the other end of the ninety-ninth resistor R99 is connected to a gate electrode of the fifth MOS transistor, and the other end of the first hundred resistor R100 is connected to a gate electrode of the sixth MOS transistor;

and the fifth MOS tube and the sixth MOS tube are both MOS upper tubes.

Further as an optional embodiment, the lower tube driving unit includes an eleventh transistor Q11, a nineteenth diode D19, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirty-seventh resistor R30, and a sixty-seventh resistor R67;

a base of the eleventh transistor Q11 is connected to a collector of the thirteenth transistor Q13, an emitter of the eleventh transistor Q11 is connected to a second bias voltage, a collector of the eleventh transistor Q11 is connected to a positive electrode of the nineteenth diode D19, a negative electrode of the nineteenth diode D19 is connected to one end of the twenty-eighth resistor R28, and the other end of the twenty-eighth resistor R28 is connected to one end of the twenty-ninth resistor R29, one end of the thirty resistor R30, and one end of the sixty-seventh resistor R67, respectively;

the other end of the twenty-ninth resistor R29 is connected with the gate of a seventh MOS transistor, the other end of the thirty-seventh resistor R30 is connected with the gate of an eighth MOS transistor, and the other end of the sixty-seventh resistor R67 is connected with the gate of a fourteenth MOS transistor;

and the seventh MOS tube, the eighth MOS tube and the fourteenth MOS tube are all MOS lower tubes.

Further as an optional implementation, the upper tube discharge unit includes a sixth transistor Q6, a forty-ninth resistor R49, a fifty-third resistor R53, a nineteenth resistor R19, and a twenty-first capacitor C21;

a base of the sixth transistor Q6 is connected to a collector of the tenth transistor Q10, an emitter of the sixth transistor Q6 is connected to the other end of the twenty-third resistor R23, a collector of the sixth transistor Q6 is grounded via the fifty-third resistor R53 and a nineteenth resistor R19 in this order, and the forty-ninth resistor R49 is connected in series between the base and the collector of the sixth transistor Q6;

one end of the twenty-first capacitor C21 is connected to one end of the first hundred resistor R100, and the other end of the twenty-first capacitor C21 is connected to the collector of the sixth transistor Q6.

As a further alternative, the lower tube discharging unit includes a fourteenth transistor Q14 and a nineteenth resistor R19;

the base of the fourteenth transistor Q14 is connected to the collector of the eleventh transistor Q11, the emitter of the fourteenth transistor Q14 is connected to the other end of the twenty-eighth resistor, and the collector of the fourteenth transistor Q14 is grounded through the nineteenth resistor R19.

As a further optional implementation, the lower tube driving unit includes an overcurrent protection circuit, and the overcurrent protection circuit includes a seventy-sixth capacitor C76 and a thirty-third resistor R33;

one end of the seventy-sixth capacitor C76 is connected to one end of the nineteenth resistor R19, the other end of the seventy-sixth capacitor C76 is connected to one end of the thirty-third resistor R33, and the other end of the thirty-third resistor R33 is connected to the base of the eleventh transistor Q11.

Further as an optional implementation manner, the lower tube driving unit further includes a thirtieth diode D30, an anode of the thirtieth diode D30 is connected to the second bias voltage, and a cathode of the thirtieth diode D30 is connected to an emitter of the eleventh transistor Q11.

The above-described circuit is explained in detail below with reference to fig. 1-3.

The principle of normal driving and turning off of the MOS upper tube is as follows:

when the input signal IO1 is at a low level, the first bias voltage 3.3V forms a loop through the resistor R25, the transistor Q9, and the resistor R26 to be amplified, so that the transistor Q9 is turned on. After the transistor Q9 is turned on, the second bias voltage 15V forms a loop through the diode D9, the resistor R17, the transistor Q9 and the resistor R26, the transistor Q10 is also turned on, the transistor Q6 is turned off, the second bias voltage 15V performs pump-up charging through the diode D9, the resistor R49 and the capacitor C22 bootstrap circuit, and at the same time, the second bias voltage 15V performs normal driving on the MOS5 and the MOS6 through the transistor Q10, the diode D8, the resistor R23, the resistor R99 and the resistor R100, and the MOS5 and the MOS6 are turned on.

When the input signal IO1 is at a high level, the transistor Q9 and the transistor Q10 are turned off, the transistor Q6 is turned on, the MOS5 passes through the resistor R99, the MOS6 passes through the resistors R100 and C21, and then the discharging is performed through the transistor Q6, the resistor R49 and the resistor R131; at this time the corresponding MOS5 and MOS6 are turned off.

The principle of normal driving and switching off of the lower tube is as follows:

when the input signal IO2 is at a low level, the first bias voltage 3.3V forms a loop through the transistor Q13 and the resistor R31 to amplify, so that the transistor Q11 is turned on, and after the transistor Q11 is turned on, the second bias voltage 15V forms a loop through the diode D30, the transistor Q11, the transistor Q13 and the resistor R31, at this time, the transistor Q11 is also turned on, and the transistor Q14 is turned off. The second bias voltage 15V drives the MOS7, the MOS8 and the MOS14 by direct push-pull amplification through the diode D30, the transistor Q11, the diode D19, the resistor R28, the resistor R29 and the resistor R30, and at the same time, the second bias voltage 15V drives the MOS5 and the MOS6 normally through the Q10, the D8, the R23, the R99 and the R100.

When the input signal IO2 is at a high level, the transistor Q11 and the transistor Q13 are turned off, the transistor Q14 is turned on, and the MOS7, the MOS8 and the MOS14 pass through the resistor R29, the resistor R130, the capacitor C23 and the resistor R67, and then discharge after passing through the transistors Q14, R32 and R19. At this time the corresponding MOS7, MOS8, and MOS14 are turned off.

When the system is powered on, the upper tube needs to be charged by turning on the lower tube MOS7, the MOS8 and the MOS14, and the specific working process is as follows:

input IO1 is set to high, IO2 is set to low, that is, lower tube is turned on, and upper tube is turned off (this specific working process has been described above in detail, and is not described here any more);

IO2 is low, when the lower tube is switched on, 15V charges the electrolytic capacitor C22 to 15V through the diode D9 and the resistor R131;

when the input detects that the input IO1 is low and the input IO2 is high, namely when the upper tube is turned on and the lower tube is turned off, the voltages at the gates of the upper tube MOS5 and MOS6 of the upper tube MOS5 and MOS6 are raised to be 15V higher than the voltage at the U point through bootstrap power supply (the voltage at two ends of the electrolytic capacitor C22 cannot change suddenly).

The IGBT overcurrent protection principle is as follows:

when the IGBT is in overcurrent, the sense terminal detects a high level, and at this time, the sense terminal enters the base of the transistor Q11 through the capacitor C76 and the resistor R30 and is at the high level, so that the transistor Q11 is turned off, which blocks the path of the second bias voltage 15V to the MOS7, the MOS8 and the MOS14, thereby effectively protecting the IGBT from overcurrent damage.

The principle of the on-off timing sequence control of the IGBT is as follows:

when the IGBT upper tube is switched on, the MOS5 grid charging loop is: 15V → D8 → R23 → R99 drive MOS 5; the MOS6 gate charging loop is: 15V → D8 → R23 → R100 drive MOS 6.

When the upper tube of the IGBT is turned off, the grid discharge loop of the MOS5 is as follows: MOS5 → R99 → Q6 → R49 → R53 → R19 → ground for discharging; the MOS6 gate discharge loop is: MOS6 → R100 → C21 → R53 → R19 → ground.

When the IGBT lower tube is switched on, the MOS7 gate charging loop is as follows: 15V → D19 → R28 → R29 drive MOS 7; the MOS8 gate charging loop is: 15V → D19 → R28 → R30 → driving MOS 8; the MOS14 gate charging loop is: 15V → D19 → R28 → R167 → drive MOS 8.

When the lower tube of the IGBT is turned off, the gate discharge loop of the MOS7 is as follows: MOS7 → R29 → Q14 → R19 → ground for discharging; the MOS8 gate discharge loop is: MOS8 → R30 → Q14 → R19 → ground for discharging; the MOS14 gate discharge loop is: MOS14 → R67 → Q14 → R19 → ground.

Fig. 2 is a simulation circuit diagram of the IGBT drive circuit according to the present embodiment, and fig. 3 is a drive voltage waveform diagram of a MOS upper tube and a MOS lower tube obtained by simulation.

In summary, the IGBT driving circuit of this embodiment has the following beneficial effects compared with the prior art:

(1) the embodiment provides a novel low-cost high-performance medium and small power IGBT driving application circuit, which is simple in driving circuit, small in onboard volume, low in cost, high in reliability and good in economic and social application values.

(2) The small driving application circuit in the IGBT of the embodiment does not need any auxiliary power supply, simplifies the circuit, naturally reduces the common coupling link causing the parasitic oscillation of the circuit, has simple design circuit and small and exquisite elements, needs few external elements, simplifies the circuit and saves the area of a main circuit board.

(3) The low-power IGBT driving application circuit in the embodiment is suitable for single-tube, half-bridge and full-bridge driving, and is also suitable for series-parallel driving of medium-power and low-power IGBTs, so that the application range of the low-power IGBT driving application circuit is greatly expanded, and the low-power IGBT driving application circuit has very wide economic and social values.

While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are intended to be included within the scope of the present invention as defined by the appended claims.

Claims (9)

1. A low-cost high-performance IGBT drive circuit, characterized by comprising:

the signal input module is used for inputting a first PWM control signal and a second PWM control signal;

the driving module is used for controlling the working state of an MOS upper tube according to the first PWM control signal and controlling the working state of an MOS lower tube according to the second PWM control signal;

the discharging module comprises an upper tube discharging unit and a lower tube discharging unit, and the upper tube discharging unit is used for releasing the electric quantity on the grid of the MOS upper tube after the MOS upper tube is closed; the lower tube discharging unit is used for releasing the electric quantity on the grid of the MOS lower tube after the MOS lower tube is closed.

2. The IGBT driving circuit according to claim 1, wherein the signal input module comprises a first input module and a second input module;

the first input module comprises a twenty-fifth resistor, a twenty-sixth resistor and a ninth transistor;

one end of the twenty-fifth resistor is connected with a first bias voltage, the other end of the twenty-fifth resistor is connected with the base electrode of the ninth transistor, the emitter electrode of the ninth transistor is connected with one end of the twenty-sixth resistor, the other end of the twenty-sixth resistor inputs a first PWM control signal, and the collector electrode of the ninth transistor is connected with the driving module;

the second input module comprises a thirty-first resistor and a thirteenth transistor;

the base electrode of the thirteenth transistor is connected with a first bias voltage, the emitting electrode of the thirteenth transistor is connected with one end of the thirty-first resistor, the other end of the thirty-first resistor is input with a second PWM control signal, and the collector electrode of the thirteenth transistor is connected with the driving module.

3. The IGBT driving circuit with low cost and high performance as claimed in claim 2, wherein the driving module comprises an upper tube driving unit and a lower tube driving unit;

the upper tube driving unit is used for controlling the working state of an MOS upper tube, and the lower tube driving unit is used for controlling the working state of an MOS lower tube.

4. A low cost high performance IGBT drive circuit as defined in claim 3, wherein said top tube drive unit comprises a tenth transistor, an eighth diode, a twenty-third resistor, a ninety-nine resistor and a one hundred resistor;

a base electrode of the tenth transistor is connected with a collector electrode of the ninth transistor, a reflector electrode of the tenth transistor is connected with a second bias voltage, a collector electrode of the tenth transistor is connected with an anode electrode of the eighth diode, a cathode electrode of the eighth diode is connected with one end of the twenty-third resistor, the other end of the twenty-third resistor is respectively connected with one end of the ninety-ninth resistor and one end of the first hundred resistor, the other end of the ninety-ninth resistor is connected with a grid electrode of the fifth MOS transistor, and the other end of the first hundred resistor is connected with a grid electrode of the sixth MOS transistor;

and the fifth MOS tube and the sixth MOS tube are both MOS upper tubes.

5. The IGBT driving circuit with low cost and high performance as claimed in claim 3, wherein the lower tube driving unit comprises an eleventh transistor, a nineteenth diode, a twenty-eighth resistor, a twenty-ninth resistor, a thirty-eighth resistor and a sixty-seventh resistor;

a base electrode of the eleventh transistor is connected with a collector electrode of the thirteenth transistor, an emitter electrode of the eleventh transistor is connected with a second bias voltage, a collector electrode of the eleventh transistor is connected with an anode electrode of the nineteenth diode, a cathode electrode of the nineteenth diode is connected with one end of the twenty-eighth resistor, and the other end of the twenty-eighth resistor is respectively connected with one end of the twenty-ninth resistor, one end of the thirty-fifth resistor and one end of the sixty-seventh resistor;

the other end of the twenty-ninth resistor is connected with the grid electrode of the seventh MOS tube, the other end of the thirty-eighth resistor is connected with the grid electrode of the eighth MOS tube, and the other end of the sixty-seventh resistor is connected with the grid electrode of the fourteenth MOS tube;

and the seventh MOS tube, the eighth MOS tube and the fourteenth MOS tube are all MOS lower tubes.

6. The low-cost high-performance IGBT driving circuit according to claim 4, wherein the upper tube discharging unit comprises a sixth transistor, a forty-ninth resistor, a fifty-third resistor, a nineteenth resistor and a twenty-first capacitor;

a base electrode of the sixth transistor is connected with a collector electrode of the tenth transistor, an emitter electrode of the sixth transistor is connected with the other end of the twenty-third resistor, a collector electrode of the sixth transistor is grounded sequentially through the fifty-third resistor and the nineteenth resistor, and the forty-ninth resistor is connected in series between the base electrode and the collector electrode of the sixth transistor;

one end of the twenty-first capacitor is connected with one end of the first hundred resistor, and the other end of the twenty-first capacitor is connected with the collector electrode of the sixth transistor.

7. The IGBT driving circuit with low cost and high performance as claimed in claim 5, wherein the down tube discharging unit comprises a fourteenth transistor and a nineteenth resistor;

the base of the fourteenth transistor is connected to the collector of the eleventh transistor, the emitter of the fourteenth transistor is connected to the other end of the twenty-eighth resistor, and the collector of the fourteenth transistor is grounded through the nineteenth resistor.

8. The IGBT driving circuit of claim 7, wherein the down tube driving unit comprises an overcurrent protection circuit comprising a seventy-sixth capacitor and a thirty-third resistor;

one end of the seventy-sixth capacitor is connected with one end of the nineteenth resistor, the other end of the seventy-sixth capacitor is connected with one end of the thirty-third resistor, and the other end of the thirty-third resistor is connected with the base electrode of the eleventh transistor.

9. The IGBT driving circuit of claim 5, wherein the down tube driving unit further comprises a thirtieth diode, an anode of the thirtieth diode is connected to the second bias voltage, and a cathode of the thirtieth diode is connected to an emitter of the eleventh transistor.

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