CN214176040U - Chip packaging structure and electronic product - Google Patents
Chip packaging structure and electronic product Download PDFInfo
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- CN214176040U CN214176040U CN202120074514.7U CN202120074514U CN214176040U CN 214176040 U CN214176040 U CN 214176040U CN 202120074514 U CN202120074514 U CN 202120074514U CN 214176040 U CN214176040 U CN 214176040U
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Abstract
The utility model discloses a chip packaging structure and electronic product, chip packaging structure includes: a first chip body having a first surface and a second surface parallel to each other, the first surface being formed with a first chip electrode; the second chip body is provided with a third surface and a fourth surface which are parallel to each other, the third surface is at least partially exposed to the outside, a second chip electrode is formed on the third surface, and at least part of the second surface is attached to the second surface so as to be electrically connected with the first chip body, so that the first chip electrode is electrically connected with the second chip electrode. The utility model discloses a chip packaging structure has reduced this packaging structure whole volume effectively to reduce its area occupied, the space that occupies the PCB board.
Description
Technical Field
The utility model belongs to the technical field of the chip architecture, more specifically say, it relates to a chip package structure and electronic product.
Background
Currently, in order to make a chip package achieve more functions, a plurality of chips are generally packaged together. Because each chip has each chip electrode, and each chip electrode needs to be drawn out respectively, consequently, the chip packaging body that has a plurality of chips is usually bulky, leads to the overall structure occupation space of chip packaging body great.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an aim at: the heat dissipation performance of the chip packaging structure is improved.
The above technical purpose of the present invention can be achieved by the following technical solutions:
provided is a chip packaging structure, including:
a first chip body having a first surface and a second surface parallel to each other, the first surface being formed with a first chip electrode; and
the second chip body is provided with a third surface and a fourth surface which are parallel to each other, the third surface is at least partially exposed to the outside, a second chip electrode is formed on the third surface, and at least part of the second surface is attached to the second surface so as to be electrically connected with the first chip body, so that the first chip electrode is electrically connected with the second chip electrode.
As a preferable technical solution of the chip packaging structure, the chip packaging structure further includes a chip carrier, the chip carrier has a fifth surface, and the second surface of the first chip body is soldered to the fifth surface of the chip carrier.
As a preferred technical solution of the chip package structure, the fifth surface is opposite to a portion of the third surface exposed to the outside, and the second chip electrode is soldered to the fifth surface of the chip carrier at the opposite portion.
As a preferable technical solution of the chip packaging structure, the second chip electrode is provided with a solder ball soldered to the fifth surface of the chip carrier.
As a preferable technical solution of the chip package structure, the second chip electrode includes a second chip source electrode, a second chip gate electrode, and a second chip drain electrode, and the second chip source electrode, the second chip gate electrode, and the second chip drain electrode are respectively welded to the chip carrier.
As a preferable technical solution of the chip package structure, the first chip electrode includes a first chip source electrode, a first chip gate electrode, and a first chip drain electrode, and the first chip source electrode is electrically connected to the second chip source electrode, the first chip gate electrode is electrically connected to the second chip gate electrode, and the first chip drain electrode is electrically connected to the second chip drain electrode.
As a preferable technical solution of the chip package structure, sintered silver or silver epoxy is used for soldering between the first chip body and the second chip body and/or between the first chip body and the chip carrier.
As an optimized technical scheme of the chip packaging structure, the chip carrier is a lead frame or a ceramic copper-clad plate.
As a preferred technical solution of the chip package structure, the first chip body is a silicon carbide chip, and the second chip body is a silicon carbide chip or a silicon chip.
The utility model discloses still an electronic product has foretell chip packaging structure.
To sum up, the utility model discloses following beneficial effect has:
the utility model provides a chip packaging structure, including first chip body and second chip body, the first surface of first chip body forms first chip electrode, the third surface of second chip body has at least part to expose in the outside, and be formed with second chip electrode, the third surface still has at least part and first surface laminating, so that first chip electrode is connected with second chip electrode electricity, make first chip electrode derive by second chip electrode, namely, the chip electrode of first chip body and the chip electrode of second chip body all derive through second chip electrode, make this packaging structure only need set up the derivation structure of second chip electrode, and only need plan on the PCB board correspond to the hookup location of second chip electrode can, this packaging structure whole volume has been reduced effectively, in order to reduce its area occupied that occupies the PCB board, A space.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of the chip package structure of the present invention.
In the figure:
100. a chip package structure; 10. a first chip body; 10a, a first surface; 10b, a second surface; 20. a second chip body; 20a, a third surface; 21. a second chip gate; 211. a grid solder ball; 22. a second chip source; 221. a source solder ball; 23. a second chip drain; 231. a drain solder ball; 30. a chip carrier; 30a, fifth surface.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a chip package structure 100.
Referring to fig. 1, the structure of the chip package structure 100 is described in detail below, and the chip package structure 100 includes:
a first chip body 10 having a first surface 10a and a second surface 10b parallel to each other, the first surface 10a being formed with a first chip electrode; and
the second chip body 20 has a third surface 20a and a fourth surface parallel to each other, the third surface 20a is at least partially exposed to the outside, and a second chip electrode is formed on the third surface, and at least partially attached to the second surface 10b to be electrically connected to the first chip body 10, so that the first chip electrode and the second chip electrode are electrically connected to each other.
In this embodiment, the first chip body 10 and the second chip body 20 may be power chips, and the functions implemented by the two chips are different, so that the whole package structure implements multiple different functions. Specifically, the first chip body 10 and the second chip body 20 are rectangular, and the second chip body 20 is stacked above the first chip body 10, so that the overall structure is more compact, and the reduction of the occupied space of the overall structure is facilitated.
The first surface 10a of the first chip body 10 is attached to the third surface 20a of the second chip body 20, so that the first chip electrode formed on the first chip body 10 is electrically connected to the second chip body 20, and further the first chip electrode is electrically connected to the second chip electrode, and the first chip electrode is led out from the second chip electrode, and meanwhile, the second chip electrode is disposed on the position where the third surface 20a of the second chip body 20 is exposed to the outside, so that the second chip electrode is connected to an external PCB board, that is, the chip electrode of the first chip body 10 and the chip electrode of the second chip body 20 are led out through the second chip electrode.
So set up, this packaging structure only need set up the derivation structure of second chip electrode, promptly, only need plan on the PCB board corresponding to the second chip electrode the hookup location can, this packaging structure need not set up the derivation structure of first chip electrode again alone, also need not plan out the hookup location of first chip electrode on the PCB board yet, has saved the occupation space that this packaging structure occupy the PCB board effectively.
The chip package structure 100 of the present invention comprises a first chip body 10 and a second chip body 20, wherein a first surface 10a of the first chip body 10 forms a first chip electrode, a third surface 20a of the second chip body 20 has at least a portion exposed to the outside and forms a second chip electrode, and the third surface 20a is at least partially attached to the first surface 10a to electrically connect the first chip electrode and the second chip electrode, such that the first chip electrode is derived from the second chip electrode, i.e., the chip electrode of the first chip body 10 and the chip electrode of the second chip body 20 are derived through the second chip electrode, such that the package structure only needs to be provided with a derivation structure of the second chip electrode, and only a connection position corresponding to the second chip electrode needs to be planned on a PCB board, thereby effectively reducing the overall size of the package structure, so as to reduce the occupied area and space of the PCB.
As a preferred embodiment of the chip package structure 100, the chip package structure 100 further includes a chip carrier 30, the chip carrier 30 has a fifth surface 30a, and the second surface 10b of the first chip body 10 is soldered to the fifth surface 30a of the chip carrier 30.
Therefore, the internal circuits of the first chip body 10 and the second chip body 20 are led out from the chip carrier 30, so as to be connected by the wires of the external PCB, which is beneficial to meeting higher design requirements. Meanwhile, the second surface 10b of the first chip is soldered to the fifth surface 30a of the chip carrier 30, so that the connection structure between the first chip and the lead frame is more compact, the higher design requirements are met, the compactness of the whole packaging structure is ensured, the size is smaller, and more occupied space is not occupied.
In this embodiment, the chip carrier 30 is a lead frame, and certainly, in other embodiments, the chip carrier 30 may also be a ceramic copper-clad plate, which is not limited herein.
As a preferred technical solution of the chip package structure 100, the fifth surface 30a is opposite to the exposed portion of the third surface 20a, and the second chip electrode is soldered to the fifth surface 30a of the chip carrier 30 at the opposite portion.
Specifically, the second chip electrode is soldered on the chip carrier 30, so that the second chip electrode is led out from the chip carrier 30, that is, the first chip electrode and the second chip electrode are led out from the chip carrier 30 together, and meanwhile, the chip carrier 30 may rearrange the connection position of the second chip electrode according to the actual connection requirement to meet the higher design requirement.
It is worth to say that the third surface 20a of the second chip is opposite to the fifth surface 30a of the chip carrier 30, so that the second chip electrode is led out and connected by using the space between the second chip body 20 and the chip carrier 30 to form a lead-out structure for leading out the second chip electrode, and no more space needs to be planned for electrode lead-out, so that the overall structure is more compact, and the occupied space of the overall structure is effectively reduced.
In this embodiment, the second chip electrode includes a second chip source 22, a second chip gate 21 and a second chip drain 23, and the second chip source 22, the second chip gate 21 and the second chip drain 23 are respectively soldered to the chip carrier 30.
The second chip source 22, the second chip gate 21 and the second chip drain 23 are respectively connected to the chip carrier 30, so that the chip carrier 30 is respectively provided with connection positions corresponding to the electrodes, and the chip carrier 30 is also convenient to rewire for arranging the connection positions of the electrodes, thereby meeting higher design requirements.
In order to electrically connect the first chip electrode and the second chip electrode to derive the package structure of the first chip electrode, the first chip electrode includes a first chip source electrode, a first chip gate electrode and a first chip drain electrode, and the first chip source electrode is electrically connected to the second chip source electrode 22, the first chip gate electrode is electrically connected to the second chip gate electrode, and the first chip drain electrode is electrically connected to the second chip drain electrode 23.
In this configuration, the first chip source electrode is electrically connected to the second chip source electrode 22, so that the first chip source electrode is led out through the second chip source electrode 22, the first chip gate electrode is electrically connected to the second chip gate electrode, so that the first chip gate electrode is led out through the second chip gate electrode, and the first chip drain electrode is electrically connected to the second chip drain electrode 23, so that the first chip drain electrode is led out through the second chip drain electrode 23, so that the first chip source electrode, the first chip gate electrode and the first chip drain electrode are led out respectively.
As a preferred technical solution of the chip package structure 100, in order to facilitate the second chip electrode to be soldered on the chip carrier 30, the second chip electrode is provided with a solder ball soldered on the fifth surface 30a of the chip carrier 30.
Specifically, the solder ball includes a source solder ball 221, a gate solder ball 211 and a drain solder ball 231 for corresponding to each electrode of the second chip electrode, specifically, the source solder ball 221 is disposed on the second chip source 22, the gate solder ball 211 is disposed on the second chip gate, and the drain solder ball 231 is disposed on the second chip drain 23, so that each electrode is connected to the chip carrier 30.
In order to improve the heat dissipation performance of the whole package structure, sintered silver or silver epoxy resin is used for welding between the first chip body 10 and the second chip body 20 and/or between the first chip body 10 and the chip carrier 30.
Because the sintered silver or the silver epoxy resin has better heat-conducting property, namely, better heat dissipation performance, the product can have better heat dissipation performance after the material is adopted for welding.
In some embodiments, the first chip body 10 and the second chip body 20 are soldered by sintered silver or silver epoxy, so that the heat of the second chip body 20 is better transferred to the first chip body 10 and transferred from the first chip body 10 to the chip carrier 30, and the heat is rapidly dissipated to the outside through the chip carrier 30.
In some embodiments, the first chip body 10 and the chip carrier 30 are soldered by sintered silver or silver epoxy resin, so that the heat of the first chip body 10 is better transferred to the chip carrier 30, and is rapidly dissipated to the outside through the chip carrier 30.
In this scheme, in order to improve this packaging structure's heat dispersion to a great extent, first chip body 10 with between the second chip body 20 and first chip body 10 with adopt sintering silver or silver epoxy welding between the chip carrier 30 to make the heat of second chip body 20 transmit to first chip body 10 better, and by first chip body 10 to chip carrier 30 transmission better, give off the heat to the external world fast through chip carrier 30, so that the heat can dispel the heat to the external world fast, work under guaranteeing that first chip body 10 and second chip body 20 are in comparatively suitable temperature environment, in order to guarantee its normal operating.
As a preferred technical solution of the chip package structure 100, in order to ensure the structural stability of the first chip body 10 and the second chip body 20, the first chip body 10 is a silicon carbide chip, and/or the second chip body 20 is a silicon carbide chip or a silicon chip.
Because the silicon carbide chip or the silicon chip has excellent heat conduction and electric conduction performance and can resist oxidation at high temperature, the chip can adapt to more different environments, namely, the chip can be ensured to normally work under more different environments.
In some embodiments, the first chip body 10 and the second chip body 20 are silicon carbide chips.
In some embodiments, the first chip body 10 and the second chip body 20 are silicon chips.
The utility model discloses still provide an electronic product, have foretell chip package structure 100, because this electronic product has adopted the whole technical scheme of above-mentioned all embodiments, consequently have all beneficial effects that the technical scheme of above-mentioned embodiment brought at least, no longer give unnecessary details here.
It is above only the utility model discloses a preferred embodiment, the utility model discloses a scope of protection does not only confine above-mentioned embodiment, the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A chip package structure, comprising:
a first chip body having a first surface and a second surface parallel to each other, the first surface being formed with a first chip electrode;
the second chip body is provided with a third surface and a fourth surface which are parallel to each other, the third surface is at least partially exposed to the outside, a second chip electrode is formed on the third surface, and at least part of the second surface is attached to the second surface so as to be electrically connected with the first chip body, so that the first chip electrode is electrically connected with the second chip electrode.
2. The chip packaging structure according to claim 1, further comprising a chip carrier having a fifth surface, the second surface of the first chip body being soldered to the fifth surface of the chip carrier.
3. The chip package structure according to claim 2, wherein the fifth surface is opposite to a portion of the third surface exposed to the outside, and the second chip electrode is soldered to the fifth surface of the chip carrier at the opposite portion.
4. The chip package structure according to claim 3, wherein the second chip electrode is provided with a solder ball bonded to the fifth surface of the chip carrier.
5. The chip package structure of claim 2, wherein the second chip electrode comprises a second chip source, a second chip gate, and a second chip drain, the second chip source, the second chip gate, and the second chip drain being soldered to the chip carrier, respectively.
6. The chip package structure of claim 5, wherein the first chip electrode comprises a first chip source, a first chip gate, and a first chip drain, the electrical connections between the first chip source and the second chip source, between the first chip gate and the second chip gate, and between the first chip drain and the second chip drain.
7. The chip package structure according to claim 2, wherein the first chip body and the second chip body and/or the first chip body and the chip carrier are soldered by sintered silver or silver epoxy.
8. The chip package structure of claim 2, wherein the chip carrier is a lead frame or a ceramic copper clad laminate.
9. The chip packaging structure according to claim 1, wherein the first chip body is a silicon carbide chip, and the second chip body is a silicon carbide chip or a silicon chip.
10. An electronic product having the chip package structure according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120074514.7U CN214176040U (en) | 2021-01-12 | 2021-01-12 | Chip packaging structure and electronic product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120074514.7U CN214176040U (en) | 2021-01-12 | 2021-01-12 | Chip packaging structure and electronic product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214176040U true CN214176040U (en) | 2021-09-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120074514.7U Active CN214176040U (en) | 2021-01-12 | 2021-01-12 | Chip packaging structure and electronic product |
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| Country | Link |
|---|---|
| CN (1) | CN214176040U (en) |
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2021
- 2021-01-12 CN CN202120074514.7U patent/CN214176040U/en active Active
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