CN214151682U - FC simulation test device based on PCIE interface - Google Patents

Abstract

The utility model discloses a FC emulation testing arrangement based on PCIE interface, the device includes: the device comprises a PCIE module, a power supply module, an FC bus module, a storage module and an FPGA chip; the PCIE module is used for providing an input voltage signal for the power supply module, forwarding data sent by the upper computer to the FPGA chip and forwarding data sent by the FPGA chip to the upper computer; the power supply module is used for generating and outputting various output voltage signals according to the input voltage signals; the FC bus module is used for realizing data transmission between the FPGA chip and external equipment to be tested; the storage module is used for caching data transmitted by the FC bus module and data transmitted by the PCIE module; and the FPGA chip is used for carrying out data transmission with an upper computer through the PCIE module, carrying out data transmission with external equipment to be tested through the FC bus module, and analyzing received data. The utility model is suitable for a fibre channel carries out data transmission.

Description

FC simulation test device based on PCIE interface

Technical Field

The utility model relates to a simulation test technical field especially relates to a FC simulation testing arrangement based on PCIE interface.

Background

With the development of communication technology, avionics systems have higher and higher requirements for data transmission of bus networks. The Fiber Channel (FC) has the advantages of high bandwidth, low delay, long transmission distance, flexible topology, supporting multiple upper layer protocols and the like, is a high-speed serial communication protocol designed for adapting to the high-performance data transmission requirement, is very suitable for having higher requirements on the real-time performance and the reliability of data transmission and the like, and can meet the requirements of an avionic system on data transmission.

At present, MIL-STD-1553 is mainly adopted by an avionics system in the military field, and an optical fiber channel is mainly widely applied to the commercial field and is not applied to the military field, so that the problem of how to apply the optical fiber channel to data transmission in the military field becomes a urgent need to be solved.

SUMMERY OF THE UTILITY MODEL

The utility model provides a technical problem be: aiming at the blank of data transmission in the fiber channel in the military field in the prior art, the utility model provides a PCIE interface-based FC simulation test device, in the scheme provided by the utility model, on one hand, the data transmission is realized and is carried out between the external tested equipment and the FPGA chip through the fiber channel by arranging the FC bus module, and then a scheme for data transmission in the fiber channel in the military field is provided; on the other hand, the PCIE module is adopted to realize data transmission between the FPGA chip and the upper computer, so that the data transmission rate between the FPGA chip and the upper computer is improved.

In a first aspect, an embodiment of the present invention provides a FC simulation testing device based on PCIE interface, the device includes: the device comprises a PCIE module, a power supply module, an FC bus module, a storage module and an FPGA chip; wherein the content of the first and second substances,

the PCIE module is connected with the power supply module and the upper computer and used for providing an input voltage signal for the power supply module, forwarding data sent by the upper computer to the FPGA chip and forwarding data sent by the FPGA chip to the upper computer;

the power supply module is connected with the FC bus module, the storage module and the FPGA chip and is used for generating and outputting various output voltage signals according to the input voltage signals;

the FC bus module is connected with external tested equipment and the FPGA chip and used for realizing data transmission between the FPGA chip and the external tested equipment;

the storage module is connected with the FPGA chip and used for caching the data transmitted by the FC bus module and the data transmitted by the PCIE module;

the FPGA chip is used for carrying out data transmission with the upper computer through the PCIE module, carrying out data transmission with external equipment to be tested through the FC bus module, and analyzing received data.

In the scheme provided by the utility model, on one hand, data transmission is realized between the external tested equipment and the FPGA chip through the optical fiber channel by arranging the FC bus module, and a scheme applied to the optical fiber channel for data transmission in the military field is further provided; on the other hand, the PCIE module is adopted to realize data transmission between the FPGA chip and the upper computer, so that the data transmission rate between the FPGA chip and the upper computer is improved.

Optionally, the FC bus module includes at least two FC bus interface submodules.

Optionally, the storage module includes at least two DDR3 sub-modules, and each DDR3 sub-module is configured to store data transmitted by one of the FC bus interface sub-modules and data transmitted by the PCIE module, respectively.

Optionally, the method further comprises: a configuration module, a programmable clock module, and a reset module, wherein,

the configuration module is connected with the power module and the FPGA chip and used for loading configuration information and configuring the FPGA chip according to the configuration information;

the programmable clock module is connected with the power module and the FPGA chip and is used for receiving clock configuration information sent by the FPGA chip and configuring a PLL clock factor according to the clock configuration information;

the reset module is connected with the power module and the FPGA chip and used for resetting the FPGA chip.

Optionally, the configuration module loads the configuration information in a BPI synchronous Flash manner.

Optionally, the reset module includes: a resistor, a capacitor and a reset key switch;

the reset module is specifically configured to: after power is connected, the capacitor is charged through the resistor, so that a reset pin of the FPGA chip is pulled to a high level from a low level, and a power-on reset process is completed; when a user presses the reset key switch, the switch is closed, and the capacitor discharges to the ground through the resistor, so that the reset pin of the FPGA chip is pulled to a low level from a high level.

Drawings

Fig. 1 is a schematic structural diagram of an FC simulation testing apparatus based on a PCIE interface according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a power module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a reset module according to an embodiment of the present invention.

Detailed Description

The embodiment of the present invention provides a solution, the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

The following describes in further detail an FC simulation testing apparatus based on PCIE interface provided in the embodiments of the present invention with reference to the attached drawings of the specification, and with reference to fig. 1, the apparatus includes: the device comprises a PCIE module 1, a power module 2, an FC bus module 3, a storage module 4 and an FPGA chip 5; wherein the content of the first and second substances,

the PCIE module 1 is connected with the power module 2 and an upper computer and is used for providing an input voltage signal for the power module 2, forwarding data sent by the upper computer to the FPGA chip 5 and forwarding data sent by the FPGA chip 5 to the upper computer;

the power module 2 is connected with the FC bus module 3, the storage module 4 and the FPGA chip 5, and is configured to generate and output a plurality of output voltage signals according to the input voltage signal;

the FC bus module 3 is connected with external tested equipment and the FPGA chip 5 and is used for realizing data transmission between the FPGA chip 5 and the external tested equipment;

the storage module 4 is connected with the FPGA chip 5 and is configured to cache data transmitted by the FC bus module 3 and data transmitted by the PCIE module 1;

the FPGA chip 5 is used for performing data transmission with the upper computer through the PCIE module 1, performing data transmission with external equipment to be tested through the FC bus module 3, and analyzing received data.

Specifically, in the scheme provided by the utility model, PCIE module 1 can adopt X4 bus mode, i.e. 4-bit bus mode, the Clock signal of PCIE bus is divided into 4 paths of PCIE differential signals through a Clock Buffer (Clock Fan out Buffer), and the 4 paths of PCIE differential signals are input to FPGA chip 5, so that PCIE module 1 is connected with FPGA chip 5; in addition, the PCIE module 1 may also provide an input voltage signal to the power module 2, where the input voltage signal may be 12V voltage. The power module 2 may generate a plurality of output voltage signals according to the input voltage signal provided by the PCIE module 1 to implement power supply for other modules, for example, the plurality of output voltage signals may include at least six voltage signals, such as 1.0V, 1.8V, 3.3V, MGT _1.8V, MGT _1.2V, MGT _1.0V, and the like. Refer to fig. 2, which is a schematic structural diagram of a power module according to the present invention.

Further, in the solution provided by the present invention, the selectable models of the FPGA chip 5 are various, and XC7K160T-2FFG676I of kilnex corporation Kintex-7 series can be selected, or other models can be selected, which is not limited herein.

In order to improve the communication stability of the FC simulation test apparatus, in a possible implementation manner, the FC bus module 3 includes at least two FC bus interface sub-modules 31.

Specifically, the utility model provides an among the scheme, arbitrary FC bus interface submodule 31 breaks down in FC bus module 3, when can not carrying out data transmission with external equipment under test, can carry out data transmission through FC bus interface submodule 31 except arbitrary FC bus interface submodule 31 in the two tunnel FC bus interface submodules at least and external equipment under test, guarantee normally to carry out data transmission with external equipment under test, and then adopt redundant FC bus interface submodule to improve FC emulation testing arrangement's communication stability.

In a possible implementation manner, the storage module 4 includes at least two DDR3 sub-modules 41, and each DDR3 sub-module 41 is configured to store one path of data transmitted by the FC bus interface sub-module 31 and one path of data transmitted by the PCIE module 1 respectively

Specifically, in the solution provided by the present invention, the DDR3 sub-module 41 may include two DDR3 SDRAM chips, wherein the DDR3 SDRAM chip model may be MT41K256M16HA-125VIT of Micron corporation, E, whose monolithic size is 512MB, i.e. providing 4Gbit storage space, the data bus width is 16 bits, and its highest data transmission rate supports MT 1600/s; that is, the utility model discloses in adopt 4 DDR3 SDRAM chips altogether, every two DDR3 SDRAM chips constitute a 32 DDR3 submodule 41 of bit, and every 32 DDR3 submodule 41 is as the data buffer memory of arbitrary FC bus interface submodule 31 respectively.

In one possible implementation manner, the method further includes: a configuration module 6, a programmable clock module 7, and a reset module 8, wherein,

the configuration module 6 is connected with the power module 2 and the FPGA chip 5, and is configured to load configuration information and configure the FPGA chip 5 according to the configuration information;

the programmable clock module 7 is connected to the power module 2 and the FPGA chip 5, and configured to receive clock configuration information sent by the FPGA chip 5 and configure a PLL clock factor according to the clock configuration information;

the reset module 8 is connected with the power module 2 and the FPGA chip 5 and is used for resetting the FPGA chip 5.

Further, in a possible implementation manner, the configuration module 6 loads the configuration information in a BPI synchronous Flash manner.

Specifically, in the utility model provides an in the scheme, in order to guarantee that PCIE module 1 can be discerned by the host computer mainboard, must guarantee to accomplish FPGA chip 5's loading before the mainboard loading is accomplished, consequently, configuration module 6 selects the synchronous Flash mode of BPI that the loading speed is the fastest. The Flash is PC28F256G18F NOR Flash of magnesium light, and the capacity of the Flash is 256Mb, 16-bit data bus.

Further, in order to guarantee that FC bus module 3 can carry out data transmission through different rates according to the actual demand the utility model provides an in the scheme, FC emulation testing arrangement still includes clock module 7 able to programme. The FC simulation test device utilizes the DDR3 submodule 41 to buffer the transmit FIFO and the receive FIFO of each channel of the FC bus interface submodule 31, and the transceiving rate, the working mode, and the like of each channel of the FC bus interface submodule 31 can be configured independently through a register, wherein the optical module selected by each channel of the FC bus interface submodule 31 is SFP package of Finisar manufacturers, and the optical module FTLF8528P3BxV with an LC interface type supports 1.0625Gbps, 2.125Gbps, 3.1875Gbs, and 4.25 Gbps. And the programmable clock module 7 receives the clock configuration information sent by the FPGA chip 5 and configures PLL clock factors according to the clock configuration information.

Referring to fig. 3, in one possible implementation, the reset module 8 includes: a resistor 81, a capacitor 82, and a reset key switch 83;

the reset module 8 is specifically configured to: after power is connected, the capacitor 82 is charged through the resistor 81, so that the reset pin of the FPGA chip 5 is pulled from a low level to a high level, and a power-on reset process is completed; when the reset key switch 83 is pressed by the user, the switch is closed, and the capacitor 82 discharges to ground through the resistor 81, so that the reset pin of the FPGA chip 5 is pulled from high level to low level.

In the scheme provided by the utility model, on one hand, the data transmission between the external tested equipment and the FPGA chip 5 is realized through the optical fiber channel by arranging the FC bus module 3, and a scheme applied to the optical fiber channel for data transmission in the military field is further provided; on the other hand, the PCIE module 1 is adopted to realize data transmission between the FPGA chip 5 and the upper computer, so that the data transmission rate between the FPGA chip 5 and the upper computer is improved.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (6)

1. An FC simulation test device based on PCIE interface is characterized by comprising: the device comprises a PCIE module, a power supply module, an FC bus module, a storage module and an FPGA chip; wherein the content of the first and second substances,

the PCIE module is connected with the power supply module and the upper computer and used for providing an input voltage signal for the power supply module, forwarding data sent by the upper computer to the FPGA chip and forwarding data sent by the FPGA chip to the upper computer;

the power supply module is connected with the FC bus module, the storage module and the FPGA chip and is used for generating and outputting various output voltage signals according to the input voltage signals;

the FC bus module is connected with external tested equipment and the FPGA chip and used for realizing data transmission between the FPGA chip and the external tested equipment;

the storage module is connected with the FPGA chip and used for caching the data transmitted by the FC bus module and the data transmitted by the PCIE module;

the FPGA chip is used for carrying out data transmission with the upper computer through the PCIE module, carrying out data transmission with external equipment to be tested through the FC bus module, and analyzing received data.

2. The apparatus of claim 1, wherein the FC bus module comprises at least two FC bus interface submodules.

3. The apparatus of claim 2, wherein the storage module comprises at least two DDR3 sub-modules, and each DDR3 sub-module is configured to store one path of data transmitted by the FC bus interface sub-module and one path of data transmitted by the PCIE module.

4. The apparatus of any of claims 1 to 3, further comprising: a configuration module, a programmable clock module, and a reset module, wherein,

the configuration module is connected with the power module and the FPGA chip and used for loading configuration information and configuring the FPGA chip according to the configuration information;

the programmable clock module is connected with the power module and the FPGA chip and is used for receiving clock configuration information sent by the FPGA chip and configuring a PLL clock factor according to the clock configuration information;

the reset module is connected with the power module and the FPGA chip and used for resetting the FPGA chip.

5. The apparatus of claim 4, wherein the configuration module loads the configuration information in a BPI synchronous Flash manner.

6. The apparatus of claim 5, wherein the reset module comprises: a resistor, a capacitor and a reset key switch;

the reset module is specifically configured to: after power is connected, the capacitor is charged through the resistor, so that a reset pin of the FPGA chip is pulled to a high level from a low level, and a power-on reset process is completed; when a user presses the reset key switch, the switch is closed, and the capacitor discharges to the ground through the resistor, so that the reset pin of the FPGA chip is pulled to a low level from a high level.

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