CN213692054U

CN213692054U - Low-capacitance protection device

Info

Publication number: CN213692054U
Application number: CN202022810249.2U
Authority: CN
Inventors: 许志峰; 宋文龙; 张鹏; 刘志雄
Original assignee: Jiangsu Jilai Microelectronics Co ltd
Current assignee: Jiangsu Jilai Microelectronics Co ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2021-07-13
Anticipated expiration: 2030-11-30

Abstract

The utility model discloses a low-capacitance protective device, which comprises a P-type substrate material (101), wherein a P-type epitaxial layer (102) is arranged on the P-type substrate material (101); a P-type buried layer (103) and a dielectric layer (104) are arranged on the P-type epitaxial layer (102); an N-type diffusion region (105) is arranged on the P-type buried layer (103); an isolation dielectric layer (106) is arranged on the dielectric layer (104) and the N-type diffusion region (105); a first metal area (107) and a second metal area (108) are respectively arranged on two sides of the isolation dielectric layer (106). The utility model discloses can reduce electric capacity, obtain lower clamping voltage.

Description

Low-capacitance protection device

Technical Field

The utility model belongs to the technical field of electronic science and mainly relate to integrated circuit Electrostatic Discharge (ESD-Electrostatic Discharge) protection field, specifically a low electric capacity protection device.

Background

Electrostatic discharge (ESD) is widely present in everyday environments, and is the phenomenon of mutual transfer of electrostatic charges between two media with different electrostatic potentials. ESD is an over-speed discharge phenomenon, the instantaneous large current and high voltage of which can damage or degrade IC components. ESD can cause latent damage to semiconductor devices, such as increased leakage current and the occurrence of logic errors; and permanent damage, including PN junction burnout, metal layer failure or oxide layer breakdown. No matter which damage, great loss in production and life can be caused, so that the ESD protection device is required to discharge large current, and the purpose of protecting the working device is achieved.

As semiconductor processing advances, the feature size and gate oxide thickness of integrated circuits continue to decrease and the operating frequency continues to increase, placing more stringent requirements on ESD protection devices. The ESD protection device is required to not only meet the requirements of the design window, but also consider the influence of its parasitic capacitance on the internal circuit. The ESD protection device needs to carry a large current when an ESD event occurs, and thus requires a large chip area to discharge heat, which leads to an increase in the manufacturing cost of the chip and a degradation in the high frequency characteristics of the circuit. For integrated circuits, the transmission of high speed signals does not allow for signal loss, and therefore the need for low capacitance is critical.

Since ESD pulses appear on IC pins in both positive and negative directions, discharge paths in both directions need to be considered when designing the protection network. The traditional ESD protective device can only provide one-way protection, at least one protective device needs to be arranged in each mode, a large amount of layout area is occupied, and other parasitic effects can be brought by the monolithic integration of a plurality of devices, so that the bidirectional ESD protective device is inevitable. The structure of a conventional triode bidirectional ESD protection device is shown in fig. 2, and includes: the P-type single crystal material 109, the P-type adjustment region 110, the dielectric layer 104, the isolation dielectric layer 106, and the two metal regions one 107. In the bidirectional ESD protection structure, when a positive potential is applied to the first metal area 107 and a negative potential is applied to the second metal area 108, or a positive potential is applied to the second metal area 108 and a negative potential is applied to the first metal area 107, ESD pulses can be discharged through the lateral NPN triode. To reduce capacitance, the P-type single crystal material 109 is a high resistivity material, which results in an increase in the avalanche voltage of the device, and to reduce the avalanche voltage, a higher doping concentration P-type adjustment region 110 is added. The contradiction between low capacitance and low avalanche voltage can be relieved through the P-type adjusting region with higher doping concentration, but on the basis, the structure shown in FIG. 1 can further reduce the capacitance of the bidirectional ESD protection device, and meanwhile, the low avalanche voltage can be obtained.

The utility model provides an optimization scheme can provide a low capacitance protection device, can obtain controllable breakdown voltage and lower clamping voltage.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, the utility model provides a low capacitance protection device, which comprises a P-type substrate material, wherein a P-type epitaxial layer is arranged on the P-type substrate material; a P-type buried layer and a dielectric layer are arranged on the P-type epitaxial layer; an N-type diffusion region is arranged on the P-type buried layer; an isolation dielectric layer is arranged on the dielectric layer and the N-type diffusion region; and a first metal area and a second metal area are respectively arranged on two sides of the isolation medium layer.

A manufacturing method of a low-capacitance protection device comprises the following steps:

step one, carrying out first epitaxy of a P-type material on the P-type substrate material.

And step two, growing a sacrificial oxide layer on the P-type epitaxial layer. And photoetching the P-type buried layer pattern, and carrying out boron implantation.

And step three, removing the oxide layer, continuing to perform second epitaxy on the P-type material, and diffusing boron in the P-type epitaxial layer to form a P-type buried layer.

And fourthly, growing an oxide layer on the P-type epitaxial layer, photoetching a groove area pattern, and etching the groove. And after the groove is etched, growing an oxide layer with P-type impurities, and carrying out chemical mechanical polishing to form a dielectric layer with negative charges.

And step five, growing an oxide layer on the P-type epitaxial layer 102, photoetching a primary N-type diffusion region 105 graph, injecting phosphorus and pushing a junction.

And step six, etching the surface oxide layer completely by a wet method, and growing a sacrificial oxide layer. And photoetching a dielectric layer pattern and an N-type diffusion region pattern. And injecting phosphorus, and pushing the junction to form an N-type diffusion region and a complete dielectric layer.

And seventhly, growing an oxide layer on the P-type epitaxial layer, photoetching a medium layer pattern with negative charges, and etching the medium layer. And depositing an isolation dielectric layer on the front surface.

And step eight, forming a contact hole area by front-side photoetching. Sputtering or evaporating metal. And photoetching the front metal to form a metal area. And (3) alloying.

Further, the first time P-type epitaxial resistivity in the first step is 0.01-100 Ω · cm.

Furthermore, the boron implantation dose in the second step is 1E13-2E15cm-2, and the energy is 30-80 KeV. The temperature condition of the boron push-bonding is 1000-1250 ℃, and the time is 30-150 min.

Further, the second P-epi resistivity in step three is the same as the first P-epi resistivity in step one.

Furthermore, the depth of the groove in the fourth step is 0.5-2 μm.

Furthermore, the dose of phosphorus implantation in the fifth step is 1E14-1E16cm-2, and the energy is 60-120 KeV. The temperature condition of the phosphorus push-bonding is 1000-1250 ℃, and the time is 30-150 min.

Further, the dose of phosphorus implantation in the sixth step is 1E13-2E15cm-2, and the energy is 40-80 KeV. The temperature condition of the phosphorus push-bonding is 950-.

Further, the isolation dielectric layer in the seventh step is tetraethoxysilane TEOS, and the thickness is 5000-.

Further, after the contact hole is subjected to photoetching in the step eight, depositing a layer of TI/TIN; the metal sputtered or evaporated on the front surface is aluminum or aluminum copper or aluminum-silicon-copper, and the thickness is 2-4 um. The temperature of the alloy is 300-600 ℃, and the time is 20-50 min.

The utility model has the advantages as follows:

1. the utility model discloses the dielectric layer of taking negative charge of introduction can further reduce two-way ESD protection device electric capacity.

2. The utility model discloses a reduce electric capacity can obtain the capacitance value of demand through the resistivity of adjustment P type epitaxial layer.

3. The utility model discloses a concentration distribution of the N type diffusion zone that the P type buried layer structure obtained and separately pour into twice around and, can adjust the breakdown voltage of device, reduce epitaxial layer resistivity to breakdown voltage's influence.

4. The utility model discloses the negatively charged dielectric layer of introduction makes the utility model provides an ESD protection device and traditional triode structure can adopt higher epitaxial layer resistivity under the same electric capacity to obtain lower clamping voltage.

Drawings

Fig. 1 is a sectional structure view of the present invention.

Fig. 2 is a schematic cross-sectional view of a conventional triac ESD protection device.

Fig. 3-10 are schematic diagrams of the manufacturing method of the present invention.

In the figure, 101, a P-type substrate material, 102, a P-type epitaxial layer, 103, a P-type buried layer, 104, a dielectric layer, 105, an N-type adjusting region, 106, an isolation dielectric layer, 107, a first metal region, 108 and a second metal region.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and embodiments. The details will be described by taking a voltage level of 5V as an example.

The embodiment uses a 5V voltage level for detailed description.

As shown in fig. 1, a low capacitance protection device includes: the structure comprises a P-type substrate material 101, a P-type epitaxial layer 102, a P-type buried layer 103, a dielectric layer 104, an N-type diffusion region 105, an isolation dielectric layer 106, a first metal region 107 and a second metal region 108. A P-type epitaxial layer 102 is arranged on the P-type substrate material 101; a P-type buried layer 103 and a dielectric layer 104 are arranged on the P-type epitaxial layer 102; an N-type diffusion region 105 is arranged on the P-type buried layer 103; an isolation dielectric layer 106 is arranged on the dielectric layer 104 and the N-type diffusion region 105; a first metal region 107 and a second metal region 108 are respectively disposed on two sides of the isolation dielectric layer 106.

as shown in fig. 3, a P-type epitaxial layer 102 is grown on a P-type substrate material 101 for the first time, and the first-time P-type epitaxial resistivity is 0.01 to 100 Ω · cm.

As shown in fig. 4, a sacrificial oxide layer is grown on P-type epitaxial layer 102. And photoetching a P-type buried layer 103 pattern, and carrying out boron implantation. The boron implantation dose is 1E13-2E15cm-2, and the energy is 30-80 KeV. The temperature condition of the boron push-bonding is 1000-1250 ℃, and the time is 30-150 min.

As shown in fig. 5, the oxide layer is removed, the second P-type epitaxy is continued, and boron is diffused in the P-type epitaxial layer 102 to form the P-type buried layer 103. The second P-type epitaxial resistivity is the same as the first P-type epitaxial resistivity in the first step.

As shown in fig. 6, an oxide layer is grown on the P-type epitaxial layer 102, and the trench is etched by photolithography with a trench pattern. After the trench is etched, an oxide layer with P-type impurities is grown and chemical mechanical polishing is performed to form a dielectric layer 104 with negative charges. The depth of the groove is 0.5-2 μm.

As shown in fig. 7, an oxide layer is grown on the P-type epitaxial layer 102, and the preliminary N-type diffusion region 105 pattern is patterned by photolithography, phosphorus implantation, and junction push-off. The phosphorus implantation dose is 1E14-1E16cm-2, and the energy is 60-120 KeV. The temperature condition of the phosphorus push-bonding is 1000-1250 ℃, and the time is 30-150 min.

As shown in fig. 8, the wet etching process completely etches the surface oxide layer to grow a sacrificial oxide layer. A photoresist layer 104 pattern and an N-type diffusion region 105 pattern. And injecting phosphorus, and performing junction pushing to form a dielectric layer 104 and a complete N-type diffusion region 105. The phosphorus implantation dose is 1E13-2E15cm-2, and the energy is 40-80 KeV. The temperature condition of the phosphorus push-bonding is 950-.

As shown in fig. 9, an oxide layer is grown on the P-type epitaxial layer 102, and the dielectric layer 104 with negative charges is patterned and etched. An isolation dielectric layer 106 is deposited on the front side. The isolation dielectric layer 106 is tetraethoxysilane TEOS with a thickness of 5000-10000A.

As shown in fig. 10, contact hole regions are formed by front side lithography. Sputtering or evaporating metal. And performing front metal photoetching to form a first metal area 107 and a second metal area 108. And (3) alloying. And after the contact hole is subjected to photoetching, depositing a layer of TI/TIN. The contact resistance is reduced, and meanwhile, the failure rate of metal overheating can be effectively reduced. The metal sputtered or evaporated on the front surface is aluminum or aluminum copper or aluminum-silicon-copper, and the thickness is 2-4 um. The temperature of the alloy is 300-600 ℃, and the time is 20-50 min.

The utility model provides a two-way ESD protection architecture can further reduce device electric capacity, and the dielectric layer 104 that has the negative charge is the same electric charge type with N type diffusion zone 105 to make device electric capacity reduce. In order to further reduce the capacitance of the device, the N-type diffusion region 105 is separately implanted twice, so that the doping concentration of the side close to the isolation dielectric layer 106 is low, the doping concentration of the side far away from the isolation dielectric layer 106 is high, the surface doping concentration is low, and the junction capacitance is further reduced. In order to reduce the avalanche voltage of the ESD protection device, the surface breakdown point of the device is transferred into the body, and the avalanche breakdown point of the structure is transferred into the body by adopting a grooving process, so that the dielectric layer 104 and the isolation dielectric layer 106 have the surface PN junction breakdown path which is blocked. In order to control the avalanche voltage of the low-capacitance protection device, the P-type buried layer 103 with a higher doping concentration is utilized, and the N-type diffusion region 105 which is transversely doped in a variable mode also has a high doping concentration above the P-type buried layer 103, so that the peak electric field of the device can be transferred to a PN junction formed by the P-type buried layer 103 and the N-type diffusion region 105 in the body from the surface, and the breakdown voltage of the device can be adjusted by adjusting the doping concentration of the P-type buried layer 103. The utility model provides a two-way ESD protection device of low electric capacity has further reduced the electric capacity of traditional triode structure ESD protection device, consequently under equal electric capacity level, the utility model provides a lower resistivity's epitaxial layer can be adopted to the ESD protection device, consequently under the same current that flows through, can obtain lower clamping voltage. The utility model provides a two-way ESD protection device of low electric capacity adds positive potential when metal area one 107, and two 108 plus negative potentials in metal area, perhaps two 108 plus positive potential in metal area, when a 107 plus negative potential in metal area, the ESD pulse all can be released through horizontal NPN triode.

Claims

1. A low capacitance protection device, characterized by: the epitaxial wafer comprises a P-type substrate material (101), wherein a P-type epitaxial layer (102) is arranged on the P-type substrate material (101); a P-type buried layer (103) and a dielectric layer (104) are arranged on the P-type epitaxial layer (102); an N-type diffusion region (105) is arranged on the P-type buried layer (103); an isolation dielectric layer (106) is arranged on the dielectric layer (104) and the N-type diffusion region (105); a first metal area (107) and a second metal area (108) are respectively arranged on two sides of the isolation dielectric layer (106).