CN213547683U - Multiplexing structure of input channel of switching matrix chip - Google Patents
Multiplexing structure of input channel of switching matrix chip Download PDFInfo
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- CN213547683U CN213547683U CN202023201557.1U CN202023201557U CN213547683U CN 213547683 U CN213547683 U CN 213547683U CN 202023201557 U CN202023201557 U CN 202023201557U CN 213547683 U CN213547683 U CN 213547683U
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Abstract
The utility model discloses a multiplex structure of switching matrix chip input channel, including two switching matrix chips, the input interface interconnect of two switching matrix chips, outside input signal line fall into two the tunnel input of respectively inputting two switching matrix chips through two resistances, and two resistances are put respectively in the top surface and the bottom surface of circuit board. The beneficial effects of the utility model reside in that, with low costs, the circuit is simple, easily realize.
Description
Technical Field
The utility model relates to a be used for video splicer/mixed matrix chip input channel multiplex structure.
Background
The video splicer/mixing matrix is a video switching device, and the video switching function is realized mainly through a switching matrix chip. All input and output video signals are switched by the switching matrix chip, so the capacity of the input and output channels can only be determined by the channel number of the switching matrix chip. Generally, the larger the number of channels of the switching matrix chip, the higher the cost. And the switching matrix chips with different channel numbers are packaged and have different sizes.
Disclosure of Invention
In order to overcome the defects of the prior art, the utility model provides a display screen fixed knot constructs, the utility model discloses just realize increasing output channel with two the same exchange matrix chips. This eliminates the need to replace the switch matrix chip with a larger number of channels.
In order to achieve the purpose of the invention, the utility model adopts the following technical scheme:
the utility model provides a multiplexing structure of switching matrix chip input channel, includes two switching matrix chips, the input interface interconnect of two switching matrix chips, the input that external input signal line divide into two the tunnel respectively and input two switching matrix chips through two resistances, and two resistances are put respectively on the top surface and the bottom surface of circuit board.
Preferably, the resistance value of the resistor is close to zero.
As a preferred scheme, the two resistors are overlapped, one end of each resistor is punched, and the resistors are connected with one end of each resistor through a through hole and are simultaneously connected with input signals; the other ends of the resistors are respectively connected to the input ends of the two switching matrix chips.
The beneficial effects of the utility model reside in that, multiplexing two exchange matrix chips compare to change the chip cost of bigger capacity lower. The circuit is simple and easy to realize.
Drawings
Fig. 1 is a schematic diagram of a single chip input/output structure.
Fig. 2 is a schematic diagram of a chip multiplexing input/output structure.
Fig. 3 is a schematic diagram of a resistive wiring structure.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
In this embodiment, an M21131V chip is taken as an example, and M21131V is a 1.6Gbps, 72-way high-speed low-power asynchronous switching matrix. The device can work at a direct current to a working frequency of 1.6Gbps and is suitable for broadcast video application. The differential signal path and signal modulation circuitry of M21131V minimizes jitter in long traces and cables and achieves reliable high speed drive and reception.
Such as the video splicer/mixing matrix of M21131V configuration shown in fig. 1, supports a maximum of 72 video signal inputs and a maximum of 72 video signal outputs. The present architecture has used the maximum capacity of M21131V. If the output channels need to be added, the M21131V chip must be replaced by another chip.
The utility model discloses what adopt is like the multiplexing structure of a chip that fig. 2 is shown, connects the input end interface of two M21131V chips simultaneously through two sections connecting wires, and the input card signal just inputs the input of two M21131V chips simultaneously like this, and two M21131V just can received signal simultaneously, also can export the output card, like this the utility model discloses a structure just can make the capacity of output increase one time.
As shown in fig. 3, each input signal line is divided into two paths through two 0 ohm resistors and respectively input to the input ends of two M21131V chips, the two resistors are respectively placed on the TOP surface TOP and the BOTTOM surface BOTTOM of the circuit board and are overlapped, a hole is formed in one end of each resistor, and one end of each resistor is connected through a via hole and is simultaneously connected with an input signal. The other ends of the resistors are respectively connected to the input ends of the two pieces of M21131V. This structure can minimize the signal loss after the signal at the input end is multiplexed.
Claims (3)
1. The multiplexing structure of the input channel of the switching matrix chip is characterized by comprising two switching matrix chips, wherein the input end interfaces of the two switching matrix chips are mutually connected, an external input signal line is divided into two paths through two resistors and respectively input to the input ends of the two switching matrix chips, and the two resistors are respectively arranged on the top surface and the bottom surface of a circuit board.
2. A switch matrix chip input channel multiplexing structure as claimed in claim 1, wherein the resistance of said resistors is close to zero.
3. The multiplexing structure of the input channels of the switching matrix chip of claim 1, wherein the two resistors are placed in a superposition manner, a hole is formed at one end of each resistor, and one end of each resistor is connected with one end of each resistor through a via hole and is simultaneously connected with an input signal; the other ends of the resistors are respectively connected to the input ends of the two switching matrix chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023201557.1U CN213547683U (en) | 2020-12-28 | 2020-12-28 | Multiplexing structure of input channel of switching matrix chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023201557.1U CN213547683U (en) | 2020-12-28 | 2020-12-28 | Multiplexing structure of input channel of switching matrix chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213547683U true CN213547683U (en) | 2021-06-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN202023201557.1U Active CN213547683U (en) | 2020-12-28 | 2020-12-28 | Multiplexing structure of input channel of switching matrix chip |
Country Status (1)
| Country | Link |
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| CN (1) | CN213547683U (en) |
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2020
- 2020-12-28 CN CN202023201557.1U patent/CN213547683U/en active Active
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