CN217739749U

CN217739749U - Switch control circuit

Info

Publication number: CN217739749U
Application number: CN202221146050.7U
Authority: CN
Inventors: 苏俊华; 黄荣柏; 晏道威; 张显禄
Original assignee: Intelligent Automation Equipment Zhuhai Co Ltd
Current assignee: Intelligent Automation Equipment Zhuhai Co Ltd
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2022-11-04
Anticipated expiration: 2032-05-13

Abstract

The utility model aims at providing a simple structure, it is with low costs, can save the on-off control circuit in integrated circuit board space. The utility model comprises a bus module and a non-buffer analog switch array module, wherein the bus module is in signal connection with the non-buffer analog switch array module, and the non-buffer analog switch array module is in signal connection with a plurality of tested devices; the bus module is used for connecting the microcontroller and peripheral equipment thereof to realize half-duplex communication; the bufferless analog switch array module is provided with an X-type connecting module and a Y-type connecting module, the X-type connecting module is used for connecting networks of at least 12 paths of tested equipment, and the Y-type connecting module is used for connecting networks of at least 8 paths of tested equipment. The utility model discloses be applied to electronic equipment test technical field.

Description

Switch control circuit

Technical Field

The utility model discloses be applied to electronic equipment test technical field, in particular to on-off control circuit.

Background

In the electronic device testing industry, the connection, the pull-up to 1.2V, 1.8V or 3.3V and the pull-down of some signals to the ground of the product-related network are often required in the mainboard function test, so that the switch circuit required by the method is required to be integrated in the board card function circuit of the testing device.

As shown in fig. 1, in the existing switching scheme, a relay, an electronic switch, an MOS transistor, a pull-up or pull-down current-limiting resistor are usually used, different devices need to be used according to different situations, and the enabling control of the switch is controlled by an IO extender chip controlled by I2C (two-wire serial bus), which is generally of CAT9555 type and has 16 input/output ports. However, when the tested device needs to pull up, pull down or short-circuit a larger number of networks, a larger number of switch circuits need to be repeated, and the switch scheme has insufficient advantages under the condition of limited material cost and board card space requirements. If a switch control circuit which is simple in structure, low in cost and capable of saving board card space can be designed, the problems can be well solved.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that overcome prior art not enough, provide a simple structure, it is with low costs, can save the on-off control circuit in integrated circuit board space.

The utility model adopts the technical proposal that: the utility model comprises a bus module and a non-buffer analog switch array module, wherein the bus module is in signal connection with the non-buffer analog switch array module, and the non-buffer analog switch array module is in signal connection with a plurality of tested devices;

the bus module is used for connecting the microcontroller and peripheral equipment thereof to realize half-duplex communication;

the bufferless analog switch array module is provided with an X-type connecting module and a Y-type connecting module, the X-type connecting module is used for connecting networks of at least 12 paths of tested equipment, and the Y-type connecting module is used for connecting networks of at least 8 paths of tested equipment.

Further, the bufferless analog switch array module includes an interface chip with a model number of ADG2128BCPZ, the X-type connection module and the Y-type connection module are both disposed on the interface chip, the X-type connection module includes 12 interfaces of X0-X11, the Y-type connection module includes 8 interfaces of Y0-Y7, and the 12 interfaces of X0-X11 and the 8 interfaces of Y0-Y7 form 96 switch channels.

Further, the Y-connection module is also used to pull up the network of the device under test to level 1V2, 1V8 or 3V3 and to ground.

Further, the bus module is an I2C bus.

Further, the bus module includes a bidirectional data line SDA and a clock line SCL, the interface chip is provided with an SDA terminal and an SCL terminal, and the bidirectional data line SDA and the clock line SCL are respectively connected with the SDA terminal and the SCL terminal.

The utility model has the advantages that:

1. has the advantages of material cost: compared with the existing switch control circuit, the number of IO expanders and switching elements in the existing switch control circuit can be saved under the condition of adopting the same control bus (I2C);

2. the method has the advantages of multi-channel selection: the bufferless analog switch array is provided with 12 paths of interfaces of X0-X11 and 8 paths of interfaces of Y0-Y7, and the 12 paths of interfaces of X0-X11 and the 8 paths of interfaces of Y0-Y7 can form 96 switch channels in an array mode. The 8-path interfaces of the Y0-Y7 can be pulled up to a level 1V2, 1V8 or 3V3, pulled down to a grounding end and subjected to short circuit between any two interfaces, and the functions of the existing switch control circuit can be completely covered;

3. has the advantages of space: to the higher integrated circuit board of space size requirement, because the utility model discloses can comparatively obviously reduce the quantity of current scheme switching device, consequently can effectively save the integrated circuit board space.

Drawings

FIG. 1 is a connection block diagram of a prior art switch control circuit;

fig. 2 is a connection block diagram of the present invention;

fig. 3 is a circuit schematic of the bufferless analog switch array module.

Detailed Description

As shown in fig. 2 and fig. 3, in this embodiment, the present invention includes a bus module 1 and a bufferless analog switch array module 2, wherein the bus module 1 is in signal connection with the bufferless analog switch array module 2, and the bufferless analog switch array module 2 is in signal connection with a plurality of devices under test 3;

the bus module 1 is used for connecting a microcontroller and peripheral equipment thereof to realize half-duplex communication;

the bufferless analog switch array module 2 is provided with an X-type connection module and a Y-type connection module, the X-type connection module is used for connecting at least 12 paths of networks of the tested equipment 3, and the Y-type connection module is used for connecting at least 8 paths of networks of the tested equipment 3.

In this embodiment, the bufferless analog switch array module 2 includes an interface chip with a model number of ADG2128BCPZ, the X-type connection module and the Y-type connection module are both disposed on the interface chip, the X-type connection module includes 12 interfaces of X0-X11, the Y-type connection module includes 8 interfaces of Y0-Y7, and the 12 interfaces of X0-X11 and the 8 interfaces of Y0-Y7 form 96 switch channels.

In this embodiment, the Y-connection module is further configured to pull up the network of the device under test 3 to a level 1V2, 1V8, or 3V3 and pull down to the ground.

In this embodiment, the bus module 1 is an I2C bus.

In this embodiment, the bus module 1 includes a bidirectional data line SDA and a clock line SCL, the interface chip is provided with an SDA terminal and an SCL terminal, and the bidirectional data line SDA and the clock line SCL are respectively connected to the SDA terminal and the SCL terminal.

In this embodiment, compared with the existing switch control circuit, the utility model has the following advantages: 1. the material cost advantage: under the condition of adopting the control bus (I2C) which is the same as the existing scheme, the number of IO expanders and switching elements in the existing switch control circuit can be saved; 2. the advantages of multichannel selection are as follows: the bufferless analog switch array is provided with 12 paths of interfaces of X0-X11 and 8 paths of interfaces of Y0-Y7, and the 12 paths of interfaces of X0-X11 and the 8 paths of interfaces of Y0-Y7 can form 96 switch channels in an array mode. The 8-path interfaces of the Y0-Y7 can be pulled up to levels 1V2, 1V8 or 3V3, and pulled down to a grounding terminal to perform short circuit between any two interfaces, so that the functions of the existing switch control circuit can be completely covered; 3. the space advantage is as follows: to the higher integrated circuit board of space size requirement, because the utility model discloses can comparatively obviously reduce the quantity of current scheme switching device, consequently can effectively save the integrated circuit board space.

Claims

1. A switch control circuit, characterized by: the device comprises a bus module (1) and a bufferless analog switch array module (2), wherein the bus module (1) is in signal connection with the bufferless analog switch array module (2), and the bufferless analog switch array module (2) is in signal connection with a plurality of tested equipment (3);

the bus module (1) is used for connecting the microcontroller and peripheral equipment thereof to realize half-duplex communication;

the bufferless analog switch array module (2) is provided with an X-type connecting module and a Y-type connecting module, the X-type connecting module is used for connecting networks of at least 12 paths of tested equipment (3), and the Y-type connecting module is used for connecting networks of at least 8 paths of tested equipment (3).

2. A switch control circuit according to claim 1, wherein: the buffer-free analog switch array module (2) comprises an interface chip with the model of ADG2128BCPZ, the X-type connection module and the Y-type connection module are both arranged on the interface chip, the X-type connection module comprises 12 paths of interfaces of X0-X11, the Y-type connection module comprises 8 paths of interfaces of Y0-Y7, and the 12 paths of interfaces of X0-X11 and the 8 paths of interface arrays of Y0-Y7 form 96 switch channels.

3. A switch control circuit according to claim 2, wherein: the Y-type connection module is also used for pulling up the network of the tested device (3) to the level 1V2, 1V8 or 3V3 and pulling down the network to the ground.

4. A switch control circuit according to claim 2, wherein: the bus module (1) is an I2C bus.

5. The switch control circuit of claim 4, wherein: the bus module (1) comprises a bidirectional data line SDA and a clock line SCL, an SDA terminal and an SCL terminal are arranged on the interface chip, and the bidirectional data line SDA and the clock line SCL are respectively connected with the SDA terminal and the SCL terminal.