CN107844672B - Clock tree unit, clock network structure and FPGA clock structure - Google Patents
Clock tree unit, clock network structure and FPGA clock structure Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a clock tree unit, a clock network structure and an FPGA clock structure, wherein the clock tree unit comprises: the device comprises a transverse driving module, a plurality of longitudinal interface modules and a plurality of programmable logic units, wherein transverse branch driving is arranged in the programmable logic units; a lateral drive module electrically connected to a plurality of said longitudinal interface modules; the longitudinal interface module is correspondingly connected with the transverse branch driver; the lateral branch drives are used for enabling the signals to be transmitted to pass between a plurality of the programmable logic units. According to the technical scheme, the transverse branch driving is arranged in the programmable logic unit, so that signals to be transmitted, which are received by the programmable logic unit from the longitudinal interface module, can be mutually transmitted, and the second driving is different from the second driving in the prior art, so that all signals to be transmitted are sent to the programmable logic unit, the chip area is reduced, and the resource waste is avoided.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a clock tree unit, a clock network structure and an FPGA clock structure.
Background
FPGAs are logic devices composed of a number of logic units, including gates, look-up tables, and flip-flops, which have rich hardware resources, powerful parallel processing capabilities, and flexible reconfigurable capabilities, and are increasingly being used in many fields such as data processing, communications, networking, and the like.
With the rapid development of the process manufacturing level, the chip size is continuously reduced, and the integration level is rapidly improved. In order to keep pace with the rapid development of digital chips, the requirements put forward on performance are also increasing, while clock signals play a decisive role in the function, performance and stability of the system. The design of the clock network is thus a key factor in determining how good the clock network is in the design process.
The existing clock network structure as shown in fig. 1 mainly includes:
a: central clock selector (MUX): the clock source is used for transmitting clock signals, and a required clock source is selected by configuring the FPGA; the number of output clocks of the central clock selector is fixed, i.e. the maximum number N of clocks that can be transferred across the clock network.
b: first drive (a-buffer): n clock signals (Nclk) output by the MUX are transmitted to the A-buffer, and the second driving (B-buffer) module is driven by the A-buffer.
c: second drive (B-buffer): and receiving Nclk transmitted by the A-buffer, and driving the clock module of a programmable logic unit (basic unit) of the corresponding area by the Nclk.
However, the above prior art has the following problems: 1. the number of clocks which can be transferred is fixed, if the number of clocks is increased, the scale of a clock network is increased, the size of a chip is increased, the cost is increased, and when the clock is applied in a small scale, part of clock network resources are idle, so that the resource waste is caused. 2. The existing clock structure can only be used for transmitting clock signals, but can not be used for transmitting custom signals which are required to be transmitted at high speed for users.
In high-speed digital processors, most of the power consumption is consumed in the clock network, and thus the design of the clock network is particularly attractive. Therefore, it is a hot research direction in the art to develop a clock network structure that is advantageous for chip area reduction and capable of reducing power consumption.
Disclosure of Invention
Aiming at the problems, the invention provides a clock tree unit, a clock network structure and an FPGA clock structure, and the specific implementation modes are as follows.
Specifically, an embodiment of the present invention provides a clock tree unit, where the clock tree unit includes: the device comprises a transverse driving module, a plurality of longitudinal interface modules and a plurality of programmable logic units, wherein transverse branch driving is arranged in the programmable logic units;
the transverse driving module is electrically connected to the plurality of longitudinal interface modules and is used for sending signals to be transmitted to the longitudinal interface modules;
the longitudinal interface module is correspondingly connected with the transverse branch driver and is used for sending the signal to be transmitted to the transverse branch driver;
the lateral branch drives are used for enabling the signals to be transmitted to pass between a plurality of the programmable logic units.
In one embodiment of the present invention, the output end of the transverse driving module is provided with a plurality of output leads, and each output lead transmits one signal to be transmitted;
each of the longitudinal interface modules is electrically connected with at least one of the plurality of output leads and is used for receiving the signals to be transmitted, which are transmitted by the output leads.
In one embodiment of the invention, the longitudinal interface modules are provided with the transverse branch drives, and a plurality of the longitudinal interface modules are electrically connected through the transverse branch drives, and the transverse branch drives are used for transmitting the signals to be transmitted among the longitudinal interface modules.
In one embodiment of the present invention, the lateral driving module is provided with N output leads, each of the longitudinal interface modules is electrically connected to H output leads, and M longitudinal interface modules are a group, where n=h×m, and N, H, M is a positive integer greater than or equal to 1;
each group of the longitudinal interface modules mutually transmit the signals to be transmitted so that each longitudinal interface module receives N signals to be transmitted;
and M programmable logic units correspondingly connected with the M longitudinal interface modules are in a group, and the M programmable logic units are in driving connection through the transverse branches so that each programmable logic unit receives N signals to be transmitted.
Another embodiment of the present invention provides a clock network structure, including a clock tree unit according to any one of the preceding embodiments, where,
the clock network further comprises a signal selector, wherein the signal selector is electrically connected to the transverse driving module and is used for sending a signal to be transmitted to the transverse driving module;
the signal selector is provided with a selection signal end, and the selection signal end is used for inputting a first selection signal; the signal selector selects an input signal to be transmitted according to the first selection signal, wherein the signal to be transmitted comprises a clock signal and a global configuration signal.
In one embodiment of the present invention, the lateral driving module is further provided with a second selection signal terminal for inputting a second selection signal; and the transverse driving module receives an external signal according to the second selection signal and transmits the external signal to the longitudinal interface module.
Another embodiment of the present invention provides an FPGA clock architecture, including the clock network architecture described in any one of the foregoing embodiments.
The beneficial effects of the invention are as follows:
1. the technical scheme of the invention constructs the longitudinal interface drive by multiplexing the longitudinal interfaces, which is used for driving the programmable logic unit, reduces special drive setting and reduces the product cost; and the transverse branch driving is arranged in the programmable logic unit, so that signals to be transmitted, which are received by the programmable logic unit from the longitudinal interface module, can be mutually transmitted, and the second driving is different from the second driving in the prior art, which sends all signals to be transmitted to the programmable logic unit, thereby reducing the chip area and avoiding the resource waste.
2. According to the embodiment of the invention, the selection signal terminal is additionally arranged on the signal selector, so that the clock network structure provided by the embodiment of the invention not only can transmit clock signals, but also can transmit global configuration signals, the time for configuring the global FPGA is shortened, the time deviation is smaller, and the high-speed application of the system is facilitated.
3. According to the embodiment of the invention, the second selection signal end is additionally arranged on the transverse driving module, so that the transverse driving module not only has the function of receiving the signals transmitted by the signal selector, but also has the function of receiving external signals, the purpose that a user transmits the self-defined signals required to be transmitted at high speed to the longitudinal interface module can be realized, more path selections are provided for the user to transmit the required high-speed signals, and the working efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art clock network architecture;
FIG. 2 is a schematic diagram of a clock tree unit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a clock network structure according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a clock network structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a signal selector according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a lateral driving module according to an embodiment of the present invention.
Reference numerals illustrate:
longitudinal interface module: 200;
programmable logic unit: 100.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings.
Example 1
Fig. 2 is a schematic structural diagram of a clock tree unit according to an embodiment of the present invention; wherein the clock tree unit comprises: the device comprises a transverse driving module, a plurality of longitudinal interface modules and a plurality of programmable logic units, wherein transverse branch driving is arranged in the programmable logic units;
the transverse driving module is electrically connected to the plurality of longitudinal interface modules and is used for sending signals to be transmitted to the longitudinal interface modules;
the longitudinal interface module is correspondingly connected with the transverse branch driver and is used for sending the signal to be transmitted to the transverse branch driver;
the lateral branch drives are used for enabling the signals to be transmitted to pass between a plurality of the programmable logic units.
The lateral driving module is simultaneously connected with the plurality of longitudinal interface modules 200, and then, each longitudinal interface module 200 is correspondingly and electrically connected with the plurality of programmable logic units 100, specifically, the longitudinal interface modules 200 are electrically connected with the lateral branch driving inside the programmable logic units 100, and the lateral branch driving is electrically connected with the plurality of programmable logic units 100 according to a certain algorithm rule, so that the programmable logic units 100 with a connection relationship can perform mutual transmission of signals to be transmitted. In this way, in the process of transmitting the signal to be transmitted, the transverse driving module only needs to transmit part of the signal to be transmitted to each longitudinal interface module 200, and then transmits the signal to be transmitted received by the programmable logic unit 100 to other programmable logic units 100 having a connection relationship with the same through transverse branch driving, so that each programmable logic unit 100 finally receives all the signals to be transmitted, and therefore, the technical problems that in the prior art, all the signals to be transmitted need to be transmitted by both the first driving and the second driving at one time, so that a large number of transmission lines and a large clock network structure area are caused are solved.
In addition, the vertical interface module 200 in the embodiment of the present invention is a plurality of vertical interfaces, and by electrically connecting the vertical interfaces with the horizontal driving module and the programmable logic unit 100 and configuring the vertical interfaces in combination with the FPGA, the vertical interfaces have a function of driving vertically, so in the embodiment of the present invention, no additional driving is required, and the functions of driving the horizontal branch driving and the clock module in the programmable logic unit 100 are realized by using the existing interfaces through resource configuration, and the required functions are realized by using the existing components, without increasing the structural volume, and reducing the cost.
Example two
As can be seen in connection with fig. 2, the output end of the lateral driving module is provided with a plurality of output leads, each of which transmits one of the signals to be transmitted;
each of the longitudinal interface modules 200 is electrically connected to at least one of the plurality of output leads, and is configured to receive the signal to be transmitted delivered by the output lead.
Specifically, the transverse driving module is connected with each longitudinal interface module 200 through a plurality of output leads, each output lead outputs a different signal to be transmitted, and the longitudinal interface module 200 is connected with one or a plurality of output leads, so that the longitudinal interface module 200 receives the signal to be transmitted sent by the one or the plurality of output leads; the longitudinal interface then passes the signals to be transmitted received from the lateral drive modules to the programmable logic units 100 to which it is correspondingly connected.
It should be noted that the lateral branch driver is electrically connected to the plurality of programmable units according to a certain algorithm rule, so as to ensure that the total number of signals to be transmitted, which are finally received by each of the programmable logic units 100 from the vertical interface module 200 and from other programmable logic units 100 having an electrical connection relationship with the vertical interface module, is the same as the total number of signals to be transmitted, which are output by the output end of the lateral driving module. Therefore, when the output leads of the lateral driving modules connected to the longitudinal interface module 200 are different, for example, when the longitudinal interface module 200 is connected to one output lead or two output leads are connected, the algorithm rule of the lateral branch driving is correspondingly adapted and changed, which specifically includes: the number of the plurality of connected programmable logic units 100, the signal transmission mode, etc. change the principle to finally realize that each programmable logic unit 100 receives all signals to be transmitted.
For example, assuming that the lateral driving module has 8 output leads, and transfers 8 signals, then each of the longitudinal interface modules 200 is connected to only one output lead, the first longitudinal interface module 200 is connected to the first output lead to receive the first signal, and then the first longitudinal interface module 200 sends the first signal to the first lateral branch driver in the first programmable logic unit 100, where the connection relationship of the first lateral branch driver to electrically connect the plurality of programmable logic units 100 may specifically be: the left and the right are respectively connected with 3 programmable logic units 100 in turn, and the left and the right are respectively connected with 4 programmable logic units 100 in turn; the signal transmission mode is as follows: and the first signals are respectively and sequentially sent to 7 programmable logic units 100 with a connection relationship to the left and the right, and meanwhile, the first programmable logic unit 100 receives signals sent by other transverse driving branches, so that all signals to be transmitted are received in the first programmable logic unit 100, and a clock module in the programmable logic unit 100 can complete corresponding functions. The detailed algorithm rule is used in a plurality of optional modes, and any connection mode capable of enabling the programmable logic unit 100 to obtain all signals to be transmitted through mutual signal transmission and reception is within the protection scope of the technical scheme of the present invention, and is not described in detail herein.
Further, each of the longitudinal interface modules 200 is electrically connected to at least one of the plurality of output leads, specifically, since the more the connection lines between each of the longitudinal interface modules 200 and the lateral driving module are electrically connected, the larger the chip size is, which is not beneficial to saving area, and if each of the longitudinal interface modules 200 and the lateral driving module has a plurality of connection lines, when the number of clock signals transmitted is small, the idle connection lines will occur, resulting in resource waste; if each of the longitudinal interface modules 200 is connected to only one signal output lead of the lateral driving module, when the transmitted signals are more, a corresponding plurality of longitudinal interface modules 200 are needed, and the chip volume is increased, so that the specific number of the connection between the longitudinal interface modules 200 and the plurality of output leads of the lateral driving module needs to be determined by comprehensively considering the total number of the signals, the number of the longitudinal interface modules 200 and the chip volume.
Since each of the programmable logic units 100 needs all signals to be transmitted to facilitate its specific function, and correspondingly, each of the longitudinal interface modules 200 also needs all signals to be transmitted to support its specific function, in the embodiment of the present invention, the transverse branch driver is also provided in the longitudinal interface modules 200, and likewise, the transverse branch driver electrically connects the plurality of longitudinal interface modules 200 according to a certain algorithm rule, and then the transverse branch driver transfers the signals to be transmitted received from the transverse driving module to the other longitudinal interface modules 200 having a connection relationship, and the specific connection structure and the signal transmission process to be transmitted may refer to the signal transmission process to be transmitted in the programmable logic unit 100, so that each of the longitudinal interface modules 200 can receive all signals to be transmitted.
Further, the detailed transmission process of the signal to be transmitted in the embodiment of the present invention is as follows:
the transverse driving module is provided with N output leads, each of the longitudinal interface modules 200 is electrically connected with H output leads, and M longitudinal interface modules 200 are a group, where n=h×m, and N, H, M is a positive integer greater than or equal to 1;
each group of the longitudinal interface modules 200 mutually transmits the signals to be transmitted, so that each longitudinal interface module 200 receives N signals to be transmitted;
the M programmable logic units 100 correspondingly connected to the M vertical interface modules 200 are a group, and the M programmable logic units 100 are connected through the horizontal branch driving, so that each programmable logic unit 100 receives N signals.
In the embodiment of the present invention, assuming that each lateral driving module outputs 9 signals and has 9 output leads, preferably, each longitudinal interface module 200 is connected to three output leads, and specifically, the lateral driving modules divide the 9 signals into 3 groups, specifically: the hs <8:0> signal is split into hs0, hs3 and hs6; hs1, hs4 and hs7; hs2, hs5 and hs8, the actual grouping is not limited to the form given in this embodiment. Each longitudinal interface module 200 connects three output leads and receives a corresponding set of signals. At this time, the connection relationship of the first lateral branch driving to electrically connect the remaining two programmable logic units 100 may specifically be: the first lateral branch is driven to electrically connect the second programmable logic unit 100 to the left side and the third programmable logic unit 100 to the right side; the signal transmission mode is as follows: the first lateral branch driver sends a first set of signals to the second and third programmable logic units 100 to the left and right, respectively, and the corresponding second and third programmable logic units 100 also send a second set and third set of signals to the first programmable logic unit 100 through respective internally disposed second and third lateral branch drivers, thus enabling the first programmable logic unit 100 to receive the three sets of signals to perform the corresponding functions.
It should be noted that, each of the lateral branch drives connects a plurality of programmable logic units 100, and the connection manner is not limited to the embodiments of the present invention, and any connection manner capable of implementing signaling is acceptable.
Example III
Another embodiment of the present invention further provides a clock network structure, as shown in fig. 3-6, and fig. 3 is a schematic structural diagram of the clock network structure provided in the embodiment of the present invention; fig. 4 is a schematic diagram of a clock network structure according to an embodiment of the present invention; FIG. 5 is a schematic diagram of a signal selector according to an embodiment of the present invention; fig. 6 is a schematic structural diagram of a lateral driving module according to an embodiment of the present invention. The clock network structure comprises a clock tree unit according to any of the above embodiments, wherein,
the clock network further comprises a signal selector, wherein the signal selector is electrically connected to the transverse driving module and is used for sending a signal to be transmitted to the transverse driving module;
the signal selector is provided with a selection signal end, and the selection signal end is used for inputting a first selection signal; the signal selector selects an input signal to be transmitted according to the first selection signal, wherein the signal to be transmitted comprises a clock signal and a global configuration signal.
Specifically, as shown in fig. 3, the signal selector is configured to send a signal to be transmitted to the whole clock network structure, and an output end of the signal selector is electrically connected to the transverse driving module; the lateral driving modules respectively drive the longitudinal interface modules to the left and right, the longitudinal interface modules on the left side are in a first group, the longitudinal interface modules on the right side are in a second group, and each longitudinal interface module 200 is respectively connected with a plurality of programmable logic units 100 upwards and downwards. Three lateral drive modules are schematically shown in fig. 3, together with six sets of longitudinal interface modules corresponding thereto.
It should be noted that, as shown in fig. 4, the number of the lateral driving modules, the longitudinal interface modules and the programmable logic units is not limited in the present technical solution, in fig. 4A, B, C is a positive integer greater than 0, and C is less than or equal to B, and B is less than or equal to a; the number of the transverse driving modules is the same as the connection relation between the longitudinal interface module groups connected leftwards and rightwards, and the clock network structure provided by the embodiment of the invention is not substantially influenced by the number of the transverse driving modules. Correspondingly, the number of the programmable logic units 100 connected to the longitudinal interface module 200 is changed without affecting the signal transmission manner between the two, and the specific transmission manner is shown in the first embodiment and the second embodiment, and further, the plurality of lateral driving modules, the plurality of longitudinal interface modules and the plurality of programmable logic units in fig. 4 are respectively indicated by ellipses of corresponding positions.
Further, in the embodiment of the present invention, as shown in fig. 5, the signal selector has two input sources, one of which inputs a clock signal and the other of which inputs a global configuration signal, and in the embodiment of the present invention, the selection signal terminal is provided in the signal selector to control the input source type of the signal selector, and in general, the input signal at the selection signal terminal defaults to a low level, the input source of the signal selector defaults to a clock signal, and when the input signal received by the selection signal terminal is at a high level, the input source of the signal selector is converted to the global configuration signal.
The existing transmission path for configuring the FPGA global configuration signal needs longer time and has larger transmission time deviation, but in the embodiment of the invention, the global configuration signal is transmitted through a clock network structure, so that on one hand, the clock network is utilized to not transmit clock signal time gaps, thereby avoiding resource waste and greatly saving the transmission time of the global configuration signal; on the other hand, the characteristic of small time deviation when the clock network transmits signals is utilized, and the high-speed application of the FPGA is facilitated.
Further, as shown in fig. 6, in the clock network structure provided by the embodiment of the present invention, the lateral driving module is further provided with a second selection signal end, where the second selection signal end is used for inputting a second selection signal; the lateral driving module receives an external signal according to the second selection signal and transmits the external signal to the longitudinal interface module 200.
Specifically, in general, the second selection signal received by the second selection signal terminal is at a low level, and the working mode of the transverse driving module is mode 1: receiving the clock signal and transmitting the clock signal to the longitudinal interface module 200; when the user-defined signal needs to be transmitted at a high speed, the second selection signal received by the second selection signal is at a high level, and the working mode of the transverse driving module is converted into a mode 2: the external signal is received and transmitted to the longitudinal interface module 200, and the external signal may be a clock signal or any other signal configured by user definition, which is not limited in this embodiment.
For example, referring to fig. 3 and fig. 6, in the transmission path of the signal in the mode 1, the signal selector sends 9 signals to the lateral driving module, and then the lateral driving module sends the 9 signals to the left and right to different longitudinal interface modules 200 respectively, and the specific sending manner is shown in the first embodiment and the second embodiment; the longitudinal interface module 200 then sends the signal to be transmitted up and down to the editable logic unit, respectively.
When the second selection signal received by the second selection signal receiver is at a high level, the working mode of the lateral driving module is adjusted to be mode 2, specifically, the lateral driving module stops sending the clock signal from the signal selector to the longitudinal interface module 200, meanwhile, the user-defined signal to be quickly transmitted, that is, the external signal is transmitted to the left longitudinal interface module 200 as shown in fig. 3 through the FPGA to be input, the longitudinal interface module 200 sends the user-defined signal to the lateral driving module, and the lateral driving module sends the user-defined signal to the right longitudinal interface module 200, and then the longitudinal interface module 200 sends the signal to the programmable logic unit 100 to complete the high-speed signal transmission. In the embodiment of the present invention, the transmission from the right longitudinal interface module 200 to the left longitudinal interface module 200 may also be implemented. The embodiment provides more path selection for the user to transmit the signals, and improves the working efficiency.
The invention also provides an FPGA clock structure comprising the clock network structure according to any one of the above embodiments. The clock network structure is based on the configurability of the FPGA, so that not only can the expansion of a high-performance clock be realized, but also the unbiased transmission of global configuration information can be realized, and the transverse driving modules with different modes can be configured, so that the user-defined signals can be transmitted more through multiplexing longitudinal interfaces.
In summary, specific examples are applied to describe the implementation manners of a clock tree unit, a clock network structure and an FPGA clock structure provided in the embodiments of the present invention, where the descriptions of the above embodiments are only used to help understand the scheme and core ideas of the present invention; meanwhile, as for those skilled in the art, there are variations in the specific embodiments and the application scope according to the idea of the present invention, and in summary, the present disclosure should not be construed as limiting the present invention, and the scope of the present invention should be defined by the appended claims.
Claims (4)
1. A clock tree unit, the clock tree unit comprising: the device comprises a transverse driving module, a plurality of longitudinal interface modules and a plurality of programmable logic units, wherein transverse branch driving is arranged in the programmable logic units;
the transverse driving module is electrically connected to the plurality of longitudinal interface modules and is used for sending signals to be transmitted to the longitudinal interface modules;
the longitudinal interface module is correspondingly connected with the transverse branch driver and is used for sending the signal to be transmitted to the transverse branch driver;
the lateral branch driving is used for enabling the signals to be transmitted among a plurality of the programmable logic units;
the output end of the transverse driving module is provided with a plurality of output leads, and each output lead transmits one signal to be transmitted;
each of the longitudinal interface modules is electrically connected with at least one of the plurality of output leads and is used for receiving the signals to be transmitted, which are transmitted by the output leads;
the longitudinal interface modules are provided with transverse branch drives, a plurality of the longitudinal interface modules are electrically connected through the transverse branch drives, and the transverse branch drives are used for enabling the signals to be transmitted among the longitudinal interface modules;
the transverse driving module is provided with N output leads, each longitudinal interface module is electrically connected with H output leads, M longitudinal interface modules are in a group, wherein N=H×M, and N, H, M is a positive integer greater than or equal to 1;
each group of the longitudinal interface modules mutually transmit the signals to be transmitted so that each longitudinal interface module receives N signals to be transmitted;
and M programmable logic units correspondingly connected with the M longitudinal interface modules are in a group, and the M programmable logic units are in driving connection through the transverse branches so that each programmable logic unit receives N signals to be transmitted.
2. A clock network structure comprising the clock tree unit of claim 1, wherein,
the clock network further comprises a signal selector, wherein the signal selector is electrically connected to the transverse driving module and is used for sending a signal to be transmitted to the transverse driving module;
the signal selector is provided with a selection signal end, and the selection signal end is used for inputting a first selection signal; the signal selector selects an input signal to be transmitted according to the first selection signal, wherein the signal to be transmitted comprises a clock signal and a global configuration signal.
3. The clock network structure of claim 2, wherein the lateral drive module is further provided with a second selection signal terminal for inputting a second selection signal; and the transverse driving module receives an external signal according to the second selection signal and transmits the external signal to the longitudinal interface module.
4. An FPGA clock architecture comprising the clock network architecture of any one of claims 2-3.
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| US6825690B1 (en) * | 2003-05-28 | 2004-11-30 | Actel Corporation | Clock tree network in a field programmable gate array |
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| US6825690B1 (en) * | 2003-05-28 | 2004-11-30 | Actel Corporation | Clock tree network in a field programmable gate array |
| CN1894913A (en) * | 2003-10-24 | 2007-01-10 | 艾梅尔公司 | Method and apparatus for a variable processing period in an integrated circuit |
| CN107342764A (en) * | 2015-01-23 | 2017-11-10 | 西安智多晶微电子有限公司 | Cpld |
| CN106992770A (en) * | 2016-01-21 | 2017-07-28 | 华为技术有限公司 | Clock circuit and its method for transmitting clock signal |
| CN105912811A (en) * | 2016-05-03 | 2016-08-31 | 山东大学 | Simulation method for analog and digital hybrid circuit |
| CN106933181A (en) * | 2017-04-27 | 2017-07-07 | 沈阳飞机工业（集团）有限公司 | A kind of put-put attaching/detaching apparatus electric control system |
| CN207571741U (en) * | 2017-12-06 | 2018-07-03 | 西安智多晶微电子有限公司 | Clock Tree unit, clock network structure and FPGA timing topologies |
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