CN107844672A - Clock Tree unit, clock network structure and FPGA timing topologys - Google Patents
Clock Tree unit, clock network structure and FPGA timing topologys Download PDFInfo
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- CN107844672A CN107844672A CN201711274987.6A CN201711274987A CN107844672A CN 107844672 A CN107844672 A CN 107844672A CN 201711274987 A CN201711274987 A CN 201711274987A CN 107844672 A CN107844672 A CN 107844672A
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention relates to a kind of Clock Tree unit, clock network structure and FPGA timing topologys, wherein the Clock Tree unit includes：Laterally driven module, multiple longitudinal interface modules, multiple programmable logic cells, transverse branch driving is provided with the programmable logic cells；Laterally driven module, it is electrically connected to multiple longitudinal interface modules；The longitudinal interface module, connection corresponding with transverse branch driving；The transverse branch is driven for making the signal to be transmitted be transmitted between multiple programmable logic cells.Technical solution of the present invention in programmable logic cells by setting transverse branch to drive, the signal to be transmitted that programmable logic cells are received from longitudinal interface module mutually transmits, and driven different from of the prior art second and whole signals to be transmitted is sent to programmable logic cells, therefore chip area is reduced, and avoids the wasting of resources.
Description
Technical field
The invention belongs to electronic technology field, and in particular to a kind of Clock Tree unit, clock network structure and FPGA clocks
Structure.
Background technology
FPGA is the logical device being made up of the logic unit of many, and wherein logic unit includes door, look-up table and triggering
Device, it has abundant hardware resource, powerful parallel processing capability and flexible reconfigurable ability, in data processing, communication, network
Increasing extensive use has been obtained etc. many fields.
With the rapid development of technological and manufacturing level, chip size is constantly reducing, and integrated level is quickly improving.To keep up with
The fast development of digit chip, people are to performance requirement also more and more higher, and function, performance of the clock signal to system
And stability plays conclusive effect.Therefore in the design process, clock network has been designed to decision clock network quality
Key factor.
Existing clock network structure as shown in Figure 1 mainly includes：
a：Central clock selector (MUX)：For transmitting clock signal, required clock is selected by configuring FPGA
Source；The output clock number of central clock selector is fixed, namely whole clock network can transmit the maximum number of clock
Mesh is N number of.
b：First driving (A-buffer)：N number of clock signal (Nclk) of MUX outputs is delivered to A-buffer, passes through A-
Buffer drivings the second driving (B-buffer) module.
c：Second driving (B-buffer)：The Nclk that A-buffer is transmitted is received, and the Nclk is driven into respective regions
The clock module of programmable logic cells (basic unit).
But there are the following problems for above-mentioned prior art：1st, the clock number that can be transmitted is fixed, if to increase
Clock number, then to increase the scale of clock network, increase chip volume, improve cost, and in small-scale application, part
Clock network resource can be idle, causes the wasting of resources.2nd, existing timing topology, be only used for transmit clock signal, and for
User needs the self-defined signal of high-speed transfer to transmit.
In high speed numerical processor, most power consumption consumption is in clock network, therefore the design of clock network is outstanding
To cause the concern of people.Therefore, work out one kind to be advantageous to reduce chip area, and the clock network knot of power consumption can be reduced
Structure, it is the hot research direction of this area.
The content of the invention
For the problem present on, the present invention proposes a kind of Clock Tree unit, clock network structure and FPGA clocks
Structure, specific embodiment are as follows.
Specifically, the embodiment of the present invention provides a kind of Clock Tree unit, wherein, the Clock Tree unit includes：Laterally drive
Dynamic model block, multiple longitudinal interface modules, multiple programmable logic cells, transverse branch is provided with the programmable logic cells
Driving；
Laterally driven module, multiple longitudinal interface modules are electrically connected to, for being sent to the longitudinal interface module
Signal to be transmitted；
The longitudinal interface module, connection corresponding with transverse branch driving, sends out for being driven to the transverse branch
Send the signal to be transmitted；
The transverse branch is driven for making the signal to be transmitted be transmitted between multiple programmable logic cells.
In one embodiment of the invention, the output end of the laterally driven module is provided with multiple output leads, often
One output lead transmits a signal to be transmitted；
Each described longitudinal interface module electrically connects with least one in multiple output leads, for receiving
State the signal to be transmitted of output lead transmission.
In one embodiment of the invention, the transverse branch driving is provided with the longitudinal interface module, it is multiple
The longitudinal interface module is driven by the transverse branch and electrically connected, and the transverse branch is driven for making the letter to be transmitted
Number transmitted between multiple longitudinal interface modules.
In one embodiment of the invention, the laterally driven module is provided with N number of output lead, and each is described vertical
To H output leads of interface module electrical connection, the M longitudinal interface modules are one group, and wherein N=H*M, N, H, M are
Positive integer more than or equal to 1；
Longitudinal interface module described in every group mutually transmits the signal to be transmitted, so that each longitudinal interface module connects
Receive N number of signal to be transmitted；
The individual programmable logic cells of M of connection corresponding with M described longitudinal interface modules are one group, the M institute
Programmable logic cells are stated by the transverse branch drive connection so that each programmable logic cells receive it is N number of
The signal to be transmitted.
Another embodiment of the present invention provides a kind of clock network structure, wherein, including described in any of the above-described embodiment
Clock Tree unit, wherein,
The clock network also includes signal selector, and the signal selector is electrically connected to laterally driven module, is used for
Signal to be transmitted is sent to the laterally driven module；
The signal selector is provided with selection signal end, and the selection signal end is used to input first choice signal；Institute
The signal to be transmitted that signal selector inputs according to the first choice signal behavior is stated, the signal to be transmitted is believed including clock
Number and global configuration signal.
In one embodiment of the invention, the laterally driven module is additionally provided with the second selection signal end, and described
Two selection signal ends are used to input the second selection signal；The laterally driven module receives outer according to second selection signal
Portion's signal, and it is transferred to the longitudinal interface module.
Another embodiment of the present invention provides a kind of FPGA timing topologys, wherein, including described in any of the above-described embodiment
Clock network structure.
Beneficial effects of the present invention are：
1st, technical solution of the present invention forms longitudinal interface driving, can compiled to drive by being multiplexed to longitudinal interface
Journey logic unit, reduce special driving and set, reduce product cost；And by being set in programmable logic cells
Transverse branch drives so that and the signal to be transmitted that programmable logic cells receive from longitudinal interface module can be transmitted mutually,
And driven different from of the prior art second and whole signals to be transmitted is sent to programmable logic cells, therefore reduce core
Piece area, and avoid the wasting of resources.
2nd, the embodiment of the present invention on signal selector by setting up selection signal end so that provided in an embodiment of the present invention
Clock network structure can not only transmit clock signal, can also transmit global configuration signal, shorten the global FPGA's of configuration
Time, and time deviation is smaller, is advantageous to system high-speed application.
3rd, the embodiment of the present invention in laterally driven module by setting up the second selection signal end so that laterally driven module is not
But the signal with reception signal selector transmission, and with the function of receiving external signal, user can be realized needs
The self-defined signal of high-speed transfer is transferred to the purpose of longitudinal interface module, is provided more for high speed signal needed for user's transmission
Path selection, improve operating efficiency.
Brief description of the drawings
Fig. 1 is the structural representation of existing clock network structure；
Fig. 2 is the structural representation of Clock Tree unit provided in an embodiment of the present invention；
Fig. 3 is the structural representation one of clock network structure provided in an embodiment of the present invention；
Fig. 4 is the structural representation two of clock network structure provided in an embodiment of the present invention；
Fig. 5 is the structural representation of signal selector provided in an embodiment of the present invention；
Fig. 6 is the structural representation of laterally driven module provided in an embodiment of the present invention.
Description of reference numerals：
Longitudinal interface module：200；
Programmable logic cells：100.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Embodiment one
As shown in Fig. 2 Fig. 2 is the structural representation of Clock Tree unit provided in an embodiment of the present invention；Wherein, the clock
Tree unit includes：Laterally driven module, multiple longitudinal interface modules, multiple programmable logic cells, the FPGA list
Transverse branch driving is provided with member；
Laterally driven module, multiple longitudinal interface modules are electrically connected to, for being sent to the longitudinal interface module
Signal to be transmitted；
The longitudinal interface module, connection corresponding with transverse branch driving, sends out for being driven to the transverse branch
Send the signal to be transmitted；
The transverse branch is driven for making the signal to be transmitted be transmitted between multiple programmable logic cells.
Laterally driven module connects multiple longitudinal interface modules 200 simultaneously, and then, each longitudinal interface module 200 is right
Multiple programmable logic cells 100 should be electrically connected, specifically, longitudinal interface module 200 is electrically connected to programmable logic cells 100
Internal transverse branch driving, transverse branch driving electrically connect multiple programmable logic cells 100 according to certain algorithm rule, made
Must be with the mutual transmission that signal to be transmitted can be carried out between the programmable logic cells 100 of annexation.So to be passed
During defeated signal transmits, laterally driven module is only needed to each transmitting portions of longitudinal interface module 200 letter to be transmitted
Number, the signal to be transmitted for then being received programmable logic cells 100 by transverse branch driving passes to other to be had therewith
Have in the programmable logic cells 100 of annexation so that each programmable logic cells 100 eventually receives whole treat
Transmission signal, therefore solve in the prior art, the first driving and the second driving are both needed to the whole letter to be transmitted of disposable transmission
Number, cause transmission line more, the big technical problem of clock network structural area.
In addition, the longitudinal interface module 200 in the embodiment of the present invention, it is substantially multiple longitudinal interfaces, by inciting somebody to action longitudinal direction
Interface and laterally driven module and programmable logic cells 100 electrically connect, and are configured with reference to FPGA so that longitudinal interface
Function with zigzag tread patterns, therefore in the embodiment of the present invention, it is not necessary to increase extra driving, but led to using existing interface
Cross resource distribution and realize the transverse branch driving in driving programmable logic cells 100 and the function of clock module, using existing
Part realizes required function, and does not increase structural volume, reduces cost.
Embodiment two
Visible with reference to Fig. 2, the output end of the laterally driven module is provided with multiple output leads, each described output
Lead transmits a signal to be transmitted；
Each described longitudinal interface module 200 electrically connects with least one in multiple output leads, for connecing
Receive the signal to be transmitted of the output lead transmission.
Specifically, laterally driven module is connected by multiple output leads with each longitudinal interface module 200, each
Output lead exports a different signal to be transmitted, and longitudinal interface module 200 connects a certain bar therein or a few defeated
Go out lead, then the longitudinal interface module 200 is the signal to be transmitted for receiving this or this several output lead transmissions；Then
The longitudinal interface passes to the signal to be transmitted received from laterally driven module the FPGA list for corresponding to connection therewith
In member 100.
It should be noted that transverse branch driving is electrically connected to multiple programmable units according to certain algorithm rule, its
Purpose is to ensure each programmable logic cells 100 finally from longitudinal interface module 200 and from other therewith with electricity
The total number of the signal to be transmitted received in the programmable logic cells 100 of annexation and the output end of laterally driven module
The total number of the signal to be transmitted of output is identical.Therefore, when the output for the laterally driven module that longitudinal interface module 200 connects is drawn
The mode of line is different, such as during two output leads of one output lead of connection of longitudinal interface module 200 or connection, it is corresponding
, the algorithm rule of transverse branch driving adaptively will be adjusted and change, and specifically include：The multiple of connection compile
The number of journey logic unit 100, signalling formula etc., it changes principle finally to realize each programmable logic cells
100, which receive whole signals to be transmitted, is defined.
For example, it is assumed that laterally driven module has 8 output leads, transmits 8 signals, then, each longitudinal direction
Interface module 200 is only connected with an output lead, and first longitudinal direction interface module 200 connects the first output lead and receives the first letter
Number, then the first signal is sent to the first transverse direction point in the first programmable logic cells 100 by first longitudinal direction interface module 200
Branch drives, and now, the first transverse branch driving annexation for electrically connecting multiple programmable logic cells 100 specifically can be with
It is：It is sequentially connected 3 programmable logic cells 100 to the left respectively, is sequentially connected 4 programmable logic cells 100 to the right；Signal
Sending method is：First signal is sent to 7 programmable logic cells with annexation successively to the left and to the right respectively
100, meanwhile, the first programmable logic cells 100 receive the signal that other laterally driven branches send, and such first can compile
The signal to be transmitted of whole is received by journey logic unit 100, to cause the clock module in programmable logic cells 100
Complete corresponding function.Detailed algorithm rule is used for a variety of optional modes, any that programmable logic cells 100 can be made logical
Cross mutual signal to send and receive, realize the connected mode for obtaining whole signals to be transmitted in technical solution of the present invention
Protection domain in, do not repeat one by one herein.
Further, each described longitudinal interface module 200 is electrically connected with least one in multiple output leads
Connect, specifically, because the connecting line that each longitudinal interface module 200 electrically connects with laterally driven module is more, then can cause
Chip volume increases, and is unfavorable for saving area, and if each longitudinal interface module 200 and laterally driven module have it is more
Individual connecting line, then when the clock signal of transmission is less, the connecting line free time just occurs, causes the wasting of resources；It is and if each
Individual longitudinal interface module 200 is only connected with a signal output lead of laterally driven module, then when the signal of transmission is more
When, then more multiple longitudinal interface modules 200 are correspondingly needed, also result in chip volume increase, therefore, longitudinal interface module
200 with the specific connection numbers of multiple output leads of laterally driven module, it is necessary to consider the total number of signal, longitudinal direction connects
Depending on the number and chip volume of mouth mold block 200.
Because each programmable logic cells 100 needs whole signals to be transmitted, so that it completes concrete function,
Corresponding, each longitudinal interface module 200 is also required to whole signals to be transmitted, to support it to complete concrete function, therefore,
In the embodiment of the present invention, in longitudinal interface module 200, the transverse branch driving is also equipped with, likewise, transverse branch is driven
Dynamic to electrically connect multiple longitudinal interface modules 200 according to certain algorithm rule, then transverse branch driving will be from laterally driven mould
The signal to be transmitted that block receives is passed in other longitudinal interface modules 200 with annexation, its specific connection knot
Structure and signal transmission process to be transmitted may be referred to the signal transduction process to be transmitted in programmable logic cells 100, finally make
Whole signals to be transmitted can be received by obtaining each longitudinal interface module 200.
Further, the detailed description process of the signal to be transmitted in the embodiment of the present invention is as follows：
The laterally driven module is provided with N number of output lead, and each described longitudinal interface module 200 electrically connects H
The output lead, it is just whole more than or equal to 1 that the M longitudinal interface modules 200, which are one group, wherein N=H*M, N, H, M,
Number；
Longitudinal interface module 200 described in every group mutually transmits the signal to be transmitted, so that each longitudinal interface mould
Block 200 receives N number of signal to be transmitted；
The individual programmable logic cells 100 of M of connection corresponding with M described longitudinal interface modules 200 are one group, described
The M programmable logic cells 100 are by the transverse branch drive connection, so that each programmable logic cells
100 receive N number of signal.
In the embodiment of the present invention, it is assumed that each laterally driven module exports 9 signals, has 9 output leads, preferably
, each longitudinal interface module 200 connects three output leads, specifically, this 9 signals are divided into 3 by laterally driven module
Group, it is specially：hs<8:0>Signal is divided into hs0, hs3 and hs6；Hs1, hs4 and hs7；Hs2, hs5 and hs8, actual packet side
Formula is not limited to this form gone out given in the present embodiment.Each longitudinal interface module 200 connects three output leads, and
Receive its corresponding one group of signal.Now, the driving of the first transverse branch electrically connects other two programmable logic cells 100
Annexation can be specifically：The driving of first transverse branch electrically connects the second programmable logic cells 100 to the left, electric to the right
Connect the 3rd programmable logic cells 100；Signalling formula is：First transverse branch is driven first group of signal difference to the left
Second and the 3rd programmable logic cells 100 are sent to the right, it is corresponding, second and the 3rd programmable logic cells 100
Driven by each internal second, third transverse branch set to the first programmable logic cells 100 and send second group and the
Three groups of signals, hence in so that the first programmable logic cells 100 can receive three groups of signals, to complete corresponding function.
It should be noted that the multiple programmable logic cells 100 of each transverse branch drive connection, its connected mode is simultaneously
It is not limited to cited by the embodiment of the present invention, other any connected modes that can realize signal transmission are subjected to.
Embodiment three
Another embodiment of the present invention also provides a kind of clock network structure, and as seen in figures 3-6, Fig. 3 is implemented for the present invention
The structural representation one for the clock network structure that example provides；Fig. 4 is the structure of clock network structure provided in an embodiment of the present invention
Schematic diagram two；Fig. 5 is the structural representation of signal selector provided in an embodiment of the present invention；Fig. 6 provides for the embodiment of the present invention
Laterally driven module structural representation.The clock network structure includes the Clock Tree any one of above-described embodiment
Unit, wherein,
The clock network also includes signal selector, and the signal selector is electrically connected to laterally driven module, is used for
Signal to be transmitted is sent to the laterally driven module；
The signal selector is provided with selection signal end, and the selection signal end is used to input first choice signal；Institute
The signal to be transmitted that signal selector inputs according to the first choice signal behavior is stated, the signal to be transmitted is believed including clock
Number and global configuration signal.
Specifically, as shown in figure 3, signal selector is used to send signal to be transmitted to whole clock network structure, its is defeated
Go out end and be electrically connected to laterally driven module；Laterally driven module drives longitudinal interface module to the left and to the right respectively, and left side is indulged
Be first group to interface module, the longitudinal interface module on right side is second group, each longitudinal interface module 200 respectively upwards and
Multiple programmable logic cells 100 are connected downwards.Three laterally driven modules are show schematically in Fig. 3, and are corresponded to therewith
Six groups of longitudinal interface modules.
It should be noted that as shown in figure 4, laterally driven module and longitudinal interface mould are not intended to limit in the technical program
The number of block, programmable logic cells, A, B, C are more than 0 positive integer in Fig. 4, and C is less than or equal to B, and B is less than or equal to A；It is described
Laterally driven module has multiple, each laterally driven module and the connection for the longitudinal interface module group being connected to the left and to the right
Relation is identical, and the number of laterally driven module does not produce substantive shadow to clock network structure provided in an embodiment of the present invention
Ring.Corresponding, the change of the number for the programmable logic cells 100 being connected with longitudinal interface module 200 has no effect on the two it
Between signal transmission form, its specific transmission means refer to embodiment one and embodiment two, further, multiple horizontal strokes in Fig. 4
To drive module, multiple longitudinal interface modules and multiple programmable logic cells, represented respectively with the ellipsis of correspondence position.
Further, in the embodiment of the present invention, as shown in figure 5, signal selector has two kinds of input sources, one of which is defeated
Enter source input is clock signal, and the input of another input source is global configuration signal, in the embodiment of the present invention, by believing
Selection signal end is set in number selector, to the input Source Type of control signal selector, generally, selection signal end
Input signal be defaulted as low level, the input source of signal selector is defaulted as clock signal, and when selection signal end receives
Input signal when being high level, then the input source of signal selector is converted to global configuration signal.
The transmission path of existing configuration FPGA global configuration signals needs to take a long time, and the time transmitted is inclined
Difference is larger, and in the embodiment of the present invention, by clock network structural transmission global configuration signal, it on the one hand make use of clock network
Not tranmitting data register signal time space, the wasting of resources is avoided, while greatly save the transmission time of global configuration signal；Separately
On the one hand, the characteristics of time deviation is small when make use of clock network transmission signal, FPGA high-speed applications are more beneficial for.
Further, as shown in fig. 6, in clock network structure provided in an embodiment of the present invention, the laterally driven module
The second selection signal end is additionally provided with, the second selection signal end is used to input the second selection signal；The laterally driven mould
Root tuber receives external signal, and be transferred to the longitudinal interface module 200 according to second selection signal.
Specifically, the second selection signal that the selection signal of ordinary circumstance second termination receives is low level, laterally driven mould
The mode of operation of block is pattern 1：Clock signal is received, and clock signal is sent to longitudinal interface module 200；And work as user certainly
When the signal of definition needs high-speed transfer, the second selection signal that the second selection signal termination receives is high level, then laterally drives
The working mode change of dynamic model block is pattern 2：External signal is received, and external signal is passed into longitudinal interface module 200, should
External signal can be other any signals of clock signal or User Defined configuration, and the present embodiment is not done to this
Limitation.
For example, with reference to Fig. 3 and Fig. 6, the transmission path of signal is in pattern 1, and signal selector is to laterally driven mould
Block sends 9 signals, and then laterally driven module to the left and to the right respectively sends 9 signals to different longitudinal interface modules
In 200, specific sending method detailed in Example one and embodiment two；Then longitudinal interface module 200 is then divided up and down
Signal to be transmitted is not sent to Programmadle logic unit.
And when the second selection signal that the second selection signal termination receives is high level, the Working mould of laterally driven module
Formula is adjusted to pattern 2, specifically, can be, laterally driven module stops the clock signal from signal selector being sent to
Longitudinal interface module 200, at the same time, the user-defined signal for needing quickly to transmit, namely external signal pass through FPGA
The longitudinal interface module 200 for being delivered to left side as shown in Figure 3 inputs, and longitudinal interface module 200 sends the self-defined signal
To laterally driven module, laterally driven module sends the self-defined signal to the longitudinal interface module 200 on right side, then again by
Longitudinal interface module 200 sends the high speed transmission for programmable logic cells 100, completing signal.In the embodiment of the present invention, also may be used
To realize the transmission from the longitudinal interface module 200 to the left of right side longitudinal interface module 200.The present embodiment is that user transmits signal
More Path selections are provided, improve operating efficiency.
The present invention also provides a kind of FPGA timing topologys, including the clock network knot as described in above-mentioned any one of embodiment
Structure.Above-mentioned configurability of the clock network structure based on FPGA, can not only realize the extension to high-performance clock, can also be real
Existing global configuration information zero deflection transmission, and the laterally driven module of configurable different mode, by being multiplexed longitudinal interface, more
User-defined signal can be transmitted.
In summary, specific case used herein is to a kind of Clock Tree unit provided in an embodiment of the present invention, clock
The embodiment of network structure and FPGA timing topologys is set forth, and the explanation of above example is only intended to help and understands this
The scheme and its core concept of invention；Meanwhile for those of ordinary skill in the art, according to the thought of the present invention, specific
There will be changes in embodiment and application, in summary, this specification content should not be construed as to the present invention's
Limitation, protection scope of the present invention should be defined by appended claim.
Claims (7)
1. a kind of Clock Tree unit, it is characterised in that the Clock Tree unit includes：Laterally driven module, multiple longitudinal interfaces
Module, multiple programmable logic cells, transverse branch driving is provided with the programmable logic cells；
Laterally driven module, multiple longitudinal interface modules are electrically connected to, it is to be passed for being sent to the longitudinal interface module
Defeated signal；
The longitudinal interface module, connection corresponding with transverse branch driving, institute is sent for being driven to the transverse branch
State signal to be transmitted；
The transverse branch is driven for making the signal to be transmitted be transmitted between multiple programmable logic cells.
2. Clock Tree unit according to claim 1, it is characterised in that the output end of the laterally driven module is provided with
Multiple output leads, each described output lead transmit a signal to be transmitted；
Each described longitudinal interface module electrically connects with least one in multiple output leads, described defeated for receiving
Go out the signal to be transmitted of lead transmission.
3. Clock Tree unit according to claim 2, it is characterised in that be provided with the horizontal stroke in the longitudinal interface module
To branch drives, multiple longitudinal interface modules are driven by the transverse branch and electrically connected, and the transverse branch driving is used
Transmitted in making the signal to be transmitted between multiple longitudinal interface modules.
4. Clock Tree unit according to claim 3, it is characterised in that
The laterally driven module is provided with N number of output lead, each described H described output of longitudinal interface module electrical connection
Lead, it is positive integer more than or equal to 1 that M longitudinal interface modules, which be one group, wherein N=H*M, N, H, M,；
Longitudinal interface module described in every group mutually transmits the signal to be transmitted, so that each longitudinal interface module receives
N number of signal to be transmitted；
The M programmable logic cells of connection corresponding with M described longitudinal interface modules are one group, can described in the M is individual
Programmed logic unit by the transverse branch drive connection so that each programmable logic cells receive it is N number of described
Signal to be transmitted.
A kind of 5. clock network structure, it is characterised in that including the Clock Tree unit described in claim any one of 1-4, wherein,
The clock network also includes signal selector, and the signal selector is electrically connected to laterally driven module, for institute
State laterally driven module and send signal to be transmitted；
The signal selector is provided with selection signal end, and the selection signal end is used to input first choice signal；The letter
The signal to be transmitted that number selector inputs according to the first choice signal behavior, the signal to be transmitted include clock signal and
Global configuration signal.
6. clock network structure according to claim 5, it is characterised in that the laterally driven module is additionally provided with second
Selection signal end, the second selection signal end are used to input the second selection signal；The laterally driven module is according to described
Two selection signals, external signal is received, and be transferred to the longitudinal interface module.
7. a kind of FPGA timing topologys, it is characterised in that including the clock network structure described in claim any one of 5-6.
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| CN201711274987.6A CN107844672B (en) | 2017-12-06 | 2017-12-06 | Clock tree unit, clock network structure and FPGA clock structure |
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| CN201711274987.6A CN107844672B (en) | 2017-12-06 | 2017-12-06 | Clock tree unit, clock network structure and FPGA clock structure |
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| TWI714039B (en) * | 2019-03-27 | 2020-12-21 | 創意電子股份有限公司 | Timing model, method for building timing model, and related method for performing top-level analysis |
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