CN213365300U - Motion control card based on DSP - Google Patents

Abstract

The utility model provides a motion control card based on DSP, which comprises a DSP control circuit connected with a USB control circuit and a PC, wherein the USB control circuit is connected with the PC through a USB interface; the USB control circuit comprises a power supply circuit, a USB interface circuit of the USB control circuit, a JTAG circuit of the USB control circuit, an I2C circuit of the USB control circuit, a reset circuit of the USB control circuit and a clock circuit of the USB control circuit; in the power circuit, the + port of the port DC1 is connected with one end of a single-pole double-throw switch K3, the other end of the single-pole double-throw switch is connected with the D5V input, and the other port of the port DC1 is grounded. The utility model provides a motion control card based on DSP combines DSP chip TMS320F2812 that data processing ability and functional structure are powerful to have constituted the new generation motion control system who has the novelty jointly.

Description

Motion control card based on DSP

Technical Field

The utility model belongs to the technical field of controlling means, especially, relate to a motion control card based on DSP.

Background

With the progress of modern science and technology, a motion control system developed by a motion control technology becomes a quite important part in the current manufacturing industry, plays an important role in the machine tool industry and plays a very important role in more and more industries. However, for machine tools, the conventional motion control system cannot meet the requirements of modern industry due to the limitation of its own characteristics, and an open motion control system having the characteristics of expandability, interoperability, scalability, interchangeability, etc. becomes the main development direction of the motion control technology of machine tools in the 21 st century.

In China, the motion control system of the traditional machine tool adopts a relatively large number of systems developed based on an ISA bus or a system which is simply converted from the ISA bus to a PCI bus, and the operation speed and the data transmission speed of the motion control system cannot meet the requirements of the motion control development of the current machine tool to a certain extent. In recent years, in order to change the current situation, a machine tool control system of 'PC + motion control card' comes into operation, which is a type that is practical and popular at home and abroad at present, and the motion control card system is embedded into a PC by utilizing communication buses such as PCI, USB, RS485/RS232 and the like based on a PC information processing platform, so that the information processing capability of the PC and the openness of the motion control card system are organically combined, and the motion control system has the advantages of high openness, strong information processing capability and good universality, and can carry out efficient, rapid and accurate motion control on a machine tool. The motion control card of such control systems generally uses a single chip or a microprocessor, an application specific chip (ASIC), or even a DSP or an FPGA as a core processor.

The prior art comprises the following steps:

the first technology is as follows: journal paper instrument technology and sensor, 2012, 8, "application of embedded computer and DSP in electric spark wire cutting machine," the paper also adopts the design concept of "PC + motion control card," the DSP motion control board card with TMS320F2812 as core completes data exchange with the PC through PIC bus communication, and then completes motion control of the electric spark wire cutting machine through the motion control card.

According to the technology, a DSP (digital signal processor) TM320F2812 is used as a core of motion control, the PCI9052 is connected with a PCI port chip through a double-port SRAM (static random access memory) chip IDT7183, the PCI9052 uses 94LC46 as an EEPROM (electrically erasable programmable read-only memory) chip, and finally, the PCI interface of an embedded computer is used for communicating with a motion control card to complete data interaction, so that the motion control of a machine tool shaft is realized, and the interpolation cutting of workpieces is further realized. The general block diagram and the chip connection diagram of the system are shown in fig. 1 and fig. 2.

The technology has the following defects:

(1) the technology adopts PCI bus communication, and the applicability and the universality of the PCI communication are not strong compared with USB communication. PCI communication requires a computer to have a PCI/32-bit bus interface, but the notebook computer which is convenient to carry is basically not provided with the interface, and more is a USB interface, thereby limiting the universality and the application range thereof, and also bringing certain limitation and inconvenience to field installation and debugging of equipment such as a machine tool and the like.

(2) PCI interface can not hot plug, and the bus load is less, can not exceed 7, and the pin count is also few, is difficult to expand I/0 interface, and the socket of PCI bus is the slot type structure, and is not firm, and the heat dissipation is bad, adopts shared bus mechanism, can appear bus competition problem.

(3) The PCI bus transfer rate in this design is only 132M/S.

The second technology is as follows: journal article automation technology and application, 2014 9, "development of multi-axis motion control system based on DSP and USB interface", the design uses USB2.0 standard communication bus (which corresponds to CY7C68013A chip in FX2 series from Cypress (laplace) corporation) to complete data interaction between PC and dspms 320F2812 control system, and then completes control of the axis through TMS320F2812 control system.

The technology adopts DSP TMS320F2812 as the core of a motion control system, and then data interaction is completed with a PC through USB bus communication. The control system is directly connected with a DSP TMS320F2812 by an EZ-USB FX2 series chip CY7C68013A (USB2.0 communication standard chip) of Cypress corporation, and the other side of the control system is connected with a PC by a USB interface to complete the communication between the PC and the DSP and finally control the shaft motion. The overall system block diagram and the chip connection diagram are shown in fig. 3 and 4.

The USB2.0 communication standard has a low transmission rate, which is only about one eighth of the USB3.0 standard, and the functions of the data interface, the number of cable signals, the bus transaction protocol, the power management, the bus power supply, the port status, etc. are all behind those of the USB3.0 standard. More importantly, the data transmission capability is too low to support most data transmission modes. At present, the data transmission environment of high speed, even ultra high speed and ultra high speed + can not meet the requirements of users, and can not meet the data transmission of a machine tool motion control system.

The third technology: research on development and application of multi-axis motion controllers based on USB3.0 and FPGA [ D ]. nanjing aerospace university, 2015.

The design in the paper adopts an FPGA (EP3C40F484) control system as a core, and communicates with a PC (personal computer) through a USB3.0 standard communication bus, and the FPGA control system is utilized to complete the multi-axis motion control.

The motion control system of the technology adopts FPGA (EP3C4F484 as a core), exchanges data with a PC through a USB3.0 communication standard, and completes multi-axis motion control through the FPGA control system. The structural block diagram of the motion control system is shown in fig. 5.

The FPGA cannot process multi-event tasks, is not suitable for conditional operation, cannot be used for particularly complex multi-algorithm tasks, is difficult to plan in time sequence, and generally loses the original logic configuration after power failure.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to solve the defect that above-mentioned prior art exists, provide a motion control card based on DSP, combine DSP chip TMS320F2812 that data processing ability and functional structure are powerful to have constituted the new generation motion control system who has the novelty jointly.

The utility model adopts the following technical scheme:

a motion control card based on DSP comprises a DSP control circuit connected with a USB control circuit and a PC, wherein the USB control circuit is connected with the PC through a USB interface.

The USB control circuit comprises a power supply circuit, a USB interface circuit of the USB control circuit, a JTAG circuit of the USB control circuit, an I2C circuit of the USB control circuit, a reset circuit of the USB control circuit and a clock circuit of the USB control circuit.

In the power circuit, the + port of the port DC1 is connected with one end of a single-pole double-throw switch K3, the other end of the single-pole double-throw switch is connected with the D5V input, and the other port of the port DC1 is grounded.

An input of D5V is connected to an EN2 port of a chip RT8012A, one end of a resistor R4, one end of a capacitor C2, a PVDD2 port, a VDD port, and a PVDD1 port of the chip RT8012A, one end of a capacitor C3, one end of a resistor R6, an EN port of the chip RT8012A, the other end of a resistor R4 is connected to a PGOOD2 port of the chip RT8012A, the capacitor C2 is grounded, the capacitor C3 is grounded, the other end of a resistor R6 is connected to a PGOOD1 port, an input of 1 is connected to one end of an inductor L1, one end of a capacitor C1, one end of a resistor R1 is grounded, the other end of the chip RT8012 1 is connected to the FB 36nd port, the other end of the capacitor C1 is connected to the ground, the other end of the resistor R1 is connected to the resistor R1, the other end of the resistor R1, the resistor R1 is connected to the GND port of the chip RT8012 and the FB port of the PGND 8012 1, the other end of the resistor R1, the resistor R1 is connected to the ground, the other end of the.

The input of U3.3V is connected with one end of R17, the other end of R17 is connected with the positive pole of the photosensitive diode LED2, and the negative pole of the photosensitive diode is grounded.

The input of the D5V is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the anode of a photosensitive diode LED1, and the cathode of the photosensitive diode is grounded.

The input of D5V is connected with the EN2 port of chip RT8012A, one end of resistor R5, one end of capacitor C4, the PVDD2 port, the VDD port, the PVDD1 port of chip RT8012A, one end of capacitor C5, one end of resistor R7, the EN port of chip RT8012A, the other end of resistor R5 is connected with the other end of PGOOD2 of chip RT8012A, the other end of capacitor C4 is grounded, the other end of capacitor C5 is grounded, the input of D1.9V is connected with one end of inductor L2, one end of a capacitor C9 and one end of a resistor R11 are connected, the other end of an inductor L2 is connected with an LX2 port of a chip RT8012A, the other end of the capacitor C9 is grounded, the other end of the resistor R11 is connected with one end of a resistor R15, the port of an FB2 of the chip RT8012A, the other end of the resistor R15 is grounded, the GND port and the PGND port of the chip RT8012A are connected with the ground, D3.3V is connected with one end of a resistor L4, one end of a capacitor C10 and one end of a resistor R9, the other end of a resistor L4 is connected with the port of an RT8012ALX1, the other end of a capacitor C10 is grounded, the other end of a resistor R9.

D3.3V is connected with one end of the resistor R18, the other end of the resistor R18 is connected with the anode of the photosensitive diode LED3, and the cathode of the photosensitive diode LED3 is grounded.

The SSTX + port of the USB female seat is connected with a TX + port and an IO1 port of CH412K, the SSTX-port of the USB female seat is connected with a TX-port, an IO3 port of CH412K, GND of the USB female seat is grounded, connected with a GND port of CH412K and connected with one end of a capacitor C6, the SSRX + port of the USB female seat is connected with an IO2 port of CH412K, the SSRX-port of the USB female seat is connected with an IO3 port of CH412K, VBUS of the USB female seat is connected with a VCC port of CH412K and the other end of the capacitor C6.

The input of a JTAG circuit of the USB control circuit is connected with one end of a capacitor C11, the input of an U3.3V port of the JTAG download port is connected with a DVCC port of a JTAG download port, the other end of the capacitor C11 is connected with GND, a TMS port is connected with TMS1, a TD1 port is connected with TDII, a TDO port is connected with TDO11, a TCK port is connected with TCK1, a TRS port is connected with TRST #, and a DGND port is;

an I2C circuit of a USB control circuit, an NC port, an A2 port and a GND port of an AT24C08 in the I2C circuit are connected with the ground, an input of U3.3V is connected with one end of a capacitor C1, one end of VCC, one end of a resistor R2 and one end of a resistor R3, the other end of the C1 is connected with the ground, the other end of the resistor R2 is connected with an SCL port of the AT24C08, the other end of the resistor R3 is connected with an SDA port of the AT24C08, and a WP port is connected with.

The RESET circuit of the USB control circuit is characterized in that a RESET # is connected with one end of a resistor R16, one end of a key K1, one end of a capacitor C12, the other end of the resistor R16 is connected with U3.3V, the other end of the key K1 is grounded, and the other end of the capacitor C12 is grounded.

U3.3V of a clock circuit of the USB control circuit is connected with one end of a magnetic bead L5, the other end of the magnetic bead L5 is connected with a VDD port of a crystal oscillator and one end of a capacitor C13, the other end of the capacitor C13 is grounded and connected with a GND port of the crystal oscillator, an OUT port of the crystal oscillator is connected with one end of a resistor R19, and the other end of the resistor R19 is connected with a CLKIN;

the DSP control circuit comprises a reset circuit of the DSP control circuit, a JTAG circuit of the DSP control circuit, a clock circuit of the DSP control circuit and an E2ROM circuit of the DSP control circuit.

In the reset circuit of the DSP control circuit, the MR port of the chip MAX708 is connected with one end of a switch K2, the other end of the switch K2 is grounded, the input of D3.3V is connected with the VCC port of the chip MAX708 and one end of a capacitor C36, the other end of a capacitor C36 is connected with the GND port of the chip MAX708 and the PFI of the chip MAX708, and is grounded, the RST port of the chip MAX708 is connected with one end of a resistor R40, and the other end of a resistor R40 is connected.

In the JTAG circuit of the DSP control circuit, a DVCC port of a JTAG download interface is connected with D3.3V input end and C37 end, the other end of the capacitor C37 is grounded, a TCK port is connected with TCK, an EMUO port is connected with one end of a resistor R44, the other end of a resistor R44 is connected with D3.3V input end and one end of a resistor R45, the other end of a resistor R45 is connected with an EMUI port, a DGND port is connected in parallel and grounded, a TRST port is connected with one end of a resistor R43, and the other end of the resistor R36.

The E2ROM circuit of the DSP control circuit, an NC port, an A2 port and a GND port of an AT24C08 chip are grounded, the D3.3V input is connected with one end of a capacitor C35 and a VCC port of an AT24C08, one end of a resistor R41 and one end of a resistor R42, the other end of the capacitor C35 is grounded, the other end of the resistor R41 is connected with an SCL port of the AT24C08, and the other end of the resistor R42 is connected with an SDA port of the AT24C 08.

In the clock circuit of the DSP control circuit, an OUT port of a T30MHz crystal oscillator is connected with X1, a GND port is connected with one end of a capacitor C8 and is grounded, and a VDD port is connected with a D3.3V input and the other end of a capacitor C38.

The DSP control circuit further comprises an external RAM, wherein an IS61LV25616AL chip IS adopted as the external RAM chip, an SST39VF800A chip IS adopted as the external FLASH, and the SST39VF800A chip IS adopted as the external FLASH.

The further technical scheme is that the DSP control circuit adopts a TMS320F2812 chip.

The further technical scheme is that the USB control circuit adopts a CYUSB3014 chip.

The utility model has the advantages that:

the utility model discloses based on the design theory of "PC + motion control card", constitute the motion control card jointly through USB3.0 standard communication bus (correspond to the CYUSB3014 chip that uses Cypress (Seapace) company FX3 series) and DSP TMS320F2812 control system, accomplish the exchange of data with the PC again, finally accomplish the motion control to the lathe through this motion control card (motion control system).

The utility model discloses use the USB interface to support the hot plug, plug-and-play, the extension interface is easy, can connect a plurality of equipment, can expand 127 at most, and secondly the USB interface plug is convenient, and is not fragile, even damage also be liable to change.

The utility model discloses use USB3.0 communication standard, its transmission rate can reach 500MB/S, is USB2.0 transmission rate' S8 times more, has greatly improved data exchange speed.

The utility model discloses with prior art among the background art two to compare as shown in following table 1, table 2:

table 1: the USB3.0 communication standard is compared with the USB2.0 communication standard

The utility model discloses a what this technique adopted is USB3.0 communication standard and USB2.0 communication standard.

TABLE 2 USB3.0 vs. USB2.0 data transfer

It can be seen from the two tables that the USB2.0 communication standard has a low transmission rate, which is only about one eighth of the USB3.0 standard, and the functions of the data interface, the number of cable signals, the bus transaction protocol, the power management, the bus power supply, the port status, etc. are all behind those of the USB3.0 standard. Most importantly, the data transmission capability is too low to support most data transmission modes. At present, the data transmission environment of high speed, even ultra high speed and ultra high speed + can not meet the requirements of users, and can not meet the data transmission of a machine tool motion control system.

The utility model discloses with the advantage of the three contrasts of background art:

the utility model discloses a DSP TMS320F2812 is as the core of motion control system (motion control card), it is faster to have execution instruction speed, adopt pipeline technique, reduce every instruction execution time, piece multibus, can get simultaneously and indicate and a plurality of data access operation, independent accumulation its and adder, can accomplish multiplication and accumulation operation simultaneously in a cycle, have DMA channel controller and serial communication mouth etc. be convenient for data transfer, there are interrupt handler and timing controller, be convenient for constitute small-scale system, have software and hardware waiting function, can with advantages such as various memory interfaces, its software flexibility is very high secondly, be applicable to the condition process, especially complicated many algorithm task, the accessible is compiled or high-level language (like C language) is programmed, the real-time implementation scheme, software update is fast, the reliability of system has greatly been improved, Versatility, replaceability, and flexibility.

In the third background technology, an FPGA is adopted, and compared with a DSP, the FPGA cannot process multi-event tasks, is not suitable for conditional operation, cannot be used for particularly complex multi-algorithm tasks, is difficult to plan in time sequence, and generally loses the original logic configuration after power failure.

Drawings

FIG. 1 is a general block diagram of a system according to the first background art;

FIG. 2 is a pin connection diagram of a chip according to the prior art;

FIG. 3 is a block diagram of a system according to a second prior art;

FIG. 4 is a diagram of a chip connection of a second prior art;

FIG. 5 is a block diagram of a prior art triple motion control system;

fig. 6 is a block diagram of the structure of the motion control card of the present invention;

FIG. 7 is a pin diagram of RT 8012A;

FIG. 8 is a circuit diagram of RT8012A classic;

FIG. 9 is a circuit diagram of a resistor divider circuit;

fig. 10 is a power supply circuit diagram of the present invention;

FIG. 11 is a reset circuit diagram;

FIG. 12 is a clock circuit diagram;

FIG. 13 is a JTAG circuit diagram;

FIG. 14 is a circuit diagram of a peripheral RAM;

FIG. 15 is a circuit diagram of a peripheral FLASH;

FIG. 16 is an E2ROM circuit diagram;

FIG. 17 is a circuit diagram of a PWM bus;

fig. 18 is an internal structural view of the CYUSB 3014;

FIG. 19 is a CYUSB3014 logic block diagram;

fig. 20 shows CH412K (ESD protection);

FIG. 21 is a USB port circuit diagram of a USB control circuit;

FIG. 22 is a CYUSB3014JTAG interface diagram;

FIG. 23 is a clock circuit diagram of a USB control circuit;

FIG. 24 is a reset circuit diagram of the USB control circuit;

FIG. 25 is a circuit diagram of an I2C (EEPROM) of the USB control circuit;

FIG. 26 is a circuit diagram showing the connection between the DSP control circuit and the USB control circuit;

in the figure: 1-power circuit, 2-USB interface circuit of USB control circuit, 3-JTAG circuit of USB control circuit, 4-I2C circuit of USB control circuit, 5-reset circuit of USB control circuit, 6-clock circuit of USB control circuit;

a reset circuit of the 7-DSP control circuit, a JTAG circuit of the 8-DSP control circuit, a clock circuit of the 9-DSP control circuit and an E2ROM circuit of the 10-DSP control circuit.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention are clearly and completely described below, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

At present, a motion control card of a machine tool is developed based on an ISA bus or is a simple system for converting the ISA bus into the PCI bus in China, the operation speed and the data transmission speed of the motion control card can not meet the requirements of the motion control development of the current machine tool to a certain extent, and the existing motion control system (the motion control card) has low applicability and large limitation, or has low data transmission rate or insufficient processing capacity of a controller.

In order to overcome the defects, the utility model adopts the bus communication mode of the USB3.0 communication standard, and combines the DSP chip TMS320F2812 with strong data processing capability and functional structure to jointly form a new generation motion control system (motion control card) with innovation.

The machine tool motion control system (motion control card) developed by the DSP is provided with an independent DMA bus and a controller thereof, and fully utilizes the data processing capacity of the DSP, so that the numerical control system has a master-slave processor structure, namely the DSP completes frequent data operation and operation work such as background control, interpolation operation, servo control, feedback processing and the like, and the PC completes foreground control such as human-computer interface management, information display, a preprocessor and the like, thereby transplanting a higher-requirement interpolation program into the DSP to complete the interpolation control, and improving the real-time property of the system. The bus communication mode of the USB3.0 communication standard enables the communication between the PC and the DSP to achieve the ultra-high data exchange of 5Gbps (500MB/s), further reduces the time of single data exchange between the DSP and the PC, and improves the real-time property of data processing of the DSP. A motion control system (motion control card) developed based on the USB3.0 bus communication and the DSP TMS320F2812 main control chip can greatly improve the processing performance of the current machine tool, expand the application field of the machine tool and have very good technical value and huge economic benefit.

As shown in fig. 6, the utility model discloses a motion control card based on DSP, it mainly comprises USB control system and DSP control system two parts jointly, has still included its necessary circuit part in each part system to two systems have adopted same electrical power generating system to pass through the steady voltage of steady voltage chip and be different voltage values, supply power again.

Power supply circuit 1

Because the maximum output voltage of the interface of USB3.0 is 5V but the maximum output current is only 900mA, obviously if directly use this USB interface power supply, often can make control chip be in unstable operating condition and probably appear the condition that can't work even, consequently the utility model discloses a 5V/2A's power adapter is as the one-level power input of this motion control card for convert 22V alternating current into 5V direct current.

Looking up and collating the CYUSB3014 and DSP TMS320F2812 chip data shows that the two main control chips TMS320F2812 and CYUSB3014 are powered by double power supplies, i.e. the power supply of the chip core and the power supply of the outer core are separated. The power supply voltage of the inner core and the outer core of the TMS320F2812 is 1.8V (or 1.9V, when the requirement of a control system on the DSP operation speed is not high, the power supply is only required to be 1.8V, if the control system is required to be used for high-speed operation, the power supply is required to be 1.9V, obviously, the design needs to supply power with the voltage of 1.9V) and 3.3V respectively; for the CYUSB3014, to ensure the high-speed data transmission system to work normally, at least two voltages, 1.2V and 3.3V, are provided, 1.2V is used for core power supply, and 3.3V is used for other electrical domains. Therefore, the power circuit 1 of the motion control card needs to provide three voltages of 1.2V, 1.9V and 3.3V and the current is 1 to 2A to stably and efficiently operate the crossbar control chip. By taking the above factors into consideration, a 1A/1.5A,1.2MHz dual-channel synchronous buck-type DC/DC converter RT8012A is selected here, and its pin diagram is shown in fig. 7.

RT8012A is a dual pulse width modulated, current mode, buck converter with a size of 4 × 0.75mm. The input voltage range of the over-temperature protective agent is 2.6V to 5.5V, the constant 1.2MHz switching frequency is realized, each output voltage is adjusted from 0.8V to 5V, and the over-temperature protective agent has an over-temperature protective agent short-circuit protection function for the load current of each channel 1A and 1.5A. As shown in FIG. 8, a 5V input VIN is connected with one end of a resistor R1, one end of a capacitor C1, one end of a Chip PVDD1, one end of a capacitor C1, one end of a resistor R1, the other end of the R1 is connected with a PGOOD1 port of a Chip RT8012 1, the other end of the capacitor C1 is grounded, the other end of the resistor R1 is connected with a port of a PG00D1, the port of the EN1 is connected with a ChipEnable input, the port of the port LX1 is connected with one end of an inductor L1, the other end of the inductor L1 is connected with one end of the resistor R1, the output VOUT and one end of the capacitor C1, the other end of the capacitor C1 is grounded, the other end of the capacitor FB1 is connected with one end of the port R1, the resistor R1 is grounded, the other end of the port of the resistor R1 is connected with a resistor L1, the other end of the resistor FB1 is grounded, the other end of the resistor FB1 is connected with the ground, the other end of, the other end of the resistor R5 is grounded.

The output voltage VOUT is regulated by a resistor divider connected between FB1 and FB2 as shown in fig. 9, VOUT is connected to one end of resistor R1, the other end of resistor R1 is connected to resistor R2 and terminal FB, and the other end of resistor R2 is connected to GND terminal and ground.

(wherein V_REF＝0.8V)

As shown in fig. 10, for the power circuit diagram of the present invention, the + port of the port DC is connected to one end of the single-pole double-throw switch K3, the other end of the single-pole double-throw switch is connected to D5V, and the-port of the port DC is grounded.

The power supply circuit 1 comprises a D5V connected with an EN2 port of a chip RT8012A, one end of a resistor R4, one end of a capacitor C2, a PVDD2 port, a PVDD2 port and a VDD port of the chip RT8012A, the circuit comprises a PVDD port, one end of a capacitor C, one end of a resistor R, an EN port of a chip RT8012, the other end of the resistor R is connected with a PGOOD port of the chip RT8012, the capacitor C is grounded, the other end of the resistor R is connected with the PGOOD port, one end of an inductor L, one end of a capacitor C, one end of a resistor R, the other end of the inductor L is connected with an LX port of the chip RT8012, the other end of the capacitor C is grounded, the other end of the resistor R is connected with an FB port, one end of a resistor R and the other end of the resistor R are connected with a GND port and a PGND port of the chip RT8012 and are connected with each other and grounded, one end of the inductor L, one end of the capacitor C, one end.

U3.3V input is connected with one end of R17, the other end of R17 is connected with the positive pole of the photosensitive diode LED2, the negative pole of the photosensitive diode is grounded;

D5V is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the anode of a photosensitive diode LED1, and the cathode of the photosensitive diode is grounded.

The D5 is connected with an EN port of the chip RT8012, one end of a resistor R, one end of a capacitor C, a PVDD port, a VDD port, a PVDD port of the chip RT8012, one end of a capacitor C, one end of a resistor R, the EN port of the chip RT8012, the other end of the resistor R is connected with the other end of a PGOOD of the chip RT8012, the other end of the capacitor C is grounded, the input is connected with one end of an inductor L, one end of the capacitor C and one end of the resistor R, the other end of the inductor L is connected with an LX port of the chip RT8012, the other end of the capacitor C is grounded, the other end of the resistor R is connected with one end of a resistor R, the FB port of the chip RT8012, the other end of the resistor R is grounded, the GND port and the PGND port of the chip RT8012 are grounded, one.

D3.3V is connected with one end of the resistor R18, the other end of the resistor R18 is connected with the anode of the photosensitive diode LED3, and the cathode of the photosensitive diode LED3 is grounded.

TMS320F2812 control system circuit

1) Reset circuit

The DSP control system needs to be RESET when being started, so that the CPU and all parts of the system are in a determined initial state and start to work from an initial stage, and the RESET pin of the TMS320F2812 is/RESET which is effective in low level. Meanwhile, the stability and the safety of the program and the operation and data are the problems that the control system must consider in different operation environments, the problem which is most likely to be encountered is that the CPU enters into a dead cycle due to interference, a software trap and a software watchdog are generally used for avoiding the phenomenon, and for the general operation environment, if the continuous operation or the severe environment condition often cannot meet the requirement, the hardware watchdog is used for restarting the CPU, so that the program is recovered to the normal operation. Also, some systems require protection of currently useful data if the power supply voltage fluctuates significantly or is powered down. Therefore, the reset circuit adopts a MAX708 chip which has power supply monitoring and data protection and a watchdog and can simultaneously output effective reset signals of high level and low level. The reset signal can be triggered by VCC voltage, manual reset input, or by an independent comparator, the circuit is shown in fig. 11, the reset circuit 7 of the DSP control circuit, the MR port of the chip MAX708 is connected to one end of the switch K2, the other end of the switch K2 is grounded, the D3.3V input is connected to the VCC port of the chip MAX708 and one end of the capacitor C36, the other end of the capacitor C36 is connected to the GND port of the chip MAX708 and to ground, the PFI port of the chip MAX708 is connected to ground, the RST port of the chip MAX708 is connected to one end of the resistor R40, and the other end of the resistor R40 is connected to the D3.3V.

K2 is a manual reset spring switch, one end of which is connected with the MR pin of MAX708, and the other end is grounded, when the key is pressed, a low level pulse is generated and sent to the reset generator, thereby generating a reset pulse output of 200ms, and achieving the purpose of resetting.

2) Clock circuit

The clock circuit cannot be separated from a phase-locked loop circuit in a chip, and the phase-locked loop is a circuit for controlling a crystal oscillator to keep a constant phase relative to a reference signal, and is widely used in a vertical communication system. At present, the on-chip phase-locked loop integrated by a microprocessor or a DSP mainly has the main function of configuring an on-chip peripheral clock in real time through software, so that the flexibility and the reliability of a system are improved. In addition, because of the use of software programmable phase locked loops, the system processor is designed to allow for lower operating frequencies externally, while the system clock is increased on-chip via the phase locked loop microprocessor. By doing so, the dependence of the system on an external clock and electromagnetic interference can be effectively reduced, the reliability of the system in starting and running is improved, and the design requirement of the system on hardware is reduced.

An on-chip crystal oscillator and a phase-locked loop module of the TMS320F2812 processor provide clock signals for a core and peripheral equipment, and control the low-power-consumption working mode of the device. The on-chip crystal oscillator module allows the device to be clocked in 2 ways, i.e. using an internal oscillator or an external clock source.

(1) An internal oscillator is used to connect a quartz crystal, typically 30MHz, between the two pins XIXCLKIN and X2.

The system works by programming to select a 5-times-multiplied PLL function, which can realize the highest operating frequency (150MHz) of F2812. The circuit only needs a crystal and two capacitors, is low in price and small in size, can meet the level requirement of a clock signal, but is poor in driving capability, cannot be used by a plurality of devices, and is small in frequency range, and when the circuit is used at 20KHz-60MHz, the circuit needs to be accurately configured with a correct load capacitor to enable the frequency of an output clock to be accurate and stable.

(2) The external clock is adopted to directly connect the input clock signal to the XI/XCLKIN pin, and the X2 is suspended without using an internal oscillator. The circuit is built by adopting an active crystal oscillator, and the active crystal oscillator is generally used as follows: one pin is suspended, two pins are grounded, three pins are connected with output, and four pins are connected with voltage. Compared with a passive crystal, the active crystal oscillator has the defects that the signal level is fixed, a proper output level needs to be selected, the flexibility is poor, the price is high, but the circuit is simple, the size is small, the frequency range is wide, the driving capability of 1 Hz-400MHz is strong, the active crystal oscillator can be used for a plurality of devices, and the active crystal oscillator can be applied to a system sensitive to time sequence requirements.

Since the operational control card has a high sensitivity to the timing requirement, an external clock is used to design a clock circuit, and the design circuit is shown in fig. 12.

In the clock circuit 9 of the DSP control circuit, the OUT port of the T30MHz crystal oscillator is connected with X1, the GND port is connected with one end of a capacitor C38 and is grounded, and the VDD port is connected with the D3.3V input and the other end of the capacitor C38.

The 30MHz active crystal oscillator packaged by the chip 7050 is adopted, the space occupation rate of the crystal oscillator on a PCB is reduced, and a decoupling capacitor is added between pins 2 and 4, so that the stability of a clock source is ensured.

3) JTAG circuit

The DSP simulator realizes the simulation function through a scanning simulation pin provided on the DSP chip, and the scanning simulation solves the problems of signal distortion, poor reliability of a simulation plug and the like caused by overlong cable in the traditional circuit simulation. And the adoption of scanning simulation makes online simulation possible to bring great inconvenience to debugging. JTAG interface circuit is as shown in FIG. 13, JTAG circuit 8 of DSP control circuit, DVCC port of JTAG download interface connects D3.3V input end, capacitance C37 end, capacitance C37 other end ground, TCK port connects TCK, EMUO connects one end of resistance R44, another end of resistance R44 connects D3.3V input, one end of resistance R45, another end of resistance R45 connects EMUI port, DGND port connects in parallel and ground, TRST port connects one end of resistance R43, another end of resistance R43 connects ground.

4) External RAM/FLASH

In order to increase the program storage space of the system and improve the working efficiency of the system, the motion control card is provided with an external RAM circuit and a FLASH circuit. The selected external RAM chip model IS IS6ILV25616AL, which has a data space size of 256KBx16 bit. 18 address lines A0-o 7 are used, and the maximum address line is 256 KB; 16 data lines from D0 to D15. Chip select C56 and the WR and RD signals are all derived from the DSP. The model of the external FFLASH chip is SST39VF800A, and the external FFLASH chip has a data space of 512KBx16bit, so that a user can conveniently write a larger program. In the design, the chip has 1 more address lines than the peripheral RAM, so the maximum address line can reach 512KB, and a chip selection signal is CS 2. The specific connection diagram of the design is shown in fig. 14 and 15.

5) E2ROM circuit

E2ROM is an abbreviation for EEPROM and refers to "Electrically Erasable Programmable Read Only Memory", i.e., "Electrically Erasable Programmable Read-Only Memory". The method has the advantages of complex process, excessive consumed gate circuits, longer reprogramming time and lower effective reprogramming times, but has the greatest advantage of being capable of being erased by electric signals directly and written by the electric signals. The circuit is designed using an AT24C08 chip that provides an 8192-bit serial Electrically Erasable Programmable Read Only Memory (EEPROM) organized in 1024 words by 8 bits. Suitable for many industrial or commercial grade applications requiring low power consumption and low voltage operation. Optionally, a space-saving 8-pin PDIP, 8-pin JEDEC SOIC, 5-pin SOT23, etc. package and access through a 2-Wire serial interface. The method is characterized in that: filtering input to realize noise suppression; a bidirectional data transfer protocol; a write protection pin for realizing hardware data protection; allowing for page partial writes, high reliability. The design circuit is as shown in fig. 16, the E2ROM circuit 10 of the DSP control circuit has an AT24C08 chip with its NC port, a2 port, and GND port grounded, the D3.3V input is connected to one end of a capacitor C35 and the VCC port of an AT24C08, one end of a resistor R41, one end of a resistor R42, the other end of the capacitor C35 is grounded, the other end of the resistor R41 is connected to the SCL port of an AT24C08, and the other end of the resistor R42 is connected to the SDA port of an AT24C 08.

6) PWM bus

The DSP chip TMS320F2812 has 2 management circuits (EVA, EVB), each event management circuit can generate 5 independent PWM signals, wherein the comparison register has 3 circuits, and the general timer has 2 circuits. Theoretically, a maximum of 10 servo drivers can be controlled by 1 TMS320F2812 chip. The common numerical control systems include three-axis linkage, five-axis linkage and the like, and the number of motors which can be controlled by the motion control card is far larger than that of the motors in one numerical control system. Therefore, the utility model discloses a "PC + motion control card" numerical control system not only can satisfy multiaxis linkage numerical control system's basic requirement, still has very high expansibility, can realize a plurality of numerical control machine tool joint control even, has greatly strengthened multiaxis linkage numerical control system's function.

A74 HC245 chip is used in the design, the chip is a high-speed CMOS bus transceiving chip compatible with TTL device pins, a typical CMOS type tri-state buffer gate circuit and eight-way buffer circuits with controllable reverse directions are used, and the chip is mainly used for realizing bidirectional asynchronous communication of a data bus. To protect the fragile master chip, a buffer is typically added between the parallel interface of the master chip and the parallel interface of the external controlled device. When bidirectional asynchronous communication between the master control chip and the controlled device is required, a bidirectional eight-way buffer is selected, and the 74HC245 is designed for the requirement, as shown in fig. 17.

CYUSB3014 control circuit

CYUSB3014 is one of the EZ-USB FX3 series USB3.0 controller chips produced by CYPRESS, which has a parallel general programmable interface GPIFII which can be completely skimmed, can be seamlessly connected with any processor, ASIC or FPGA, integrates USB3.0 and USB2.0 physical layers to make the chip compatible with USB2.0 and USB3.0 protocols simultaneously, and has a high-performance 32bARM926EJS microprocessor core with the working frequency of 200MHz, so that the chip can be used in places with higher requirements on data processing.

Besides, a 512KB internal SRAM is integrated inside the chip, and is used for storing codes and configuration parameters and also used as a buffer area of a DMA channel inside the chip. It also supports many kinds of peripheral interfaces, including high-speed USB interface, second generation general programmable interface GPIFII and common UART interface, SPI interface, I2C interface, I2S interface and common GPIO interface. Therefore, the FX3-CYUSB3014 can be used to easily integrate the USB3.0 interface into any electronic system, so that the system can be connected with a PC at high speed, and the internal structure of the system is shown in FIG. 18.

The CYUSB3014 has the following four structural characteristics:

(1) barrier-free access 32CPU

The chip integrates a 512KB embedded SRAM to store code and data, and an 8KB instruction cache and data cache. The chip is provided with a 32b ARM9 core with the running frequency of 200MHz, the core can directly access a 16KB instruction Tight Connection Memory (TCM) and an 8KB data TCM, and the core also provides a JTAG interface for debugging of firmware, and firmware programs are directly downloaded into an internal RAM through the JTAG interface for online debugging.

(2) General purpose programmable interface (GPIF II)

The high-performance general programmable interface GPIF II has high-performance general programmable interface GPIF II, and the interface frequency of the GPIF II can reach 100 MHz. GPIFII is a programmable state and the flexible interface enabled by it can be used as a master or slave in an industrial standard or proprietary interface, both parallel and serial interfaces can be implemented by GPIFII. 256 firmware programmable states are provided, support for 8b, 16b/32b parallel data buses, and support for 14 configurable control pins using a 32-bit data bus.

(3)32 physical endpoints

An endpoint is the smallest unit of storage for data reception and transmission by a USB device. USB3.0 provides 32 physical endpoints, namely 16 input endpoints and 16 output endpoints. The end point can control the output end point in a range mode, the interrupt transmission end point, the batch transmission end point and the isochronous transmission end point respectively and is used for realizing four transmission modes of control, interrupt, batch and isochronous. The control endpoint completes the status information of the USB3.0 device. Of all endpoints, only the data of the control endpoint may be passed from the host to the control of the device, either powered down or from the control endpoint of the device to the host.

(4) I/O system

The CYUSB3014 can realize flexible pin configuration on both GPIF II and serial peripheral interfaces. Any unused control pins on the GPIF II interface (except CTL [15 ]) can be used as general purpose I/O, and similarly, any unused pins on the serial peripheral interface can also be configured as general purpose I/O.

The logic block diagram of the chip is an important part of the circuit design that must be referenced, and the correct pin connection and processing method are required to make the chip in the normal operation mode, which is shown in the CYUSB3014 logic block diagram 19.

1) USB port design

The main function of the USB port is to connect a dual-port data line between a PC and the CYUSB3014, and since the USB3.0 standard is adopted, the port here adopts a patch type USB3.0A female socket.

The USB3.0 female seat has 9 lines which are respectively an input differential line SSRX +/-, an output differential line SSTX +/-and two grounding pins for realizing a full-duplex transmission mode under a VBUS, a pair of differential lines D +/-, a USB3.0 protocol, and the differential lines are downward compatible with a USB2.0 bus, and the pins are connected with corresponding pins on a CYUSB3014 chip. Wherein the VBUS pin is used for connecting +5V voltage from a computer USB3.0 interface, a pair of 0.1uF (104) capacitors is required to be connected in series on an SSTX +/-differential line on a chip for filtering, and the sizes of the two alternating current coupling capacitors are reduced in order to avoid extra capacitance caused by a capacitor pad.

Secondly, the signal and GND pins of the USB interface have built-in ESD protection. Wherein the D +, D-, SSRX +, SSTX-, SSTX +, SSTX-pins have the highest Human Body Mode (HBM) internal ESD protection of + -2.2 KV. However, the USB interface is frequently inserted and inevitably contacts with a human body, and an ESD overvoltage of 8KV or even higher is generated when the human body contacts, which may cause transient interference, damage, and the like to the device, so a special ESD protection device is required to protect the USB3.0 interface.

The chip CH412K is used as an ESD protector for the four paths of differential signals SSRX +, SSRX-, SSTX + and SSTX-. The CH412K provides 4-channel low-capacitance diode protection and TVS transient voltage suppressor clamping, is a four-way ESD protection diode array, can bear the ESD pulse of the highest +/-15 KV human body model, +/-8 KV contact discharge and +/-15 KV air gap discharge specified by IEC61000-4-2, is suitable for high-speed and medium-low speed signals, and can be used for USB over-speed, high-speed and full-speed and low-speed signal ESD protection. The internal structure and external pin diagram of the chip are shown in fig. 20. The design principle of the USB port is shown in fig. 21, in the USB interface circuit 2 of the USB control circuit, SSTX + of the USB female socket is connected to TX +, IO1 of CH412K, SSTX-of the USB female socket is connected to TX-, IO3 of CH412K, GND of the USB female socket is grounded, connected to GND port of CH412K, and connected to one end of capacitor C6, SSRX + of the USB female socket is connected to IO2 shorts of CH412K, SSRX-of the USB female socket is connected to IO3 port of CH412K, VBUS of the USB female socket is connected to VCC port of CH412K, and the other end of capacitor C6.

2) JTAG interface

The ARM926EJ-S kernel of CYUSB3014D supports JTAG interface debugging. TDI, TDO, TCK, TMS and TRST # are respectively connected with corresponding pins of CYUSB3014, fixed 50K pull-up resistors are arranged in the pins TDI, TMS and TRST #, and fixed 10K pull-down resistors are arranged in the pin TCK, so that the JTAG interface does not need external pull-up/pull-down resistors, the JTAG pin can be directly connected with JTAG to debug the JTAG by only leading out the JTAG pin, and the debugger can debug firmware through an on-chip debugging circuit of a CPU core. In order to save design cost and time, the same 14-interface JTAG debugger of the DSP master control system is adopted here, the design circuit is shown in FIG. 22, JTAG circuits 3, U3.3V of the USB control circuit are connected with one end of a capacitor C11, a DVCC port of a JTAG download port, and the other end of the capacitor C11 is connected with GND.

Because the higher the clock frequency, the faster the working speed of the chip, and the higher the requirement for the running speed of the chip, a patch type 52MHz active crystal oscillator is selected as an input clock to provide a clock source for the chip, and each line of the FSLC [2:0] is connected to U3.3V through a 10K pull-up resistor. The clock circuit design is as shown in fig. 23, the clock circuit 6, U3.3V of the USB control circuit is connected to one end of a reactance L5, the other end of the reactance L5 is connected to one end of a crystal oscillator VDD port and one end of a capacitor C13, the other end of the capacitor C13 is grounded and connected to a crystal oscillator GND port, the crystal oscillator OUT port is connected to one end of a resistor R19, and the other end of the resistor R19 is connected to CLKIN.

Connect the magnetic bead at the VCC pin of crystal oscillator to connect 0.1uf (104) electric capacity between VCC and ground and prevent effectively and disturb, guaranteed the stability of clock source. The CYUSB3014 has two reset modes, a hard reset mode and a soft reset mode. Hard RESET completes the initialization of the chip by activating RESET # on the chip. The soft reset completes chip initialization by setting a proper position in a PP _ INI control register, and the soft reset is divided into two types of CPU reset and full-device reset. Resetting the CPU, namely resetting a CPU program counter, wherein the firmware is not required to be reloaded after the resetting; full device reset is the same as hard reset and the firmware must be reloaded after reset.

The utility model discloses a mode that RESETs firmly, among the system operation process, through pressing the button, can draw down the level of RESET # pin, force the RESET. In the circuit debugging process, the USB interface can be prevented from being frequently plugged and unplugged by adopting a hard reset mode, and the interface is effectively prevented from being damaged. The design of the RESET circuit is shown in fig. 24, the RESET circuit 5 of the USB control circuit, RESET # is connected with one end of a resistor R16, one end of a key K1, one end of a capacitor C12, the other end is connected with a terminal U3.3V, the other end of the key K1 is grounded, and the other end of the capacitor C12 is grounded.

3) I2C (EEPROM) circuit

The mask ROM of the CYUSB3014 is integrated with a boot loader, and the boot loader records that the CYUSB3014 can load boot images (firmware programs) through different interface modes such as USB, I2C, SPI (supporting SPI devices are M2516(16Mbit), M25P80(8Mbit) and M25P40(4Mbit) or the like), GPIF II asynchronous ADMUX mode, GPIFII synchronous ADMUX mode, GPIFII asynchronous SRAM mode and the like, thereby completing the wakeup and startup of the chip. The boot loader selects the boot mode by controlling three pins (BGA packages corresponding to L4, H4, G4, respectively) of PMODE [2:0], as shown in the following table:

the utility model discloses a "I2C, if fail, then can the USB guide", both the chip defaults to load firmware program to inside RAM from the external EEPROM of I2C, accomplishes equipment and enumerates again, if run into I2C geological cycle and data cycle mistake, the condition such as guide image of invalid signature then launches the USB guide mode. The PMODE [2:0] pins are set to: the PMODE [2] (L4) and PMODE [1] (H4) pins are suspended, and the PMODE [1] pin is connected to U3.3V through a 10K pull-up resistor. In addition, the I2C interface is powered using the VI05 electrical domain, which is independent of other serial peripherals. The I2C interface may thus gain flexibility to operate at voltages different from other serial interfaces. The bus frequencies supported by the I2C controller are 100KHz/400KHz and 1 MHz. When VI05 is 1.2V, the maximum supported operating frequency is 100 KHz. When VI05 is 1.8V, 2.5V or 3.3V, the supported working frequency is 400KHz and 1MHz, and 3.3V is adopted for power supply, so that the I2C working frequency reaches 1MHz, the re-enumeration speed of the chip is greatly improved, and the starting time is reduced. In order to save the design cost, the EEPROM chip of I2C here still selects the same AT24C08 as the DSP control circuit, the circuit design of which is shown in fig. 25.

The I2C circuit 4 of the USB control circuit, the NC port of AT24C08 in the I2C circuit, the A2 port, the GND port are connected and grounded, U3.3V is connected with one end of a capacitor C1, one end of VCC, one end of a resistor R2, one end of a resistor R3, the other end of the resistor R2 is connected with the SCL port of AT24C08, and the other end of the resistor R3 is connected with the SDA port of AT24C 08.

The design of the DSP control circuit and the USB control circuit is completed, the USB control circuit is already connected to the PC through the USB port, and the DSP control circuit and the USB control circuit are effectively connected to each other for the effective connection and data exchange between the PC and the DSP, as shown in fig. 26.

The description of each interface signal or bus is shown in the following table:

motion control card schematic

Motion control card PCB design

1) Design of circuit board layer number

Because the utility model discloses in used cypress (serplase) company FX3 series USB3.0 chip CYUSB3014, it adopts BGA encapsulation, 121 pins have been integrateed in 1cmx1 cm's chip bottom, the pin interval is only 0.8mm, therefore, single, the double-sided board can not satisfy this motion control card's requirement, can only select the multiply wood, but the circuit board number of piles is more, its design cost is higher, so this motion control card's design has adopted four-layer board [25], the number of piles structure of four-layer board generally is top layer-power plane (VCC) -stratum (GND) -bottom, perhaps top layer-stratum (GND) -power plane (VCC) -bottom.

The utility model discloses increased a positive lamella and a burden lamella between top, bottom. The positive layer can be used for routing signal lines and can also be used as a power line layer of multiple power supplies, copper cladding of the printed circuit board is reserved at routing positions, and copper cladding is removed at positions without routing (similar to a top layer and a bottom layer); the negative plate layer is equivalent to adding a reference plane and can be directly used as a VCC plane or a GND plane, and the two plane systems are completely covered with copper in a default mode, so that copper does not need to be covered after the PCB design is finished, and the planes are only required to be divided aiming at different VCC and GND in the design process. However, the CYUSB3014 BGA encapsulation chip pin that uses here is too much, and adopts four-layer board, and two-layer signal layer in top, bottom has can't satisfy the line demand, consequently, the utility model discloses do not set up solitary power plane (VCC), use the positive film layer that increases as the signal layer, both crossed the signal line and also crossed the power cord, the negative film layer is as public stratum (GND), its range upon range of structure is top layer-positive film layer (signal + power) -negative film layer (GND) -bottom.

2) Component layout

The layout of the components relates to various performances of the designed and manufactured circuit board, such as aesthetics, complexity, reliability, usability and the like, the reasonable layout of the components not only can reduce the time and money cost of the design and the manufacture of the circuit board, but also can reduce the manufacture difficulty, the wiring difficulty and the like of the circuit board, and when the motion control card is designed and manufactured, the layout of the components follows the following main points and methods:

(1) and performing modular layout. The components of the same module are firstly concentrated, and then the positions of the components are placed and adjusted according to a module schematic diagram, so that the reasonable layout of the components of a single module is finally realized.

(2) And (5) special component layout. The special components mainly comprise a DSP main control chip TMS320F2812, a CYUSB3014, a power adapter DC terminal, a USB3.0 port, a JTAG download port and the like, and the placement positions and the directions of the components are combined with actual use for placement.

(3) Layout of capacitors, resistors, inductors, etc. The placement of the filter capacitor, the resistor, the inductor and the like is close to the corresponding power supply pin, the pull-up pin and the pull-down pin of the chip to the greatest extent, so that the effects of better filtering and the like are achieved, the components are aligned, translated and the like, and the circuit board looks more attractive.

(4) For clock-related components such as active crystal oscillators and crystals, the components are far away from the CYUSB3014 as far as possible and are far away from I/O ports and power sockets.

(5) The AC coupling capacitors on the super speed differential pair SS TX are placed symmetrically and as close as possible to the CYUSB3014 chip.

(6) The components with larger current are placed near the power supply and far away from the connector as far as possible, so that the large-current backflow path is reduced, and the purpose of reducing electromagnetic radiation is achieved.

The number of layers of the circuit board and the reasonable layout of the components are designed.

The utility model discloses compare with traditional mode: (1) can be used for replacing the traditional ISA bus machine tool motion control system. (2) The motion control system has no special requirements on a computer interface, the debugging and the installation of the motion control system (a motion control card) can be realized by a common notebook computer, and the USB communication interface is used, so that the motion control system has stronger universality, adaptability and convenience and has wider application range. (3) The USB interface supports hot plug, plug and play, the expansion interface is easy, the plug is convenient, the damage is not easy, the stability of data exchange between the motion control system (motion control card) and the PC is ensured, the accurate motion control of the motion control system (motion control card) to the machine tool is further ensured, and the processing precision of the machine tool is improved. (4) The use of the USB3.0 communication standard improves the data exchange rate between a control system taking a DSP chip as a core and a PC, reduces the time of single data exchange, and compared with other communication modes, under the same motion control requirement, the time of processing data by the DSP is increased, the reliability of the data is ensured, and the processing efficiency of the machine tool is improved. And can completely replace the existing motion control system (motion control card) of USB2.0 communication. (5) The use of the DSP chip enables the motion control system (motion control card) to have high software flexibility, be suitable for conditional processing, be capable of executing complex multi-algorithm tasks, be capable of programming through assembly or high-level languages (such as C language), realize the scheme in real time, enable the software updating speed to be faster, and greatly improve the reliability, the universality and the replaceability of the system.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (4)

1. A motion control card based on DSP is characterized by comprising a DSP control circuit connected with a USB control circuit and a PC, wherein the USB control circuit is connected with the PC through a USB interface;

the USB control circuit comprises a power supply circuit, a USB interface circuit of the USB control circuit, a JTAG circuit of the USB control circuit, an I2C circuit of the USB control circuit, a reset circuit of the USB control circuit and a clock circuit of the USB control circuit;

the + port of the port DC1 of the power supply circuit is connected with one end of a single-pole double-throw switch K3, the other end of the single-pole double-throw switch is connected with the input of D5V, and the other port of the port DC1 is grounded;

an input end of a D5V is connected with an EN2 port of a chip RT8012A, one end of a resistor R4, one end of a capacitor C2, a PVDD2 port, a VDD port and a PVDD1 port of the chip RT8012A, one end of a capacitor C3, one end of a resistor R6, an EN port of the chip RT8012A, the other end of a resistor R4 is connected with a PGOOD2 port of the chip RT8012A, the capacitor C2 is grounded, the capacitor C3 is grounded, the other end of a resistor R6 is connected with a PGOOD1 port, an input end of the chip RT 80172 is connected with one end of an inductor L1, one end of a capacitor C1, one end of a resistor R1 is grounded, the other end of the inductor L1 is connected with an LX1 port of the chip RT8012 1, the other end of the capacitor C1 is grounded, the other end of the resistor R1 is connected with a ground, the other end of the resistor R1 is connected with a GND port of the chip RT8012 1, the other end of the resistor R1, the resistor R1 is connected with a GND port and the other end of the resistor R1, the resistor;

U3.3V input is connected with one end of R17, the other end of R17 is connected with the positive pole of the photosensitive diode LED2, the negative pole of the photosensitive diode is grounded;

the input of the D5V is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the anode of a photosensitive diode LED1, and the cathode of the photosensitive diode is grounded;

the input of D5V is connected with the EN2 port of chip RT8012A, one end of resistor R5, one end of capacitor C4, the PVDD2 port, the VDD port, the PVDD1 port of chip RT8012A, one end of capacitor C5, one end of resistor R7, the EN port of chip RT8012A, the other end of resistor R5 is connected with the other end of PGOOD2 of chip RT8012A, the other end of capacitor C4 is grounded, the other end of capacitor C5 is grounded, the input of D1.9V is connected with one end of inductor L2, one end of a capacitor C9 and one end of a resistor R11 are connected, the other end of an inductor L2 is connected with an LX2 port of a chip RT8012A, the other end of the capacitor C9 is grounded, the other end of the resistor R11 is connected with one end of a resistor R15, the port of an FB2 of the chip RT8012A, the other end of the resistor R15 is grounded, the GND port and the PGND port of the chip RT8012A are connected with the ground, D3.3V is connected with one end of a reactor L4, one end of a capacitor C10 and one end of a resistor R9, the other end of a reactor L4 is connected with the port of an RT8012ALX1, the other end of a capacitor C10 is grounded, the other end of a resistor R9;

D3.3V is connected with one end of a resistor R18, the other end of the resistor R18 is connected with the anode of a photosensitive diode LED3, and the cathode of the photosensitive diode LED3 is grounded;

the SSTX + port of the USB female seat is connected with a TX + port and an IO1 port of CH412K, the SSTX-port of the USB female seat is connected with a TX-port, an IO3 port of CH412K, GND of the USB female seat is grounded, connected with a GND port of CH412K and connected with one end of a capacitor C6, the SSRX + port of the USB female seat is connected with an IO2 port of CH412K, the SSRX-port of the USB female seat is connected with an IO3 port of CH412K, VBUS of the USB female seat is connected with a VCC port of CH412K and the other end of the capacitor C6;

the input of a JTAG circuit of the USB control circuit is connected with one end of a capacitor C11, the input of an U3.3V port of the JTAG download port is connected with a DVCC port of a JTAG download port, the other end of the capacitor C11 is connected with GND, a TMS port is connected with TMS1, a TD1 port is connected with TDII, a TDO port is connected with TDO11, a TCK port is connected with TCK1, a TRS port is connected with TRST #, and a DGND port is;

an I2C circuit of a USB control circuit, wherein an NC port, an A2 port and a GND port of an AT24C08 in the I2C circuit are connected with the ground, the input of U3.3V is connected with one end of a capacitor C1, one end of VCC, one end of a resistor R2 and one end of a resistor R3, the other end of C1 is connected with the ground, the other end of the resistor R2 is connected with an SCL port of the AT24C08, the other end of the resistor R3 is connected with an SDA port of the AT24C08, and a WP port is connected with;

the RESET # of the RESET circuit of the USB control circuit is connected with one end of a resistor R16, one end of a key K1, one end of a capacitor C12, the other end of the resistor R16 is connected with U3.3V, the other end of the key K1 is grounded, and the other end of the capacitor C12 is grounded;

U3.3V of a clock circuit of the USB control circuit is connected with one end of a magnetic bead L5, the other end of the magnetic bead L5 is connected with a VDD port of a crystal oscillator and one end of a capacitor C13, the other end of the capacitor C13 is grounded and connected with a GND port of the crystal oscillator, an OUT port of the crystal oscillator is connected with one end of a resistor R19, and the other end of the resistor R19 is connected with a CLKIN;

the DSP control circuit comprises a reset circuit of the DSP control circuit, a JTAG circuit of the DSP control circuit, a clock circuit of the DSP control circuit and an E2ROM circuit of the DSP control circuit;

in the reset circuit of the DSP control circuit, the MR port of the chip MAX708 is connected with one end of a switch K2, the other end of the switch K2 is grounded, the D3.3V input is connected with the VCC port of the chip MAX708 and one end of a capacitor C36, the other end of the capacitor C36 is connected with the GND port of the chip MAX708 and the PFI of the chip MAX708, and is grounded, the RST port of the chip MAX708 is connected with one end of a resistor R40, and the other end of a resistor R40 is connected with;

the JTAG circuit of the DSP control circuit, DVCC port of JTAG download interface connects D3.3V input end, one end of electric capacity C37, another end of electric capacity C37 is earthed, TCK port connects TCK, EMUO port connects one end of resistance R44, another termination D3.3V of resistance R44 inputs, one end of resistance R45, another termination EMUI port of resistance R45, DGND port connects in parallel and earthed, TRST port connects one end of resistance R43, another end of resistance R43 is earthed;

the E2ROM circuit of the DSP control circuit, the NC port, the A2 port and the GND port of the AT24C08 chip are grounded, the D3.3V input is connected with one end of a capacitor C35 and the VCC port of the AT24C08, one end of a resistor R41 and one end of a resistor R42, the other end of the capacitor C35 is grounded, the other end of the resistor R41 is connected with the SCL port of the AT24C08, and the other end of the resistor R42 is connected with the SDA port of the AT24C 08;

in the clock circuit of the DSP control circuit, an OUT port of a T30MHz crystal oscillator is connected with X1, a GND port is connected with one end of a capacitor C38 and is grounded, and a VDD port is connected with a D3.3V input and the other end of a capacitor C38.

2. The DSP-based motion control card of claim 1 wherein the DSP control circuitry further comprises peripheral RAM, the peripheral RAM chip IS61LV25616AL, the peripheral FLASH IS SST39VF 800A.

3. A DSP based motion control card according to claim 1 wherein the DSP control circuitry is a TMS320F2812 chip.

4. A DSP based motion control card as claimed in claim 1 wherein the USB control circuitry uses a CYUSB3014 chip.

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