CN213069073U - Avalanche diode's testing arrangement - Google Patents
Avalanche diode's testing arrangement Download PDFInfo
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- CN213069073U CN213069073U CN202022038753.5U CN202022038753U CN213069073U CN 213069073 U CN213069073 U CN 213069073U CN 202022038753 U CN202022038753 U CN 202022038753U CN 213069073 U CN213069073 U CN 213069073U
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Abstract
The utility model discloses a testing arrangement of avalanche diode, a serial communication port, including signal processing circuit, picosecond light pulse produces the module, the optical attenuation module, control circuit, and be used for installing the test fixture who is surveyed the APD, signal processing circuit's light pulse trigger signal output end connects the input that picosecond light pulse produced the module, the installation on the test fixture is connected to signal processing circuit's gate signal output end is surveyed the APD, the input of optical attenuation module is connected to the output that picosecond light pulse produced the module, the installation on the test fixture is connected to the output of optical attenuation module is surveyed the APD. The utility model has the advantages that: the testing device solves the problem of too many testing devices, and can realize the independent performance test of the APD only by using one PCB board to match with a testing tool.
Description
Technical Field
The utility model belongs to the technical field of quantum communication technique and specifically relates to testing arrangement to avalanche diode (APD).
Background
The single photon detection technology is one of core technologies in the field of quantum secure communication. Currently, single photon detectors in the field of quantum secure communications are mainly based on avalanche diodes (APDs) of InGaAs/InP materials as their detection elements. In order to ensure the security of the key generated in the quantum key distribution process, matching requirements are provided for the detection efficiency, the dark counting rate, the post-pulse probability and other performances of the APD, and detectors with different performances need APDs of different levels. The APD component is used as a key device of a high-speed photoelectric system, index parameters of the APD component, such as working voltage, detection efficiency, back pulse, dark count and other performance parameters, can affect the performance of the detector, so that the performance test of the APD component is particularly important, the grade of the APD can be further distinguished through the test of the APD, and the APDs with different performances are suitable for different detector equipment.
In the prior art, the patent with application number 201510272222.3 discloses a testing device and a testing method for a single photon detector, and the testing method is that parameter issuing, numerical calculation and statistics in the test are realized through upper computer software; the main control circuit outputs a light source trigger driving signal to the narrow pulse light source, the narrow pulse light source emits light and then generates a single photon horizontal signal through the optical attenuator for testing, meanwhile, a gate control trigger signal in the main control circuit drives the narrow pulse light source to be sent to the single photon detector module, delay adjustment is achieved in the main control circuit (testing tool), counting output by the single photon detector module is sent to the main control circuit to perform data processing, and then counting indexes such as detection efficiency, dark counting probability, rear pulse probability, effective gate width and the like of the single photon detector module are obtained. The test method has the problem of more test equipment, and the test efficiency is lower because only one APD can be tested at one time. And the testing device is limited to the testing of non-integrated APDs.
The patent with application number 201920734226.2 discloses a testing device for a single photon detector, which comprises a testing circuit, wherein the testing circuit comprises a controller, a clock module, a time position measuring module, a light source module, a light attenuation module and a light splitter module. The test method comprises the following steps: a controller in the testing device receives instructions of a man-machine exchange device and outputs driving signals to a narrow pulse adjusting circuit to drive a DFB laser to emit light, and the light is adjusted to reach a single photon level through a VOA attenuation circuit and a rear-stage optical attenuator; the controller outputs synchronous clock signals to a main control module of the single photon detector device through the output comparator and the clock driver to carry out frequency multiplication output, the synchronous clock signals are processed in the main control module of the single photon detector device to obtain gating signals and are sent to the single photon APD tube, meanwhile, the main control module of the single photon detector device is controlled through the man-machine exchange device to start a parameter calibration process, the single photon detector device outputs counting pulse signals to the test circuit, the two paths of clock signals are output by the 1:2 clock driver to be respectively sent to the time position measurement unit and the controller to complete counting statistics, and the detection efficiency, the dark counting probability, the rear pulse probability and the effective gate width of the single photon detector device can be calibrated through the method. Although debugging equipment is reduced, the device can only be used for testing single photon detector equipment with an APD installed, belongs to module-level testing, and is not used for testing the independent performance of a key device APD of the detector, namely, the testing device cannot perform batch performance testing when avalanche diodes enter a factory, if the performance (dark count, back pulse, detection efficiency and the like) of the APD is not tested when the APD enters the factory, the avalanche diodes cannot be classified in grades, and the APDs with different performances cannot be used for different detectors.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve lies in how to use less test equipment to accomplish the problem of the independent capability test of APD.
The utility model discloses a following technical means realizes solving above-mentioned technical problem: a testing device for an avalanche diode comprises a signal processing circuit, a picosecond optical pulse generation module, an optical attenuation module, a control circuit and a testing tool for mounting a tested APD, wherein an optical pulse trigger signal output end of the signal processing circuit is connected with an input end of the picosecond optical pulse generation module, a gate control signal output end of the signal processing circuit is connected with the tested APD mounted on the testing tool, an output end of the picosecond optical pulse generation module is connected with an input end of the optical attenuation module, an output end of the optical attenuation module is connected with the tested APD, and the signal processing circuit, the picosecond optical pulse generation module, the optical attenuation module and the control circuit are integrated on a PCB.
The testing device solves the problem of too many testing devices, and can realize the independent performance test of the APD only by using one PCB board to match with a testing tool.
As an optimized technical scheme, the signal processing circuit comprises an FPGA, an optical pulse trigger signal circuit, a gate control signal forming circuit, a coincidence gate signal forming circuit, an avalanche signal screening and coincidence circuit and an avalanche signal shaping circuit, the FPGA is respectively connected with the optical pulse trigger signal circuit, the gate control signal forming circuit, the coincidence gate signal forming circuit and the avalanche signal shaping circuit, the output end of the optical pulse trigger signal circuit is connected with the picosecond optical pulse generating module, the output end of the gate control signal forming circuit is connected with a detected APD, and the coincidence gate signal forming circuit is connected with the FPGA through the avalanche signal screening and coincidence circuit and the avalanche signal shaping circuit.
As a further optimized technical scheme, the signal processing circuit further comprises a delay circuit and a clock buffer circuit, and the FPGA is respectively connected with a gate control signal forming circuit and a coincidence gate signal forming circuit after sequentially passing through the delay circuit and the clock buffer circuit.
As an optimized technical scheme, the picosecond light pulse generation module comprises a trigger signal discrimination circuit, a delay coincidence circuit, a laser driving circuit, an FPGA, a bias current control circuit, a laser state acquisition circuit, a laser and a TEC control circuit. The FPGA is respectively connected with the bias current control circuit, the laser state acquisition circuit and the TEC control circuit, the input end of the trigger signal discrimination circuit is connected with the output end of the signal processing circuit, the output end of the trigger signal discrimination circuit is connected with the laser driving circuit through the delay coincidence circuit, the laser driving circuit is connected with the laser, the laser is respectively connected with the bias current control circuit, the laser state acquisition circuit and the TEC control circuit, and the output end of the laser is connected with the light attenuation module.
As an optimized technical scheme, the light attenuation module comprises an MCU, a DAC and a VOA, the MCU is sequentially connected with the DAC and the VOA, the input end of the VOA is connected with the laser output end of the picosecond light pulse generation module, and the output end of the VOA is connected with the APD to be tested.
As an optimized technical scheme, the control circuit mainly comprises an FPGA, a refrigeration driving circuit, a temperature acquisition circuit, a bias voltage control circuit and a bias current acquisition circuit, wherein the FPGA is respectively connected with the refrigeration driving circuit, the temperature acquisition circuit, the bias voltage control circuit and the bias current acquisition circuit, the bias current acquisition circuit is connected with the bias voltage control circuit, and the refrigeration driving circuit, the temperature acquisition circuit and the bias voltage control circuit are connected with a detected APD.
As a further optimized technical scheme, the APD to be tested is attached to the test board through a conductive adhesive.
As a further optimized technical scheme, the APD to be tested is installed on a test tool, and the test tool is arranged on a test board.
As a further optimized technical scheme, the APD to be tested is installed on a test tool, the test tool is an external tool, the test tool comprises a PCB supporting tool and a packaging connector, the PCB supporting tool is fixed on a substrate, a test board is fixedly installed in a plurality of grooves formed in the PCB supporting tool, the packaging connector is fixed on the test board, and the APD to be tested is inserted into the packaging connector.
As a further optimized technical scheme, a multi-channel switching device is arranged between the signal processing circuit, the control circuit, the optical attenuation module and the test fixture, one end of the multi-channel switching device is connected with signal input or output ports of the signal processing circuit, the control circuit and the optical attenuation module, the other end of the multi-channel switching device is connected with a plurality of APDs to be tested, which are installed on the test fixture, and the upper computer is connected with the multi-channel switching device through the PCB.
The utility model has the advantages that:
1. the testing device solves the problem of too many testing devices, and can realize the independent performance test of the APD only by using one PCB board to match with a testing tool;
2. the coincidence gate signal forming circuit can generate positive and negative coincidence gates according to configuration, double coincidence gates are adopted for counting, a pseudo-random number generator is not needed, and the test accuracy and the APD batch test requirements are both considered;
3. the testing device is compatible with an integrated refrigeration type APD test and a non-integrated refrigeration type APD test, and provides convenience for the factory test of two APDs in the future;
4. the test fixture of the test device can support a plurality of APDs to be installed, batch tests can be completed by matching with the upper computer, the test efficiency is greatly improved, and the manual input is reduced.
Drawings
Fig. 1 is a schematic connection diagram of a testing apparatus for avalanche diodes according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a test fixture for integrated refrigeration APDs;
fig. 3 is a schematic structural diagram of a test fixture for a non-integrated refrigeration APD.
Detailed Description
To make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are combined to clearly and completely describe the technical solution in the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1, the testing apparatus for avalanche diode of the present invention includes a signal processing circuit, a picosecond light pulse generating module, a light attenuation module, a control circuit, and a testing fixture for mounting an APD to be tested.
The optical pulse trigger signal output end of the signal processing circuit is connected with the input end of the picosecond optical pulse generation module, the gate control signal output end of the signal processing circuit is connected with a tested APD installed on the testing tool, the output end of the picosecond optical pulse generation module is connected with the input end of the optical attenuation module, and the output end of the optical attenuation module is connected with the tested APD installed on the testing tool. The picosecond optical pulse generating module receives an optical pulse trigger signal output by the signal processing circuit, a laser driving circuit in the picosecond optical pulse generating module forms a narrow pulse and drives a laser to generate a picosecond-magnitude optical pulse, the optical attenuation module attenuates the optical pulse output by the picosecond optical pulse generating module to a single photon magnitude, a single photon magnitude optical pulse signal is output to an APD to be detected, and a gating signal generated by the signal processing circuit is output to the APD to be detected. The signal processing circuit, the picosecond light pulse generation module, the light attenuation module and the control circuit can be integrated on a PCB.
The signal processing circuit comprises an FPGA, an optical pulse trigger signal circuit, a delay circuit, a clock buffer circuit, a gating signal forming circuit, a coincidence gate signal forming circuit, an avalanche signal discrimination and coincidence circuit and an avalanche signal shaping circuit, wherein the FPGA is respectively connected with the optical pulse trigger signal circuit, the delay circuit and the avalanche signal shaping circuit, the output end of the optical pulse trigger signal circuit is connected to a picosecond optical pulse generating module, the output end of the delay circuit is connected with the input end of the clock buffer circuit, the output end of the clock buffer circuit is respectively connected with the gating signal forming circuit and the coincidence gate signal forming circuit, the output end of the gating signal forming circuit is connected with a detected APD, and the coincidence gate signal forming circuit is connected with the FPGA through the avalanche signal discrimination and coincidence circuit and the avalanche signal shaping circuit. The avalanche signal screening and coincidence circuit is used for screening signals output by avalanche diodes with voltages higher than the screening voltage, and then the screened signals are input to the FPGA for counting after being shaped by the avalanche signal shaping circuit. Specifically, the avalanche signal discrimination and coincidence circuit receives an avalanche signal generated by the APD to be detected, the avalanche signal is separated from a noise signal by setting an avalanche signal discrimination threshold, and the pulse is widened and amplified in amplitude by the avalanche signal shaping circuit and is converted into a counting pulse which accords with the FPGA counting standard. The coincidence gate signal forming circuit adjusts the delay and the width of the coincidence gate signals, so that the coincidence gate signal width is larger than the width of the pulse signals received by the avalanche signal screening and coincidence circuit, and positive and negative coincidence gates are generated according to configuration so as to respectively test coincidence counting at different delay positions.
The picosecond optical pulse generation module comprises a trigger signal discrimination circuit, a delay coincidence circuit, a laser driving circuit, an FPGA, a bias current control circuit, a laser state acquisition circuit, a laser and a TEC control circuit. The FPGA is respectively connected with the bias current control circuit, the laser state acquisition circuit and the TEC control circuit, the input end of the trigger signal discrimination circuit is connected with the output end of the signal processing circuit, the output end of the trigger signal discrimination circuit is connected with the laser driving circuit through the delay coincidence circuit, the laser driving circuit is connected with the laser, the laser is respectively connected with the bias current control circuit, the laser state acquisition circuit and the TEC control circuit, and the output end of the laser is connected with the light attenuation module. The trigger signal discrimination circuit is used for discriminating an input signal, shaping the input signal, inputting the shaped signal into the laser driving circuit through the time delay coincidence circuit, and outputting the signal to the laser through the laser driving circuit to drive the laser to emit light. The bias current control circuit mainly controls the bias current of the laser through the voltage-controlled current source to adjust the light emission of the laser. The TEC control circuit provides a TEC drive current to a TEC (thermo electric cooler) at the laser. The laser state acquisition circuit realizes acquisition of the laser temperature, the laser light intensity, the temperature on the PCB and the TEC driving current.
The light attenuation module comprises an MCU (central processing unit), a DAC (digital-to-analog converter) and a VOA (variable optical attenuator), the MCU is sequentially connected with the DAC and the VOA, the input end of the VOA is connected with the laser output end of the picosecond light pulse generation module, and the output end of the VOA is connected with the APD to be detected. The DAC device is controlled by the MCU to realize the control of VOA and further realize the control of attenuation, calibration coefficients of all VOAs are stored in the MCU, and accurate attenuation control is realized by looking up a table.
The control circuit mainly comprises an FPGA, a refrigeration driving circuit, a temperature acquisition circuit, a bias voltage control circuit and a bias current acquisition circuit, wherein the FPGA is respectively connected with the refrigeration driving circuit, the temperature acquisition circuit, the bias voltage control circuit and the bias current acquisition circuit, the bias current acquisition circuit is connected with the bias voltage control circuit, and the refrigeration driving circuit, the temperature acquisition circuit and the bias voltage control circuit are connected with a tested APD. The refrigeration driving circuit provides TEC refrigeration driving current for the APD to be tested, the refrigeration driving circuit mainly provides refrigeration for the integrated refrigeration type APD, and the non-integrated refrigeration type APD tool is placed in the incubator for temperature control. The temperature acquisition circuit is used for acquiring the temperature of the APD to be detected and transmitting an acquired temperature signal to the FPGA so as to control the temperature of the avalanche diode to be detected. The integrated refrigeration APD internally comprises a temperature acquisition resistor, the temperature of the APD can be acquired, and the non-integrated refrigeration APD is not required to be acquired because the temperature control is controlled by the incubator in the incubator, but the hardware of the device also supports temperature acquisition. The bias voltage control circuit is used for generating bias voltage required by APD avalanche to be tested and comprises a bias voltage generation chip with a bias current acquisition function; the bias current acquisition circuit acquires the real-time bias current value of the APD to be tested, and the I-V curve test of the APD to be tested can be realized by combining the bias voltage control circuit and the bias current acquisition circuit.
It should be noted that, the FPGAs in the signal processing circuit, the picosecond light pulse generating module, and the control circuit may be the same FPGA chip on the PCB or multiple FPGA chips arranged as needed, which is not limited in this application.
Test fixture, different test object adopts different test fixture, integrated refrigeration type APD's test fixture is on surveying the board, non-integrated refrigeration type APD's test fixture is external frock, because this testing arrangement only is used for the factory of income of avalanche diode to detect, can not damage to the pin to some extent, do not damage the device pin for the convenience dismouting, as shown in fig. 2, integrated refrigeration type APD10 sets up in the mounting hole that survey board 20 was seted up, adopt the fixed integrated refrigeration type APD10 of current test fixture, or also can adopt the electric conductivity colloid to paste integrated refrigeration APD type 10 in surveying board 20 and test. As shown in fig. 3, a test fixture structure of non-integrated refrigeration APD40 is provided, in which a non-integrated refrigeration APD40 is fixed on a test board 31 through an external test fixture, the test fixture includes a PCB support fixture 30 and a package connector 32, the PCB support fixture 30 is fixed on a substrate, the test board 31 is fixedly mounted in a plurality of grooves formed on the PCB support fixture 30, the package connector 32 is fixed on the test board 31, the non-integrated refrigeration APD40 is inserted on the package connector 32, and the test board 31 is not required to be welded or can be optimized, the non-integrated refrigeration APD40 directly passes through the test board 31, and the non-integrated refrigeration APD40 is connected with the test board 31 through a conductive adhesive without welding. After the test is finished, the tested non-integrated refrigeration APD40 can be taken down. The two test tools support simultaneous testing of multiple channels. Of course, the two test fixtures are only examples, and any existing fixture capable of fixing the APD may be used to fix the APD to be tested.
When the testing device has the function of multi-channel testing, a multi-channel switching device is required to be arranged between the signal processing circuit, the control circuit, the optical attenuation module and the testing tool, one end of the multi-channel switching device is connected with signal input or output ports of the signal processing circuit, the control circuit and the optical attenuation module, the other end of the multi-channel switching device is connected with a plurality of APDs to be tested, the APDs to be tested are mounted on the testing tool, the upper computer controls the multi-channel switching device through an FPGA on a PCB, the signal processing circuit, the control circuit and the optical attenuation module are connected with one or more of the APDs to be tested, batch testing can be completed through the arrangement of the upper computer, testing efficiency is greatly improved.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.
Claims (10)
1. The testing device for the avalanche diode is characterized by comprising a signal processing circuit, a picosecond optical pulse generating module, an optical attenuation module, a control circuit and a testing tool for mounting a tested APD, wherein an optical pulse trigger signal output end of the signal processing circuit is connected with an input end of the picosecond optical pulse generating module, a gate control signal output end of the signal processing circuit is connected with the tested APD mounted on the testing tool, an output end of the picosecond optical pulse generating module is connected with an input end of the optical attenuation module, an output end of the optical attenuation module is connected with the tested APD, and the signal processing circuit, the picosecond optical pulse generating module, the optical attenuation module and the control circuit are integrated on a PCB.
2. The avalanche diode testing device according to claim 1, wherein the signal processing circuit includes an FPGA, a light pulse trigger signal circuit, a gate control signal forming circuit, a coincidence gate signal forming circuit, an avalanche signal screening and coincidence circuit, and an avalanche signal shaping circuit, the FPGA is connected to the light pulse trigger signal circuit, the gate control signal forming circuit, the coincidence gate signal forming circuit, and the avalanche signal shaping circuit, respectively, an output of the light pulse trigger signal circuit is connected to the picosecond light pulse generating module, an output of the gate control signal forming circuit is connected to the APD under test, and the coincidence gate signal forming circuit is connected to the FPGA through the avalanche signal screening and coincidence circuit and the avalanche signal shaping circuit.
3. The apparatus as claimed in claim 2, wherein the signal processing circuit further comprises a delay circuit and a clock buffer circuit, and the FPGA is connected to the gate signal forming circuit and the coincidence gate signal forming circuit after passing through the delay circuit and the clock buffer circuit in sequence.
4. The avalanche diode testing device according to claim 1, wherein the picosecond light pulse generating module comprises a trigger signal discrimination circuit, a delay coincidence circuit, a laser driving circuit, an FPGA, a bias current control circuit, a laser state acquisition circuit, a laser and a TEC control circuit, the FPGA is connected to the bias current control circuit, the laser state acquisition circuit and the TEC control circuit, the input end of the trigger signal discrimination circuit is connected to the output end of the signal processing circuit, the output end of the trigger signal discrimination circuit is connected to the laser driving circuit through the delay coincidence circuit, the laser driving circuit is connected to the laser, the laser is connected to the bias current control circuit, the laser state acquisition circuit and the TEC control circuit, and the output end of the laser is connected to the light attenuation module.
5. The avalanche diode testing device according to claim 1, wherein the optical attenuation module comprises an MCU, a DAC and a VOA, the MCU is connected to the DAC and the VOA in sequence, the input terminal of the VOA is connected to the laser output terminal of the picosecond optical pulse generation module, and the output terminal of the VOA is connected to the APD under test.
6. The avalanche diode testing device according to claim 1, wherein the control circuit comprises an FPGA, a refrigeration driving circuit, a temperature acquisition circuit, a bias control circuit, and a bias current acquisition circuit, the FPGA is connected to the refrigeration driving circuit, the temperature acquisition circuit, the bias control circuit, and the bias current acquisition circuit, respectively, the bias current acquisition circuit is connected to the bias control circuit, and the refrigeration driving circuit, the temperature acquisition circuit, and the bias control circuit are connected to the APD under test.
7. The apparatus as claimed in claim 1, wherein the APD under test is attached to the test board by a conductive adhesive.
8. The apparatus as claimed in claim 1, wherein the APD under test is mounted on a test fixture, and the test fixture is disposed on the test board.
9. The device as claimed in claim 1, wherein the APD under test is mounted on a test fixture, the test fixture is an external fixture, the test fixture includes a PCB support fixture and a package connector, the PCB support fixture is fixed on a substrate, the test board is fixedly mounted in a plurality of grooves formed on the PCB support fixture, the package connector is fixed on the test board, and the APD under test is inserted into the package connector.
10. The device for testing avalanche diodes according to claim 1, wherein a multi-channel switching device is disposed between the signal processing circuit, the control circuit, the optical attenuation module and the testing fixture, one end of the multi-channel switching device is connected to signal input or output ports of the signal processing circuit, the control circuit and the optical attenuation module, the other end of the multi-channel switching device is connected to the plurality of APDs to be tested mounted on the testing fixture, and the upper computer is connected to the multi-channel switching device through the PCB.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114062831A (en) * | 2022-01-17 | 2022-02-18 | 国网浙江省电力有限公司金华供电公司 | Fault self-detection method and device suitable for single photon detector |
| WO2023020370A1 (en) * | 2021-08-18 | 2023-02-23 | 国开启科量子技术(北京)有限公司 | Method and apparatus for extracting avalanche signal |
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2020
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023020370A1 (en) * | 2021-08-18 | 2023-02-23 | 国开启科量子技术(北京)有限公司 | Method and apparatus for extracting avalanche signal |
| CN114062831A (en) * | 2022-01-17 | 2022-02-18 | 国网浙江省电力有限公司金华供电公司 | Fault self-detection method and device suitable for single photon detector |
| CN114062831B (en) * | 2022-01-17 | 2022-04-19 | 国网浙江省电力有限公司金华供电公司 | Fault self-detection method and device suitable for single photon detector |
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