CN213041987U

CN213041987U - Ultra-wideband radar signal simulation platform

Info

Publication number: CN213041987U
Application number: CN202020827061.6U
Authority: CN
Inventors: 刘岩
Original assignee: Beijing Huankai Innovation Technology Development Co ltd
Current assignee: Beijing Huankai Innovation Technology Development Co ltd
Priority date: 2020-05-18
Filing date: 2020-05-18
Publication date: 2021-04-23
Anticipated expiration: 2030-05-18

Abstract

The utility model provides an ultra-wideband radar signal simulation platform; the simulation platform comprises a power supply module, a serial communication module, a gigabit network port module, a user-defined I/O module, a core computing unit, an auxiliary computing unit, a storage module, a clock system, a digital-to-analog conversion module, an analog signal conditioning module and an optical port module; the device is developed based on the comparative analysis of ultra-wideband radar signals and the generation technology thereof; the simulation platform solves the problem of phase synchronization of multipath transmission of radar signals based on the theory of signal integrity; meanwhile, the problem of signal integrity is solved by adjusting the phase of the transmitting multipath to simulate radar echo; the utility model discloses can be applied to the actual scene of simulation radar, ensure the reliability of design, shorten the research and development cycle, reduce the research and development cost, can extensively be applicable to in digital system design.

Description

Ultra-wideband radar signal simulation platform

Technical Field

The utility model relates to a digital signal simulation field especially relates to an ultra wide band radar signal simulation platform.

Background

With the development of broadband microwave devices and the enhancement of digital signal processing capability of software algorithms, the performance of ultra-wideband radar has reached a higher level after the 90 s of the 20 th century. The characteristics of high resolution, strong penetrability and the like of the ultra-wideband radar mean that the ultra-wideband radar has the following excellent performances: high distance resolution, high concealment, low interception rate and anti-interference; the signal has the capacity of resisting attenuation when being transmitted by multiple beams; has good electromagnetic compatibility and spectrum utilization compared with narrow-band signals. The distance resolution is proportional to the bandwidth of the transmitted signal, and the bandwidth of the transmitted signal needs to be increased to improve the distance resolution of the radar. The development of ultra-wideband radar signal sources becomes the key to the development of high-resolution radar systems. With the increase of signal bandwidth, the problems of signal integrity of high-speed digital circuits are highlighted, and the development of radar signal sources becomes more difficult. Therefore, the research on the signal integrity of the high-speed digital circuit and the development of the ultra-wideband radar signal source have important significance for the development of high-resolution radars.

SUMMERY OF THE UTILITY MODEL

In order to solve the defects of the prior art, the utility model aims to provide an ultra wide band radar signal simulation platform to satisfy electronic circuit's development trend.

In order to achieve the above object, the utility model provides an ultra wide band radar signal simulation platform; the simulation platform comprises a power supply module, a serial communication module, a gigabit network port module, a user-defined I/O module, a core computing unit, an auxiliary computing unit, a storage module, a clock system, a digital-to-analog conversion module, an analog signal conditioning module and an optical port module; the power supply module is electrically connected with the core computing unit, the auxiliary computing unit, the storage module and the digital-to-analog conversion module and is used for supplying power to the system; the serial port communication module is in communication connection with the core computing unit and the auxiliary computing unit and is used for providing low-speed data communication and facilitating debugging; the gigabit network port module is in communication connection with the core computing unit, is used for network communication, receives an instruction sent by an upper computer and uploads a working state; the user-defined I/O module is in communication connection with the auxiliary computing unit and is used for providing user-defined I/O and flexibly expanding functions; the core computing unit and the auxiliary computing unit are communicated and interconnected to be EMIF, SRIOx4 and PCIEx 4; the core computing unit is used for forming the core computing power of a radar analog signal generating algorithm, and the auxiliary computing unit is used for synthesizing and sending out the generated radar analog signals; the storage module is in communication connection with the core computing unit and is used for caching core computing data; the clock system is in communication connection with the auxiliary computing unit and is used for providing clock signals for system work; the digital-to-analog conversion module is in communication connection with the auxiliary computing unit and is used for completing conversion from digital signals to analog signals; the analog signal conditioning module is in communication connection with the digital-to-analog conversion module and is used for improving the signal integrity of the production analog signal; the optical port module is in communication connection with the auxiliary computing unit and is used for providing an optical port and realizing high-speed data exchange with the outside.

Preferably, the power supply module consists of 6 energy storage power supply sub-modules, the input voltage is 8-12V, and the power consumption is 45-50W.

Preferably, the core computing unit comprises a DSP1, a DSP2, a PHY1, a PHY2, a NAND Flash1 and a NAND Flash 2; the DSP1 and the DSP2 are interconnected through Hyper Link 5 Gbps; the PHY1 is communicatively connected to the DSP1, and is configured to receive signals from the gigabit network port module and transmit the signals to the DSP 1; the PHY2 is communicatively connected to the DSP2, and is configured to receive signals from the gigabit network port module and transmit the signals to the DSP 2; the NAND Flash1 is in communication connection with the DSP1 and is used for setting the FLASH of the DSP1 to be in a NAND mode; the NAND Flash2 is in communication connection with the DSP2, and is configured to set the Flash of the DSP2 to a NAND mode.

Preferably, the memory module comprises 10 DDR3 memory granules and supports the ECC check function; and 5 DDR3 memory granules are in communication connection with the DSP1, and 5 DDR3 memory granules are in communication connection with the DSP 2.

Preferably, the auxiliary computing unit comprises an FPGA and an SPI Flash; and the SPI Flash is in communication connection with the FPGA and used for setting the FLASH of the FPGA to be in an SPI mode.

Preferably, the digital-to-analog conversion module comprises 4 analog-to-digital conversion chips DAC connected in parallel, the sampling rate of each channel is 1250M, and the chips adopt AD9129 chips.

Preferably, the analog signal conditioning module comprises 4 conditioning circuits connected in parallel.

Preferably, the optical port module comprises 8 optical ports connected in parallel, and the capacity is 10G.

Compared with the prior art, the beneficial effects of the utility model are embodied in:

(1) the utility model discloses based on the theory of signal integrality, the phase synchronization problem of radar signal multipath transmission has been solved to and the multipath problem of simulation radar echo.

(2) The utility model discloses can solve the problem of signal integrality, simulation radar practical application scene.

(3) The utility model discloses ensured the reliability of design, shortened the research and development cycle, reduced the research and development cost, can extensively be applicable to in digital system design.

Drawings

Fig. 1 is a schematic structural diagram of an ultra-wideband radar signal simulation platform according to the present invention;

fig. 2 is a schematic view of the loading manner of the DSP1 and DPS2 according to the present invention;

fig. 3 is a design diagram of the DDR3 interface of the DSP1 and DPS2 according to the present invention;

fig. 4 is a DAC design diagram of the digital-to-analog conversion module of the present invention;

fig. 5 is a schematic diagram of the communication interconnection between the core computing unit and the auxiliary computing unit according to the present invention.

Detailed Description

In order to further understand the structure, characteristics and other objects of the present invention, the following detailed description is given with reference to the accompanying preferred embodiments, which are only used to illustrate the technical solution of the present invention and are not intended to limit the present invention.

Firstly, as shown in fig. 1, fig. 1 is a schematic structural diagram of an ultra-wideband radar signal simulation platform according to the present invention; the simulation platform comprises a power supply module 1, a serial communication module 2, a gigabit network port module 3, a user-defined I/O module 4, a core computing unit 5, an auxiliary computing unit 6, a storage module 7, a clock system 8, a digital-to-analog conversion module 9, an analog signal conditioning module 10 and an optical port module 11; the power supply module 1 is electrically connected with the core computing unit 5, the auxiliary computing unit 6, the storage module 7 and the digital-to-analog conversion module 9 and is used for supplying power to a system, the input voltage is 8-12V, and the power consumption is 45-50W; the core computing unit 5 comprises a DSP1, a DSP2, a PHY1, a PHY2, a NAND Flash1 and a NAND Flash 2; the DSP1 and the DSP2 adopt TI DSP TMS320C 6678; the DSP1 and the DSP2 are externally connected with the gigabit network port module 3 and the storage module 7; the auxiliary computing unit 6 comprises an FPGA and an SPI Flash; the FPGA chip adopts a XILINX FPGA XC72K325T FFG 900-2I; the FPGA is externally connected with the serial port communication module 2, the user defined I/O module 4, the digital-to-analog conversion module 9 and the optical port module 11; FPGA FLASH is in SPI mode; the digital-to-analog conversion module 9 comprises 4 analog-to-digital conversion chips DAC which are connected in parallel, the sampling rate of each channel is 1250M, and the chips adopt AD9129 chips; the optical port module 11 comprises 8 optical ports connected in parallel, and the capacity is 10G; the DSP1 and the FPGA are interconnected as EMIF, SRIOx4 and PCIEx 4.

Further, please refer to fig. 2, fig. 2 is a schematic view illustrating a loading manner of the DSP1 and DPS2 according to the present invention; the DSP1 and the DSP2 adopt TI DSP TMS320C 6678; TMS320CC6678 is a new generation DSP chip developed by TI, and the capacity of the kernel, the peripheral interface and the internal interconnection of the TMS320CC6678 is greatly improved compared with the capacity of DSP of C64x series. First, it has eight processor cores C66x, and the C66x core has both a fixed point of 320GMAC and a floating point processing capability of 160 GFLOP. Then, the peripheral integrates high-speed interfaces of SRIO2.1, PCIe2.0, HyperLink and the like of a new generation. In addition, the internal interconnection also adopts a new TeraNet switch interconnection technology, and has very high speed.

The global control pin of the DSP is a configuration circuit of the DSP1 and the DSP2, and is used for initialization setting and state control of the DSP, such as loading mode setting and the like. The configuration pin level of C6678 is 1.8V LVCMOS. When the DSP is in power-on reset, the working mode of the DSP can be set according to the state of the configuration pins. C6678 supports various loading modes, which are set by BOOTMODE [12:0], wherein BOOTMODE [2:0] is used to select the boot device, BOOTMODE [9:3] is used to set the selected boot device, BOOTMODE [12:10] is used to set the system phase-locked loop of the DSP, the settings are as shown in the following table, wherein the meaning of BOOTMODE [9:3] is different according to different boot devices. The scheme selects the loading mode of EMIF16, and can flexibly select other loading modes through register configuration.

In addition, please refer to fig. 3, fig. 3 is a design diagram of the DDR3 interface of the DSP1 and DPS2 according to the present invention; based on a DSP TMS320CC6678, a DDR3 controller in the C6678 is used for DDR3 SDRAM access, the initial address of the DDR3 controller in the C6678 memory map is 0x80000000, and the DDR3 controller is mainly characterized in that: 1) support JESD79-3C DDR3

The SDRAM standard; 2) the data bit width is 64bit/32bit/16 bit; 3) the addressing space is two CEs, maximum 8 GB; 4) the highest rate is DDR 3-1600; 5) CAS Latency is 5, 6, 7, 8, 9, 10, 11; 6) the number of the banks is 1, 2, 4 and 8; 7) the burst length is 8; 8) page sizes 256, 512, 1024, 2048; 9) support for auto-initialization and Self-refresh (Self-refresh); 10) ECC is supported.

The DSP of the single chip of the board card is designed according to the capacity of 512MB, the maximum compatibility is 4GB, the SDRAM must occupy 1 DCE space, the data bit width is designed to 64bit, 4 SDH SDRAMs MT41J128M16JT-125 with 16bit width are selected during design, and the board card supports the ECC mode. For uniform type selection, the chip used for storing ECC data selects the same SDRAMMT41J128M16JT-125, but only uses its lower 8 bits.

In addition, for the FPGA, a main board card chip adopts a Xilinx Kintex-7 FPGA xc7k325t-ffg900-2, and the main board card chip is provided with a PCI Express Endpoint module, a high-speed serial communication interface, a DDR3 memory interface and a user-defined I/O interface. The cache of the FPGA is composed of two DDR3 groups: two MT41K256M16HA-125 are combined to form a 256x32 mode cache; and a 50M single-ended clock is connected to the FPGA as a source clock. In addition, 1 piece of 200M differential clock is needed, and all the clocks are connected to the global clock resource of the FPGA.

In addition, please refer to fig. 4, fig. 4 is a DAC design diagram of the digital-to-analog conversion module according to the present invention; the DAC chip in the digital-to-analog conversion module 9 adopts 4 high-speed analog-to-digital converters AD9129 (14-bit, highest supporting 5.7GSPS (2.85GSPS direct RF synthesis)) of ADI corporation, and has an output impedance of 50 ohms; work at 1.25Gsps, and support up to 2.5 GSPS.

In addition, please refer to fig. 5, fig. 5 is a schematic diagram illustrating the communication interconnection between the core computing unit and the auxiliary computing unit according to the present invention; the DSP1 and the FPGA are interconnected through a high-speed transceiver interface, an SRIO interface protocol is adopted, and the FPGA works in an x4 mode @5GHz, so that high-speed data exchange between the DSP and the FPGA is realized; the DSP1 and the FPGA are connected in an alternating current coupling mode, and a coupling capacitor is close to a receiving end.

In addition, the DPS1 and the DSP2 are interconnected through Hyper Link @5Gbps, so that the high-speed data exchange function between the two core processing units DSP is realized.

Finally, the utility model discloses an ultra wide band radar signal simulation platform, its specific technical characterstic as follows:

It should be noted that the above mentioned embodiments and embodiments are intended to demonstrate the practical application of the technical solution provided by the present invention, and should not be interpreted as limiting the scope of the present invention. Various modifications, equivalent substitutions and improvements will occur to those skilled in the art and are intended to be within the spirit and scope of the present invention. The protection scope of the present invention is subject to the appended claims.

Claims

1. An ultra-wideband radar signal simulation platform is characterized by comprising a power supply module (1), a serial port communication module (2), a gigabit network port module (3), a user-defined I/O module (4), a core computing unit (5), an auxiliary computing unit (6), a storage module (7), a clock system (8), a digital-to-analog conversion module (9), an analog signal conditioning module (10) and an optical port module (11); the power supply module (1) is electrically connected with the core computing unit (5), the auxiliary computing unit (6), the storage module (7) and the digital-to-analog conversion module (9) and is used for supplying power to a system; the serial port communication module (2) is in communication connection with the core computing unit (5) and the auxiliary computing unit (6) and is used for providing low-speed data communication and facilitating debugging; the gigabit network port module (3) is in communication connection with the core computing unit (5) and is used for network communication, receiving an instruction sent by an upper computer and uploading a working state; the user-defined I/O module (4) is in communication connection with the auxiliary computing unit (6) and is used for providing user-defined I/O and flexibly expanding functions; the core computing unit (5) and the auxiliary computing unit (6) are communicated and interconnected to be EMIF, SRIOx4 and PCIEx 4; the core computing unit (5) is used for forming the core computing power of a radar analog signal generation algorithm, and the auxiliary computing unit (6) is used for synthesizing and sending out the generated radar analog signals; the storage module (7) is in communication connection with the core computing unit (5) and is used for caching core computing data; the clock system (8) is in communication connection with the auxiliary computing unit (6) and is used for providing a clock signal for system work; the digital-to-analog conversion module (9) is in communication connection with the auxiliary computing unit (6) and is used for converting a digital signal into an analog signal; the analog signal conditioning module (10) is in communication connection with the digital-to-analog conversion module (9) and is used for improving the signal integrity of the produced analog signals; the optical port module (11) is in communication connection with the auxiliary computing unit (6) and is used for providing an optical port and realizing high-speed data exchange with the outside.

2. The simulation platform of claim 1, wherein the power module (1) consists of 6 energy storage power supply sub-modules, the input voltage is 8-12V, and the power consumption is 45-50W.

3. Simulation platform according to claim 1, characterized in that the core computing unit (5) comprises a DSP1, a DSP2, a PHY1, a PHY2, a NAND Flash1 and a NAND Flash 2; wherein the DSP1 and the DSP2 are interconnected through Hyper Link 5 Gbps; the PHY1 is communicatively connected to the DSP1, and is configured to receive signals from the gigabit network port module and transmit the signals to the DSP 1; the PHY2 is communicatively connected to the DSP2, and is configured to receive signals from the gigabit network port module and transmit the signals to the DSP 2; the NAND Flash1 is in communication connection with the DSP1 and is used for setting the FLASH of the DSP1 to be in a NAND mode; the NAND Flash2 is in communication connection with the DSP2, and is configured to set the Flash of the DSP2 to a NAND mode.

4. The simulation platform according to claim 3, wherein the memory module (7) comprises 10 DDR3 memory granules, which support ECC check function; and 5 DDR3 memory granules are in communication connection with the DSP1, and 5 DDR3 memory granules are in communication connection with the DSP 2.

5. Simulation platform according to claim 1, characterized in that the auxiliary computing unit (6) comprises an FPGA and an SPI Flash; the SPI Flash is in communication connection with the FPGA and used for setting the FLASH of the FPGA to be in an SPI mode.

6. The analog platform according to claim 1, characterized in that the digital-to-analog conversion module (9) comprises 4 analog-to-digital conversion chips DAC connected in parallel, wherein the sampling rate per channel is 1250M, and the chips adopt AD9129 chips.

7. The simulation platform of claim 1, wherein the analog signal conditioning module (10) comprises 4 conditioning circuits (101) in parallel.

8. The simulation platform of claim 1, wherein the optical port module (11) comprises 8 optical ports connected in parallel, and has a capacity of 10G.