CN212848426U

CN212848426U - Solar cell

Info

Publication number: CN212848426U
Application number: CN202021429208.2U
Authority: CN
Inventors: 张俊兵; 刘淑华; 尹海鹏
Original assignee: JA Solar Technology Yangzhou Co Ltd
Current assignee: JA Solar Technology Yangzhou Co Ltd
Priority date: 2020-07-20
Filing date: 2020-07-20
Publication date: 2021-03-30
Anticipated expiration: 2030-07-20

Abstract

The utility model discloses a solar cell belongs to solar cell technical field, and it is higher to have solved solar cell's leakage current among the prior art, leads to the lower scheduling problem of yield of battery. The utility model provides a solar cell, including the silicon substrate, the front of silicon substrate includes the first surface, the first surface is including doping region and undoped region, undoped region distributes in the edge region all around of doping region, the upper surface in doping region is provided with the doping layer. The utility model discloses a solar cell's leakage current is low.

Description

Solar cell

Technical Field

The utility model belongs to the technical field of solar cell, in particular to solar cell.

Background

Human survival and development are not energy-efficient. Solar energy is one of the most advantageous renewable, high volume, clean energy sources. Crystalline silicon solar cells are a type of semiconductor device that directly converts light energy into electrical energy. Efficient photoelectric conversion and lower use cost are human desires for crystalline silicon solar cells. High efficiency solar cells must have good surface passivation, low surface recombination rates, and thus high open circuit voltage, short circuit current, and conversion efficiency. At present, the surface passivation is mainly of a single-layer or multi-layer dielectric film structure such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and the like. However, after the surface passivation is done, metallization is needed, and the passivation film under the printed metal is inevitably damaged, so that the recombination of the metal contact area is relatively large, and the performances of the battery, such as open-circuit voltage, are reduced. The problem is only alleviated to a certain extent but not eliminated by using point contact electrodes or the like.

In recent years, passivated contacts have attracted considerable attention in the field of crystalline silicon solar cells, and more efficient passivated contact solar cells have been developed by various research institutes, mainly by using an ultra-thin oxide layer and growing a doped crystalline silicon thin film on the oxide layer, followed by doping the crystalline silicon thin film. The battery can better realize passivation and reduce recombination brought by metal contact. However, the area of the battery is increasing, the short-circuit current of the high-efficiency battery is increasing, and higher requirements on the electric leakage of the battery are also increasing in order to ensure the reliability of the assembly.

SUMMERY OF THE UTILITY MODEL

In view of the above analysis, the present invention aims to provide a solar cell, which can at least solve one of the following technical problems: (1) the current leakage current of the existing solar cell is high, so that the yield of the cell is low; (2) the reliability of the solar cell module is low.

The purpose of the utility model is mainly realized through the following technical scheme:

the utility model provides a solar cell, including the silicon substrate, the front of silicon substrate includes the first surface, the first surface is including doping region and undoped region, undoped region distributes in the edge region all around of doping region, the upper surface in doping region is provided with the doping layer.

Furthermore, a first composite passivation film is arranged on the upper surfaces of the undoped region and the doped layer, and a front electrode is arranged on the upper surface of the first composite passivation film.

Furthermore, a passivation dielectric layer, a selective carrier transmission layer, a second composite passivation film and a back electrode are sequentially arranged on the back of the silicon substrate along the direction far away from the silicon substrate.

Further, the passivation dielectric layer is a single-layer film or a laminated film of several films of a silicon oxide layer, an aluminum oxide layer, a titanium oxide layer and a silicon oxynitride layer.

Furthermore, the selective carrier transmission layer is a silicon film formed by laminating one or more of a microcrystalline silicon film layer, an amorphous silicon film layer and a polycrystalline silicon film layer.

Furthermore, the thickness of the passivation dielectric layer is 0.1-10.0 nm.

Further, the thickness range of the selective carrier transport layer is 10nm-300 nm.

Further, the thicknesses of the first composite passivation film and the second composite passivation film are both 1-300 nm.

Furthermore, the upper surface of the doped region is a suede surface, and the upper surface of the undoped region is a polished surface.

Further, the conduction type of the doped layer is opposite to or the same as that of the silicon substrate.

Compared with the prior art, the utility model discloses can realize one of following technological effect at least:

(1) the utility model discloses a positive surface of solar cell is along all around sets up the undoped region, and the undoped region has increased the distance between doping layer edge and the back doping layer (being selective carrier transfer layer) edge, ensures that doping layer edge and the back doping layer (being selective carrier transfer layer) edge breaks off completely, can realize lower leakage current, promotes the parallelly connected resistance of battery, can improve the yield of battery piece.

(2) The utility model discloses a solar cell's leakage current is low, consequently adopts the utility model discloses a subassembly of solar cell preparation has higher reliability.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout the figures.

Fig. 1 is a schematic structural diagram of a solar cell according to the present invention;

fig. 2 is a process flow diagram of a method for manufacturing a solar cell according to the present invention;

FIG. 3 is a schematic structural view after the texturing of the present invention;

fig. 4 is a schematic structural view of the present invention after front doping;

FIG. 5 is a schematic structural view of the present invention for removing back doped and front borosilicate glass;

fig. 6 is a schematic structural diagram of the passivation dielectric layer according to the present invention;

fig. 7 is a schematic structural diagram of the selective carrier transport layer according to the present invention after being prepared;

fig. 8 is a schematic structural diagram of the composite passivation film according to the present invention.

Reference numerals:

the structure comprises a silicon substrate 1, a doped region 1-1, an undoped region 1-2, a doped layer 2, a first composite passivation film 3, a front electrode 4, a passivation dielectric layer 5, a selective carrier transmission layer 6, a second composite passivation film 7 and a back electrode 8.

Detailed Description

A solar cell is described in further detail below with reference to specific examples, which are provided for comparison and explanation purposes only, and the present invention is not limited to these examples.

Various structural schematics according to embodiments of the present invention are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

In the prior art, the peripheral edge of some battery front doped layers is etched back partially, so that the edge reflectivity is higher, but the doped layers still exist. The effect of the battery is not essentially different from the common battery structure, and the short-circuit current of the battery cannot be greatly reduced. Because the edge insulation of such cells is still based on wet etching process to remove the doped emission from the back and side edges. The effect of the conventional process is that the front surface is etched back by the process, which results in a little increase in the reflectivity of the edge. The prior art has not been able to completely and better reduce the short circuit current of the battery.

The utility model discloses a solar cell, as shown in figure 1, including silicon substrate 1, the front of silicon substrate 1 includes the first surface, and the first surface includes doping region 1-1 and undoped region 1-2, and undoped region 1-2 distributes in the edge region all around of doping region 1-1, and the upper surface of doping region 1-1 is equipped with doping layer 2.

In one possible design, the width of the undoped region 1-2 does not exceed 2 mm.

Specifically, the upper surface of the doped region is a textured surface, and the upper surface of the undoped region is a polished surface.

Specifically, the conduction type of the doped layer 2 is the same as or opposite to that of the silicon substrate 1, a first composite passivation film 3 is arranged on the upper surfaces of the undoped region 1-2 and the doped layer 2, and a front electrode 4 is arranged on the upper surface of the first composite passivation film 3; a passivation dielectric layer 5, a selective carrier transmission layer 6, a second composite passivation film 7 and a back electrode 8 are sequentially arranged on the back of the silicon substrate 1 along the direction far away from the silicon substrate 1.

It is noted that if the width of the undoped region 1-2 (width refers to the distance from the outer edge of the first surface to the outer edge of the doped region 1-1) is too small, on one hand, the short-circuit current of the cell cannot be reduced to an optimum value, and on the other hand, the process control is not easy; too large a width results in too much increase in the total area of high reflectivity, resulting in much lower short circuit current of the cell, and thus much lower cell efficiency. Preferably, the width of the undoped region 1-2 is controlled to be 1 to 2mm (e.g., 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, 1.6mm, 1.7mm, 1.8mm, 1.9mm, etc.).

Compared with the prior art, the utility model discloses a solar cell's positive surface all around edge sets up the undoped region, and the undoped region has increased the distance between doping layer edge and the back doping layer edge, ensures doping layer edge and the complete disconnection of back doping layer edge, can realize lower leakage current, promotes the parallelly connected resistance of battery, can improve the yield of battery piece.

Specifically, the silicon substrate 1 is an n-type silicon substrate or a p-type silicon substrate.

Specifically, the silicon substrate 1 may be a single crystal silicon substrate or a polycrystalline silicon substrate.

Specifically, the passivation dielectric layer 5 may be a single-layer film or a stacked film of several films of a silicon oxide layer, an aluminum oxide layer, a titanium oxide layer, and a silicon oxynitride layer.

It should be noted that if the thickness of the passivation dielectric layer 5 is too thick, the carriers cannot form tunneling characteristics, and a passivation contact structure with good performance cannot be formed; the thickness is too thin, the requirement on the doping amount control of the selective carrier transmission layer is high, the batch production is not facilitated, the doping amount is slightly more, the passivation dielectric layer is easily damaged, and the performance of the passivation contact structure is damaged. Therefore, the thickness of the passivation dielectric layer 5 is controlled to be 0.1 nm-10.0 nm.

Specifically, the selective carrier transport layer 6 may be one or more stacked silicon thin films of a doped microcrystalline silicon thin film layer, an amorphous silicon thin film layer, and a polycrystalline silicon thin film layer.

It should be noted that, the too large thickness of the selective carrier transport layer 6 may reduce the short-circuit current, and further reduce the efficiency of the battery, because the transmittance of the layer is relatively poor, and the layer has a certain absorption to light; the thickness is too small, the requirement on slurry for metal contact is high, because the existing slurry has certain burn-through characteristics, the slurry is easy to burn through due to the fact that the existing slurry is too thin, a passivation dielectric layer is damaged after the slurry burns through, and the voltage, the filling factor and the efficiency of the whole battery are lowered. Therefore, the thickness of the selective carrier transport layer 6 is controlled to be 10 to 300 nm.

Specifically, the first composite passivation film 3 and the second composite passivation film 7 are made of the same material. Illustratively, the composite passivation film may be a silicon oxide SiO₂Aluminum oxide Al₂O₃Titanium oxide TiO₂Silicon oxynitride SiO_xN_1-xA single layer film or a laminated film of several kinds.

Considering that the thickness of the composite passivation film is too thick, the production cost is increased, the production capacity is reduced, and meanwhile, the contact characteristic of metal contact slurry is not facilitated, so that the filling factor and the efficiency are reduced; too thin a thickness may not provide enough hydrogen to passivate the cell. Therefore, the thicknesses of the first composite passivation film 3 and the second composite passivation film 7 are controlled to be 1-300 nm.

Specifically, the selective carrier transport layer 6 may be n-type doped or p-type doped.

The passivation dielectric layer 5 and the selective carrier transport layer 6 may be emitters doped differently from the silicon substrate 1, or may be highly doped back fields doped the same as the silicon substrate 1.

The solar cell of the utility model is prepared by adopting the following preparation method, and the preparation process flow chart is shown in figure 2, comprising the following steps:

s1, providing a p-type or n-type silicon substrate 1 with the resistivity of 0.1-20 omega cm, texturing the silicon substrate 1 by NaOH or KOH, wherein the structure after texturing is shown in figure 3, and performing HCl and O₃、H₂O₂And HF, KOH, etc. for surface cleaning.

S2, front doping: using gaseous BCl on the textured surface of the front side of the silicon substrate 1₃Or BBr₃The source is subjected to boron diffusion at 700-1100 ℃ or adopts PH₃Red phosphorus or B₂H₆After ion implantation, the plasma source carries out doping by a method of annealing at 700-1100 ℃; the structure after front doping is as shown in fig. 4, a doped layer 2 is formed on the textured surface of the front surface of the silicon substrate 1, silica glass is formed above the doped layer 2, and a diffusion layer is formed on the back surface of the silicon substrate 1.

And S3, removing the back doping and forming an undoped region 1-2 on the front surface.

Specifically, the step of removing the back-side doping and forming the undoped region 1-2 on the front-side in S3 includes the following steps:

s301, placing the silicon wafer with the front side upward in chain type wet etching equipment, and adopting HNO₃Wet etching the back surface by using HF solution, removing a back diffusion layer, placing the back diffusion layer in KOH (or using HF solution with the concentration of less than 1%) to remove porous silicon, and finally removing an HF process tank in the conventional process to retain the silica glass formed on the front surface, and simultaneously properly increasing the liquid level to ensure that proper liquid turnover is generated within 2mm around the front surface, wherein the silica glass around the front surface is obviously thinner or hardly remained than the middle part due to the liquid turnover;

s302, the silicon wafer is put into NaOH or TMAH to polish the back, and meanwhile, because the silicon glass on the periphery of the front side is thinner and cannot protect the diffusion layer, the periphery of the front side can be polished while polishing the back side, and an undoped region 1-2 is formed.

In one possible design, the step of removing the back doping in S3 and forming the undoped region 1-2 on the front surface includes the following steps:

s31, the front side of the silicon chip is upwards placed in a chain type single-side etching device, the back side single-side etching is carried out by adopting HF solution, the liquid level of the solution is ensured to be close to the front surface of the silicon chip, so that the silicon glass formed by back side diffusion is removed, meanwhile, a proper amount of chemical solution can be turned over to the periphery of the front side, the area is not more than 2mm, and the silicon glass on the periphery of the front side becomes very thin or is completely etched.

S32, putting the silicon wafer into NaOH or TMAH to polish the back; meanwhile, because the diffusion layer at the periphery of the front surface cannot be well protected under the condition that the silicon glass at the periphery of the front surface is thinner or is not available, the periphery of the front surface is polished at the same time of back surface polishing, and an undoped region 1-2 is formed.

It should be noted that this scheme is the preferred scheme, mainly because its chemicals that adopt are relatively few, and whole technology is easier to control, more is favorable to the large-scale batch production of technology ization.

s311, firstly, removing the silicon glass along the peripheral edge of the silicon wafer by adopting laser with each wavelength and the wavelength of 1064nm or 1064nm frequency doubled laser to the edge of the front surface,

and S312, putting the silicon wafer into NaOH or TMAH to polish the back, and polishing the periphery of the front while polishing the back to form an undoped region 1-2.

And S4, removing the residual silicon glass on the front surface, and cleaning, as shown in FIG. 5, so as to prepare a passivation dielectric layer later.

Specifically, HF is used to remove the residual silicon glass on the front surface in S4, and HCl and H can be used₂O₂、O₃、NH₃Further cleaning the surface by using a mixed solution of OH and the like, and finally adopting an HF solution to make the surface hydrophobic.

And S5, preparing a passivation dielectric layer 5 on the back surface of the silicon substrate, as shown in FIG. 6.

Specifically, in S5, the passivation dielectric layer 5 may be prepared on the back surface of the silicon wafer obtained in S4 by using a low-temperature furnace tube oxidation process, a nitric acid oxidation process, an ozone oxidation process, an ALD, a CVD (such as PECVD, LPCVD), a PVD (such as sputtering, evaporation), and the like.

Specifically, the passivation dielectric layer 5 in S5 may be silicon oxide SiO₂Aluminum oxide Al₂O₃Titanium oxide TiO₂Or silicon oxynitride SiO_xN_1-xThe thickness of the passivation dielectric layer 5 is 0.1 nm-10.0 nm;

and S6, preparing and forming a selective carrier transport layer 6 on the passivation dielectric layer 5, as shown in FIG. 7.

Specifically, in S6, the selective carrier transport layer 6 may be one or more stacked silicon thin films of a microcrystalline silicon thin film layer, an amorphous silicon thin film layer, and a polycrystalline silicon thin film layer, and the thickness of the silicon thin film is in a range of 10nm to 300 nm.

Specifically, in S6, the selective carrier transport layer 6 may be deposited by a Low Pressure Chemical Vapor Deposition (LPCVD) method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.

Specifically, in S6, the selective carrier transport layer 6 may be an undoped intrinsic silicon thin film or an in-situ doped but unactivated silicon thin film.

S7, back doping: the selective carrier transport layer 6 is doped or activated.

Specifically, in S7, if the selective carrier transport layer 6 is an undoped intrinsic silicon thin film, the selective carrier transport layer is implanted by an ion implanter, and then the doped impurities can be activated by annealing, so that doping of the selective carrier transport layer 6 is truly achieved, and meanwhile, crystallization is performed, thereby further improving the performance of the silicon thin film.

Specifically, in S7, if the selective carrier transport layer 6 is an in-situ doped but inactivated silicon thin film, high-temperature annealing is performed to activate impurities and achieve true doping, and crystallization of the silicon thin film is achieved, so as to further improve the performance of the silicon thin film.

And S8, preparing the composite passivation film as shown in FIG. 8.

Specifically, in S8, a composite passivation film is deposited on the surfaces of the selective carrier transport layer 6 and the front doped layer 2 by using a tube or plate Plasma Enhanced Chemical Vapor Deposition (PECVD) or ALD.

Specifically, in S8, the composite passivation film may be silicon oxide SiO₂Aluminum oxide Al₂O₃Titanium oxide TiO₂Silicon oxynitride SiO_xN_1-xThe thickness of the composite passivation film is 1-300 nm.

And S9, preparing an electrode and sintering to obtain the solar cell, as shown in figure 1.

Specifically, in S9, a metal contact paste is printed by screen printing, and then sintered to prepare the front electrode 4 and the back electrode 8, thereby obtaining the solar cell.

Example 1

The present embodiment discloses a solar cell, and the structure of the solar cell of the present embodiment is shown in fig. 1.

In the preparation method of the solar cell of the embodiment, the silicon substrate 1 is an n-type silicon wafer, the front doping is boron diffusion, and the furnace tube oxidation is used for preparing silicon dioxide (SiO)₂) The passivation dielectric layer 5 and the selective carrier transmission layer 6 are intrinsic polycrystalline silicon, P is injected into the selective carrier transmission layer 6 in an ion injection mode to realize doping, and a flow chart of the whole preparation method is shown in fig. 2. The method comprises the following specific steps:

front doping: selecting an n-type monocrystalline silicon wafer with the resistivity of 0.1-20 omega · cm, and firstly placing the n-type monocrystalline silicon wafer in a texturing groove for surface texturing to form a textured structure, as shown in figure 3; then, the textured silicon wafer is placed in a boron (B) diffusion furnace tube to prepare a p + doped layer 2, and borosilicate glass is formed on the front surface, as shown in fig. 4.

Removing the back doping: when the front side is doped, the gaseous diffusion source can also diffuse to the back side, so that doping is formed on the back side, therefore, the doped silicon wafer needs to be placed in a wet etching machine to remove the back side doping layer, and borosilicate glass formed by doping on the front side is reserved, but at the moment, the borosilicate glass on the periphery of the front side is obviously thinner than that in the middle due to liquid turnover; polishing the back surface by NaOH, wherein the borosilicate glass in the peripheral region of the front surface is thin, so that the doped layer at the peripheral region cannot be protected, and the periphery of the front surface can be polished while polishing the back surface to form an undoped region 1-2; and finally, removing the residual borosilicate glass on the front surface by adopting HF (hydrogen fluoride), so as to be convenient for preparing a passivation dielectric layer later. The schematic structure is shown in fig. 5.

Preparing a passivation dielectric layer: growing a layer of 1.5nm silicon dioxide (SiO) on the back surface by adopting a furnace tube oxidation mode₂) And passivating the dielectric layer 5 as shown in fig. 6.

Preparing a selective carrier transport layer: an undoped intrinsic polysilicon thin film having a thickness of 120nm was grown at a temperature of 610 c in a low pressure chemical deposition (LPCVD) apparatus, as shown in fig. 7.

Back doping: p ion implantation is carried out on the polycrystalline silicon film of the selective carrier transmission layer 6 by an ion implanter; and then activating at 870 ℃ to realize doping of the back, and simultaneously, carrying out crystallization heat treatment on the polycrystalline silicon film grown by LPCVD at the high temperature to further improve the performance of the film.

Preparing a composite passivation film: an oxide layer growing on the surface of the silicon wafer after the back side is doped by using an HF solution is removed, then a second composite passivation film 7 (the composite passivation film is a laminated film of aluminum oxide and silicon nitride) is grown on the selective carrier transmission layer 6 under the process condition of 460 ℃ by using a tubular Plasma Enhanced Chemical Vapor Deposition (PECVD), and a first composite passivation film 3 is grown on the doping layer 2 on the front side, as shown in FIG. 8. Wherein the thickness of the composite passive film is 120 nm.

Preparing an electrode: and printing metal contact slurry on the front surface and the back surface of the silicon wafer by adopting a screen printing mode, and preparing a front electrode 4 and a back electrode 8 by adopting a sintering process to obtain the solar cell, wherein the solar cell is shown in figure 1.

The performance parameters of the undoped solar cell prepared in this example and the ordinary solar cell are compared, and are shown in table 1 below:

table 1 properties of example 1 and conventional solar cells

Example 2

This embodiment discloses a solar cell, and the structure of the solar cell of this embodiment is the same as that of embodiment 1. The difference lies in that: in the method for manufacturing the solar cell of the embodiment, silicon dioxide (SiO) is prepared by a chemical method of nitric acid oxidation₂) The passivation dielectric layer 5 and the selective carrier transmission layer 6 are P-doped amorphous silicon and intrinsic polycrystalline silicon laminated silicon thin films. The method comprises the following specific steps:

front doping: selecting an n-type monocrystalline silicon wafer with the resistivity of 0.1-20 omega-cm, and firstly placing the n-type monocrystalline silicon wafer in a texturing groove for surface texturing to form a textured structure, as shown in figure 3; then, the textured silicon wafer is placed in a boron (B) diffusion furnace tube to prepare a p + doped layer 2, and borosilicate glass is formed on the front surface, as shown in fig. 4.

Removing the back doping: firstly, single-side etching is carried out on a silicon wafer to remove borosilicate glass formed by back diffusion, and then the silicon wafer is put into TMAH to polish the back; meanwhile, due to liquid turnover, borosilicate glass at the periphery of the front side is thinner, a doped layer at the periphery of the front side cannot be protected, and the periphery of the front side can be polished while the back side is polished to form an undoped region 1-2; and finally, removing the residual borosilicate glass on the front surface by adopting HF (hydrogen fluoride), so as to be convenient for preparing a passivation dielectric layer later. The schematic structure is shown in fig. 5.

Preparing a passivation dielectric layer: growing a layer of 1.2nm silicon dioxide (SiO) on the back surface by adopting a chemical mode of nitric acid oxidation₂) And passivating the dielectric layer 5 as shown in fig. 6.

Preparing a selective carrier transport layer: in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus, a 60nm layer of P-doped amorphous silicon film is grown on the surface of the passivation dielectric layer 5, and then a 50nm layer of undoped intrinsic polysilicon film is grown on the surface thereof, as shown in fig. 7.

Back doping: the doping source in the in-situ doped silicon film is activated at 900 ℃ to realize the doping of the back surface, and simultaneously, the crystallization heat treatment is carried out on the amorphous silicon and polycrystalline silicon films grown by LPCVD at the high temperature, so that the performance of the film is further improved.

Preparing a composite passivation film: an oxide layer growing on the surface of the silicon wafer after back doping is removed by using an HF solution, and then a first composite passivation film 3 and a second composite passivation film 7 (the composite passivation films are laminated films of aluminum oxide and silicon nitride) are respectively grown on the back selective carrier transport layer 6 and the front doping layer 2 by a tubular Plasma Enhanced Chemical Vapor Deposition (PECVD) method, as shown in FIG. 8. Wherein the thickness of the composite passive film is 50 nm.

Example 3

This embodiment discloses a solar cell, and the structure of the solar cell of this embodiment is the same as that of embodiment 1. The difference lies in that: in the preparation method of the solar cell of the embodiment, the silicon substrate 1 is a p-type silicon wafer, the front doping is phosphorus diffusion, and a layer of silicon oxynitride (SiO) is prepared by low pressure chemical deposition (LPCVD)_xN_1-x) The selective carrier transmission layer is an intrinsic undoped polysilicon thin film, and the selective carrier transmission layer is subjected to B doping in an ion injection mode. The method comprises the following specific steps:

front doping: selecting a p-type monocrystalline silicon wafer with the resistivity of 0.1-20 omega-cm, and firstly placing the p-type monocrystalline silicon wafer in a texturing groove for surface texturing to form a textured structure, as shown in figure 3; then, the textured silicon wafer is placed in a phosphorus (P) diffusion furnace tube to prepare an n + doped layer 2, and meanwhile, phosphosilicate glass is formed on the front surface, as shown in fig. 4.

Removing the back doping: firstly, removing phosphorosilicate glass on the edge of the front side by adopting laser, then putting a silicon wafer into NaOH to polish the back side, and polishing the periphery of the front side while polishing the back side to form an undoped region 1-2; and finally, removing the residual phosphorosilicate glass on the front surface by adopting HF (hydrogen fluoride), so as to be convenient for preparing a passivation dielectric layer later. The schematic structure is shown in fig. 5.

Preparing a passivation dielectric layer: in-situ growth of a layer of 2.0nm silicon oxynitride (SiO) in a low pressure chemical deposition (LPCVD) apparatus_xN_1-x) And passivating the dielectric layer 5 as shown in fig. 6.

Preparing a selective carrier transport layer: after growing the passivation dielectric layer 5 in a low pressure chemical deposition (LPCVD) apparatus, a 60nm polysilicon film was grown in the same apparatus at a temperature of 620 c, as shown in fig. 7.

Back doping: b ion implantation is carried out on the polycrystalline silicon film of the selective carrier transmission layer by an ion implanter; and activating the film at 950 ℃ to realize back doping, and simultaneously realizing crystallization heat treatment on the polycrystalline silicon film grown by LPCVD at high temperature, thereby further improving the performance of the film.

Preparing a composite passivation film: an oxide layer growing on the surface of the silicon wafer after the back side doping is removed by using an HF solution, and then a first composite passivation film 3 and a second composite passivation film 7 (the composite passivation films are laminated films of aluminum oxide and silicon nitride) are respectively grown on the selective carrier transport layer 6 on the back side and the front side doping layer 2 by a tubular Plasma Enhanced Chemical Vapor Deposition (PECVD) method, as shown in FIG. 8. Wherein the thickness of the composite passive film is 80 nm.

As can be seen from table 1, the utility model discloses a solar cell's positive surface all around edge sets up the undoped region, and the undoped region has increased the distance between doping layer edge and the back doping layer edge, ensures doping layer edge and the complete disconnection of back doping layer edge, can realize lower leakage current, promotes the parallelly connected resistance of battery, can improve the yield of battery piece.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered by the present invention.

Claims

1. A solar cell is characterized by comprising a silicon substrate (1), wherein the front surface of the silicon substrate (1) comprises a first surface, the first surface comprises a doped region (1-1) and an undoped region (1-2), the undoped region (1-2) is distributed in the peripheral edge region of the doped region (1-1), and the doped layer (2) is arranged on the upper surface of the doped region (1-1).

2. The solar cell according to claim 1, characterized in that the upper surfaces of the undoped region (1-2) and the doped layer (2) are provided with a first composite passivation film (3), and the upper surface of the first composite passivation film (3) is provided with a front electrode (4).

3. The solar cell according to claim 2, characterized in that the back side of the silicon substrate (1) is provided with a passivation dielectric layer (5), a selective carrier transport layer (6), a second composite passivation film (7) and a back electrode (8) in this order along the direction away from the silicon substrate (1).

4. The solar cell according to claim 3, wherein the passivation dielectric layer (5) is a single-layer film or a stacked-layer film of several of a silicon oxide layer, an aluminum oxide layer, a titanium oxide layer and a silicon oxynitride layer.

5. The solar cell according to claim 3, wherein the selective carrier transport layer (6) is a silicon thin film of one or more of a microcrystalline silicon thin film layer, an amorphous silicon thin film layer and a polycrystalline silicon thin film layer.

6. The solar cell according to claim 5, wherein the thickness of the passivation dielectric layer (5) is 0.1-10.0 nm.

7. The solar cell according to claim 6, wherein the thickness of the selective carrier transport layer (6) is 10 to 300 nm.

8. The solar cell according to claim 7, wherein the first composite passivation film (3) and the second composite passivation film (7) each have a thickness of 1 to 300 nm.

9. The solar cell according to any of claims 1-8, characterized in that the upper surface of the doped regions (1-1) is textured and the upper surface of the undoped regions (1-2) is polished.

10. Solar cell according to any of claims 1 to 8, characterized in that the conductivity type of the doped layer (2) is opposite or the same as the conductivity type of the silicon substrate (1).