CN212518828U - Synchronous rectification circuit - Google Patents
Synchronous rectification circuit Download PDFInfo
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- CN212518828U CN212518828U CN202021392135.4U CN202021392135U CN212518828U CN 212518828 U CN212518828 U CN 212518828U CN 202021392135 U CN202021392135 U CN 202021392135U CN 212518828 U CN212518828 U CN 212518828U
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Abstract
The utility model discloses a synchronous rectifier circuit, including coil T1C, coil T1B, MOS pipe Q2 and MOS pipe Q3, coil T1C's one end connecting resistance R5 and MOS pipe Q3's source electrode, electric capacity C5 is connected to resistance R5's the other end, electric capacity C5's other end connecting resistance R1, coil T1C's the other end, MOS pipe Q3's grid and MOS pipe Q5's grid, MOS pipe Q3's drain electrode is connected to MOS pipe Q5's drain electrode, coil T1B's one end connecting resistance R111, diode D3's negative pole and inductance L2, inductance L2's the other end connecting capacitance EC2 and output Vo +, the utility model discloses a synchronous rectifier circuit is built with the separating element, and external element is few, and the circuit is simple, and the cost is on the low side. Meanwhile, the efficiency of the product can be improved.
Description
Technical Field
The utility model relates to an electric power tech field specifically is a synchronous rectification circuit.
Background
At present, diodes are used as a switching tube and a follow current tube in most forward circuit products. Or a synchronous rectification control IC is separately selected to drive the MOSFET. One of them results in low product efficiency, and the other one results in high product cost due to the use of a separate IC and peripheral circuits.
Based on the above defects, a rectifier circuit with cost saving and efficiency improvement is to be researched.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a synchronous rectification circuit to solve the problem that proposes among the above-mentioned background art.
In order to achieve the above object, the utility model provides a following technical scheme:
a synchronous rectification circuit comprises a coil T1, an MOS tube Q and an MOS tube Q, wherein one end of the coil T1 is connected with a resistor R and a source electrode of the MOS tube Q, the other end of the resistor R is connected with a capacitor C, the other end of the capacitor C is connected with the resistor R, the other end of the coil T1, a grid electrode of the MOS tube Q and the grid electrode of the MOS tube Q, a drain electrode of the MOS tube Q is connected with a drain electrode of the MOS tube Q, one end of the coil T1 is connected with a resistor R111, a cathode of a diode D and an inductor L, the other end of the inductor L is connected with a capacitor EC and an output end Vo +, the other end of the resistor R111 is connected with the capacitor C, the other end of the capacitor C is connected with the drain electrode of the MOS tube Q and the other end of the coil T1, the other end of the resistor R is connected with a cathode of a voltage stabilizing diode Z, the resistor R and the grid electrode of, The other terminal of the capacitor EC2 and the output Vo-.
As a further technical solution of the present invention: the MOS transistor Q2 is an NMOS transistor.
As a further technical solution of the present invention: the MOS transistor Q3 is an NMOS transistor.
As a further technical solution of the present invention: the MOS transistor Q5 is an NMOS transistor.
As a further technical solution of the present invention: the diode D3 is a freewheeling diode.
Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses a synchronous rectifier circuit builds with the discrete component, and external element is few, and the circuit is simple, and the cost is on the low side. Meanwhile, the efficiency of the product can be improved.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1, embodiment 1: a synchronous rectification circuit comprises a coil T1, an MOS tube Q and an MOS tube Q, wherein one end of the coil T1 is connected with a resistor R and a source electrode of the MOS tube Q, the other end of the resistor R is connected with a capacitor C, the other end of the capacitor C is connected with the resistor R, the other end of the coil T1, a grid electrode of the MOS tube Q and the grid electrode of the MOS tube Q, a drain electrode of the MOS tube Q is connected with a drain electrode of the MOS tube Q, one end of the coil T1 is connected with a resistor R111, a cathode of a diode D and an inductor L, the other end of the inductor L is connected with a capacitor EC and an output end Vo +, the other end of the resistor R111 is connected with the capacitor C, the other end of the capacitor C is connected with the drain electrode of the MOS tube Q and the other end of the coil T1, the other end of the resistor R is connected with a cathode of a voltage stabilizing diode Z, the resistor R and the grid electrode of, The other terminal of the capacitor EC2 and the output Vo-.
The working principle of the circuit is as follows: T1B is a product secondary side coil, a resistor R111 and a capacitor C11 are absorption lines, Q2 replaces a MOSFET of a rectifier diode, a diode D3 is a freewheeling diode, L2 is an energy storage inductor, and an E capacitor C2 is an output filter capacitor. T1C is another set of coils, R5 and C5 are absorption lines, and Q3 and Q5 are switching MOSFETs for controlling MOSFET-Q2. The resistor R1 is a driving current-limiting resistor, and the function of the voltage-stabilizing diode Z1 is to ensure the stability of the gate voltage of the Q2. The resistor R2 is a discharge resistor and discharges the parasitic capacitance energy of the MOSFET-Q2 when the Q2 is turned off.
After power-on, when the transistor on the primary side is turned on, according to the principle of the same name terminal, when pin 3 of T1B generated on the secondary side of the transformer is positive, pin 4 (T1) is negative, pin 6 of a T1C coil is positive, pin 5 of a T1C coil is negative, positive voltage of pin 6 of T1C is directly connected to the grid of Q3, negative voltage of pin 5 of T1C is directly connected to the source of MOSFET-Q3, and GS of MOSFET-Q3 is turned on by adding positive voltage. Since the drain of MOSFET-Q3 is connected to the drain of MOSFET-Q5, the drain voltage of MOSFET-Q5 is also negative, while the source of MOSFET-Q5 is connected to GND, the internal body diode of Q5 is forward conducting, clamping the negative potential of pin 5 of the T1C coil, creating a positive voltage to the gate of MOSFET-Q2, and MOSFET-Q2 is conducting. The current path is: the 6-pin positive of T1C drives the current limiting resistor R1 to the Zener diode Z1 and resistor R2 to GND to the source and drain of MOSFET-Q5, to the drain and source of MOSFET-Q3, and finally back to the 5-pin negative of the T1C coil.
The main current path is from the 3 pin positive of T1B to the energy storage inductor L2 to the output Vo + to the output Vo to the main output MOSFET-Q2 (the gate voltage of MOSFET-Q2 is positive, already conducting) to the 4 pin negative of T1B, charging EC2 and creating a 1 pin positive, 2 pin negative voltage of L2 across the energy storage inductor L2.
When the transistor on the primary side is turned off, the voltage on the secondary side of the transformer is reversed, the voltage with negative pin 3 and positive pin 4 of T1B, the voltage with negative pin 6 of the coil T1C, the voltage with positive pin 5 of the coil T1C, the negative voltage of pin 6 of T1C is directly connected to the grid electrode of MOSFET-Q3, the positive voltage of pin 5 of T1C is directly connected to the source electrode of MOSFET-Q3, and GS of MOSFET-Q3 is cut off by adding negative voltage. Also, since the voltage across the DS of MOSFET-Q5 is reversed, the body diode of MOSFET-Q5 is off. In addition, the voltage at GS of MOSFET-Q5 is also negative, so MOSFET-Q5 is also off.
The main line is reverse voltage due to the voltage across the DS internal diode of MOSFET-Q2, while there is no positive voltage on GS of MOSFET-Q2. The MOSFET-Q2 is off. At this time, in order to maintain the original characteristics of the L2 energy storage inductor, a voltage with reversed polarity is generated in the L2 energy storage inductor, the 1 pin of L2 is a negative voltage, the 2 pin of L2 is a positive voltage, the current path is from the 2 pin of L2 to Vo + to Vo-to the 1 pin of D3 to L2, and the negative voltage of the 1 pin of L2 is clamped. EC1 discharges the output. The stability of the output voltage is maintained.
In embodiment 2, the MOS transistor Q2 is an NMOS transistor in addition to embodiment 1. The MOS transistor Q3 is an NMOS transistor. The MOS transistor Q5 is an NMOS transistor. The diode D3 is a freewheeling diode.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (5)
1. A synchronous rectification circuit comprises a coil T1C, a MOS tube Q C and a MOS tube Q C, and is characterized in that one end of the coil T1C is connected with a resistor R C and a source electrode of the MOS tube Q C, the other end of the resistor R C is connected with a capacitor C C, the other end of the capacitor C C is connected with the resistor R C, the other end of the coil T1C, a grid electrode of the MOS tube Q C and a grid electrode of the MOS tube Q C, a drain electrode of the MOS tube Q C is connected with a drain electrode of the MOS tube Q C, one end of the coil T1C is connected with a resistor R111, a cathode of a diode D C and an inductor L C, the other end of the inductor L C is connected with the capacitor EC C and an output end Vo +, the other end of the resistor R111 is connected with the capacitor C C, the drain electrode of the MOS tube Q C is connected with the other end of the coil T1C, the other end of the resistor R C is connected with a cathode of a zener diode Z C, the resistor R C and the grid electrode of the MOS tube Q C, the, The source of the MOS transistor Q5, the other end of the capacitor EC2 and the output Vo-.
2. The synchronous rectification circuit of claim 1, wherein the MOS transistor Q2 is an NMOS transistor.
3. The synchronous rectification circuit of claim 1, wherein the MOS transistor Q3 is an NMOS transistor.
4. The synchronous rectification circuit of claim 1, wherein the MOS transistor Q5 is an NMOS transistor.
5. The synchronous rectification circuit according to any one of claims 1 to 4, wherein the diode D3 is a freewheeling diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021392135.4U CN212518828U (en) | 2020-07-15 | 2020-07-15 | Synchronous rectification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021392135.4U CN212518828U (en) | 2020-07-15 | 2020-07-15 | Synchronous rectification circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212518828U true CN212518828U (en) | 2021-02-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021392135.4U Active CN212518828U (en) | 2020-07-15 | 2020-07-15 | Synchronous rectification circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212518828U (en) |
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2020
- 2020-07-15 CN CN202021392135.4U patent/CN212518828U/en active Active
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