CN212463161U - Intermediate frequency amplifying circuit capable of being started quickly - Google Patents
Intermediate frequency amplifying circuit capable of being started quickly Download PDFInfo
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- CN212463161U CN212463161U CN202021244636.8U CN202021244636U CN212463161U CN 212463161 U CN212463161 U CN 212463161U CN 202021244636 U CN202021244636 U CN 202021244636U CN 212463161 U CN212463161 U CN 212463161U
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Abstract
The utility model discloses a quick-start intermediate frequency amplifying circuit, which comprises an intermediate frequency amplifying circuit and a quick start circuit, wherein the intermediate frequency amplifying circuit is formed by cascading three operational amplifiers; the quick start circuit comprises a CMOS switch array, a follower array and a reference voltage source circuit, wherein one end of a CMOS switch of the CMOS switch array is connected with the intermediate frequency amplifying circuit, the other end of the CMOS switch array is respectively connected with a Vo1 end, a Vo2 end, a Vo3 end, a Vo4 end and the output end of a follower of the follower array, and the input end of the follower is respectively connected with different ports of the reference voltage source circuit; and the voltage value of each port of the reference voltage source circuit is equal to the port voltage of the intermediate frequency amplifying circuit in normal operation. The utility model discloses a quick starting circuit makes the electric charge amount at electric capacity C1 and electric capacity C2 both ends remain unchanged basically, and stabilization time shortens greatly, realizes that intermediate frequency amplifier circuit's output signal can be quick stable.
Description
Technical Field
The utility model belongs to the technical field of the integrated circuit technique and specifically relates to a quick start's intermediate frequency amplifier circuit.
Background
The intermediate frequency amplifying circuit is a power amplifying circuit, not only amplifies signals, but also has a frequency selecting function, namely, the power gain of a specific frequency band is higher than the gain of other frequency bands. The intermediate frequency amplifying circuit is widely applied to a sensor and an analog front end of a transceiver for wireless communication, and plays a crucial role. An existing commonly-used intermediate frequency amplifying circuit forms a closed-loop structure through a resistor, a capacitor and an operational amplifier, as shown in fig. 1, IFp/IFn is a differential input signal, a capacitor C11 and a resistor R11 (a resistor C12 and a resistor R12) form a first-stage high-pass filter circuit, and a capacitor C31 and a resistor R31 form a second-stage high-pass filter circuit; the capacitor C21 and the resistor R21 form a first-stage low-pass circuit, and the capacitor C41 and the resistor R41 form a second-stage low-pass circuit. The signal is amplified and output after passing through a high-pass and low-pass filter network formed by an intermediate frequency amplifying circuit, and is provided for a post-stage circuit to process. Because the stability time of the intermediate frequency amplifying circuit is mainly determined by the charging and discharging time of the operational amplifier and the high-pass capacitor C, when the high-pass cut-off frequency is low (about lower than 1kHz), the adopted capacitance value is large, the charging and discharging time is long, the corresponding stability time reaches ms level, the starting is slow, and the application of the intermediate frequency amplifying circuit in some circuit modules needing to be fast and stable is seriously limited.
SUMMERY OF THE UTILITY MODEL
The applicant aims at the problem that the conventional intermediate frequency amplifying circuit is slow in starting, and provides the intermediate frequency amplifying circuit which is reasonable in structure and can be started quickly, so that the stabilizing time of the intermediate frequency amplifying circuit is shortened, and the circuit can be started quickly and stably.
The utility model discloses the technical scheme who adopts as follows:
a quick-start intermediate frequency amplifying circuit comprises an intermediate frequency amplifying circuit and a quick start circuit, wherein the intermediate frequency amplifying circuit is formed by cascading three operational amplifiers;
the quick starting circuit comprises a CMOS switch array, a follower array and a reference voltage source circuit, wherein the CMOS switch array comprises four CMOS switches, one ends of the four CMOS switches are connected with the intermediate frequency amplifying circuit through an IF1 end, an IF2 end, an IF3 end and an IF4 end, and the other ends of the four CMOS switches are respectively connected with a Vo1 end, a Vo2 end, a Vo3 end and a Vo4 end; the output ends of the followers of the follower array are respectively connected with the Vo1 end, the Vo2 end, the Vo3 end and the Vo4 end, and the input ends of the followers are respectively connected with different ports of the reference voltage source circuit; the voltage value of each port of the reference voltage source circuit is equal to the port voltage of the intermediate frequency amplifying circuit during normal operation; the enabling ends of the operational amplifier, the CMOS switch and the follower are connected with the EN end;
the Vo1 end of the quick start circuit is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with a resistor R1 in series and then connected to the Vo2 end to form a first high-pass circuit; the Vo3 end is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with a resistor R2 in series and then connected to the Vo4 end to form a second high-pass circuit; the two ends of the capacitor C3 and the resistor R3 which are connected in parallel are respectively connected with the Vo2 end and the Vo3 end to form a first low-pass circuit; the capacitor C4 and the resistor R4 are connected in parallel, and then two ends of the capacitor C4 and the resistor R4 are respectively connected with the Vo4 end and the OUT end of the intermediate-frequency amplifying circuit to form a second low-pass circuit.
Preferably, the first-stage operational amplifier Amp1 of the intermediate frequency amplifying circuit is a pre-amplifying stage, the inverting input terminal is connected to the IN terminal, the non-inverting input terminal is connected to the INx terminal, and the output terminal is connected to the IF1 terminal; the second-stage operational amplifier Amp2 is an adjustable gain stage, the non-inverting input end of the second-stage operational amplifier Amp2 is connected with a common-mode reference signal Vcm1, the inverting input end of the second-stage operational amplifier Amp is connected with the IF2 end, the output end of the second-stage operational amplifier Amp is connected with the IF3 end, and a feedback resistor R101 is connected between the inverting input; the third-stage operational amplifier Amp3 is an output stage, the non-inverting input end of the third-stage operational amplifier Amp3 is connected with the common-mode reference signal Vcm2, the inverting input end of the third-stage operational amplifier Amp is connected with the IF4 end, the output end of the third-stage operational amplifier Amp is connected with the OUT end, and a feedback resistor R102 is connected between the inverting input.
Preferably, when the EN terminal is at a high level, the first high-pass circuit is connected to the output terminal of the first-stage operational amplifier Amp1 of the intermediate-frequency amplification circuit and the input terminal of the second-stage operational amplifier Amp2, the second high-pass circuit is connected to the output terminal of the second-stage operational amplifier Amp2 and the input terminal of the third-stage operational amplifier Amp3, the first low-pass circuit is connected to the input and output terminals of the second-stage operational amplifier Amp2, and the second low-pass circuit is connected to the input and output terminals of the third-stage operational amplifier Amp 3.
Preferably, the follower is a voltage follower.
The utility model has the advantages as follows:
the utility model discloses a quick start circuit can be so that intermediate frequency amplifier circuit when the enable signal conversion is the high level, and the electric charge amount at electric capacity C1 and electric capacity C2 both ends remains unchanged, need not unnecessary charge-discharge process, shortens intermediate frequency amplifier circuit's output signal's stabilization time greatly, and stabilization time only is original 1/4-1/5, realizes rapid and stable's output.
Drawings
Fig. 1 is a circuit diagram of a conventional intermediate frequency amplifier circuit.
Fig. 2 is a block schematic diagram of the present invention.
Fig. 3 is a circuit diagram of the intermediate frequency amplifying circuit of fig. 2.
Fig. 4 is a circuit diagram of the fast start circuit of fig. 2.
In the figure: 100. an intermediate frequency amplifying circuit; 200. a fast start circuit; 201. a CMOS switch array;
202. a follower array; 203. a reference voltage source circuit.
Detailed Description
The following describes embodiments of the present invention with reference to the drawings.
As shown IN fig. 2 to 4, the fast-start intermediate frequency amplifying circuit of the present invention includes an intermediate frequency amplifying circuit 100 and a fast start circuit 200, as shown IN fig. 3, the intermediate frequency amplifying circuit 100 is formed by cascading three operational amplifiers, after amplifying the differential signal inputted from the IN terminal and the INx terminal, the differential signal is outputted from the OUT terminal to the post-stage circuit for processing, and the enable terminals of the three operational amplifiers are all connected to the EN terminal; the first-stage operational amplifier Amp1 is a pre-amplification stage and simultaneously realizes the function of converting differential to single-ended, the inverting input end of the first-stage operational amplifier Amp1 is connected with an IN end, the non-inverting input end is connected with an INx end, and the output end is connected with an IF1 end; the second-stage operational amplifier Amp2 is an adjustable gain stage, the gain and the bandwidth can be adjusted through an external resistor and capacitor, the common-mode reference signal Vcm1 is connected to the non-inverting input end of the second-stage operational amplifier Amp2, the non-inverting input end of the second-stage operational amplifier Amp is connected to the IF2 end, the output end of the second-stage operational amplifier Amp is connected to the IF3 end, a feedback resistor R101 is connected between the non-inverting input; the third-stage operational amplifier Amp3 is an output stage, and can adjust gain and bandwidth through an external resistor and a capacitor, wherein a common-mode reference signal Vcm2 is connected to a non-inverting input end of the third-stage operational amplifier Amp3, an IF4 end is connected to an inverting input end of the third-stage operational amplifier Amp, an OUT end is connected to an output end of the third-stage operational amplifier Amp, and a feedback resistor R102 is.
As shown in fig. 4, the fast start circuit 200 includes a CMOS switch array 201, a follower array 202, and a reference voltage source circuit 203. The CMOS switch array 201 is used for switching circuit states and includes four CMOS switches, one ends of the four CMOS switches are respectively connected to the IF1 end, the IF2 end, the IF3 end and the IF4 end of the fast start circuit 200, the other ends are correspondingly connected to the Vo1 end, the Vo2 end, the Vo3 end and the Vo4 end of the fast start circuit 200, and enable ends of the CMOS switches are all connected to the EN end. The follower array 202 processes the bias voltage, plays roles of isolation and connection, and comprises four voltage followers, the output ends of the four followers are respectively connected with the Vo1 end, the Vo2 end, the Vo3 end and the Vo4 end, and the enabling ends of the followers are all connected with the EN end. The reference voltage source circuit 203 provides a bias voltage, and includes a terminal Vb1, a terminal Vb2, a terminal Vb3 and a terminal Vb4, the four terminal voltages are respectively equal to the terminal voltages of the intermediate frequency amplifying circuit 100 during normal operation, and the terminals Vb1, Vb2, Vb3 and Vb4 are respectively connected to the input terminals of different followers. The fast start circuit 200 switches the circuit state, so that the circuit can be started fast, the consumed current occupies a small part of the whole power consumption, and the consumed current is less than 10 uA.
As shown in fig. 1, the IF1, IF2, IF3 and IF4 of the IF amplifier circuit 100 are respectively connected to the IF1, IF2, IF3 and IF4 of the fast start circuit 200 in a one-to-one correspondence; the Vo1 end of the fast start circuit 200 is connected with one end of a capacitor C1, the other end of the capacitor C1 is connected with a resistor R1 in series and then connected to the Vo2 end to form a first high-pass circuit, and the first high-pass circuit is connected with the output of a first-stage operational amplifier and the input of a second-stage operational amplifier of the intermediate-frequency amplification circuit 100; the Vo3 end of the fast start circuit 200 is connected with one end of a capacitor C2, the other end of the capacitor C2 is connected with the Vo4 end after being connected with a resistor R2 in series to form a second high-pass circuit, and the second high-pass circuit is connected with the output of a second-stage operational amplifier of the intermediate frequency amplification circuit 100 and the input of a third-stage operational amplifier; the two parallel ends of the capacitor C3 and the resistor R3 are respectively connected to the Vo2 end and the Vo3 end of the fast start circuit 200 to form a first low-pass circuit, which is connected to the input and output ends of the second-stage operational amplifier of the intermediate frequency amplifying circuit 100; after the capacitor C4 and the resistor R4 are connected in parallel, two ends of the capacitor C4 are respectively connected to the Vo4 end of the fast start circuit 200 and the OUT end of the intermediate frequency amplifying circuit 100 to form a second low pass circuit, which is connected to the input and output ends of the third stage operational amplifier of the intermediate frequency amplifying circuit 100. The resistor R1, the resistor R2, the resistor R3, the resistor R4, the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 are all used for signal frequency modulation and gain control.
The working principle of the utility model is as follows:
when the enable signal EN is at a low level, the intermediate frequency amplifying circuit 100 is not turned on to operate, the CMOS switch array 201 in the fast start circuit 200 is turned off, the follower array 202 is turned on, voltages at the Vb1 terminal, the Vb2 terminal, the Vb3 terminal and the Vb4 terminal of the reference voltage module 203 are connected to the follower array 202 to provide a dc bias voltage to the two terminals of the capacitor C1 and the capacitor C2, and the voltage difference between the two terminals of the capacitor C1 and the capacitor C2 is maintained to be constant, and the charge amount is kept to be constant, at this time, the power consumption of the whole circuit comes from the fast start circuit.
When the enable signal EN is at a high level, the intermediate frequency amplifying circuit 100 starts to operate, the CMOS switch array 201 is closed and turned on, the follower array 202 is turned off, and at this time, voltages of the IF1 terminal, the IF2 terminal, the IF3 terminal, and the IF4 terminal of the fast start circuit 200 are directly connected to the Vo1 terminal, the Vo2 terminal, the Vo3 terminal, and the Vo4 terminal, because voltages of the IF1 terminal, the IF2 terminal, the IF3 terminal, and the IF4 terminal of the intermediate frequency amplifying circuit 100 are consistent with voltages provided by the Vb1 terminal, the Vb2 terminal, the Vb3 terminal, and the Vb4 terminal of the reference voltage module 203, when the circuits are switched, bias voltages at two ends of the capacitor C1 and the capacitor C2 are basically unchanged, so that charge amounts at two ends of the capacitor C1 and the capacitor C2 are basically unchanged, no additional charge and discharge processes are performed, and an output signal of the intermediate frequency amplifying circuit 100 can be; when the circuit is stable, the input signal is filtered and amplified according to the parameter values of the resistor and the capacitor, and the filtered and amplified signal is output through an OUT end to be processed by a post-stage circuit.
The above description is illustrative of the present invention and is not intended to limit the present invention, and the present invention may be modified in any manner without departing from the spirit of the present invention. The resistor R1, the resistor R2, the resistor R3, the resistor R4, the capacitor C1, the capacitor C2, the capacitor C3 and the capacitor C4 can be modified according to actual parameter requirements or configured in an adjustable mode, so that different amplification factors and bandwidth parameters can be realized.
Claims (4)
1. A quick-start intermediate frequency amplifying circuit is characterized in that: comprises an intermediate frequency amplifying circuit and a quick start circuit,
the intermediate frequency amplifying circuit is formed by cascading three operational amplifiers;
the quick starting circuit comprises a CMOS switch array, a follower array and a reference voltage source circuit, wherein the CMOS switch array comprises four CMOS switches, one ends of the four CMOS switches are connected with the intermediate frequency amplifying circuit through an IF1 end, an IF2 end, an IF3 end and an IF4 end, and the other ends of the four CMOS switches are respectively connected with a Vo1 end, a Vo2 end, a Vo3 end and a Vo4 end; the output ends of the followers of the follower array are respectively connected with the Vo1 end, the Vo2 end, the Vo3 end and the Vo4 end, and the input ends of the followers are respectively connected with different ports of the reference voltage source circuit; the voltage value of each port of the reference voltage source circuit is equal to the port voltage of the intermediate frequency amplifying circuit during normal operation; the enabling ends of the operational amplifier, the CMOS switch and the follower are connected with the EN end;
the Vo1 end of the quick start circuit is connected with one end of a capacitor C1, and the other end of the capacitor C1 is connected with a resistor R1 in series and then connected to the Vo2 end to form a first high-pass circuit; the Vo3 end is connected with one end of a capacitor C2, and the other end of the capacitor C2 is connected with a resistor R2 in series and then connected to the Vo4 end to form a second high-pass circuit; the two ends of the capacitor C3 and the resistor R3 which are connected in parallel are respectively connected with the Vo2 end and the Vo3 end to form a first low-pass circuit; the capacitor C4 and the resistor R4 are connected in parallel, and then two ends of the capacitor C4 and the resistor R4 are respectively connected with the Vo4 end and the OUT end of the intermediate-frequency amplifying circuit to form a second low-pass circuit.
2. A fast start-up if amplifier circuit according to claim 1, wherein: a first-stage operational amplifier Amp1 of the intermediate-frequency amplifying circuit is a pre-amplifying stage, the inverting input end is connected with the IN end, the non-inverting input end is connected with the INx end, and the output end is connected with the IF1 end; the second-stage operational amplifier Amp2 is an adjustable gain stage, the non-inverting input end of the second-stage operational amplifier Amp2 is connected with a common-mode reference signal Vcm1, the inverting input end of the second-stage operational amplifier Amp is connected with the IF2 end, the output end of the second-stage operational amplifier Amp is connected with the IF3 end, and a feedback resistor R101 is connected between the inverting input; the third-stage operational amplifier Amp3 is an output stage, the non-inverting input end of the third-stage operational amplifier Amp3 is connected with the common-mode reference signal Vcm2, the inverting input end of the third-stage operational amplifier Amp is connected with the IF4 end, the output end of the third-stage operational amplifier Amp is connected with the OUT end, and a feedback resistor R102 is connected between the inverting input.
3. A fast start-up if amplifier circuit according to claim 1, wherein: when the EN terminal is at a high level, the first high-pass circuit is connected to the output terminal of the first-stage operational amplifier Amp1 and the input terminal of the second-stage operational amplifier Amp2 of the intermediate-frequency amplification circuit, the second high-pass circuit is connected to the output terminal of the second-stage operational amplifier Amp2 and the input terminal of the third-stage operational amplifier Amp3, the first low-pass circuit is connected to the input and output terminals of the second-stage operational amplifier Amp2, and the second low-pass circuit is connected to the input and output terminals of the third-stage operational amplifier Amp 3.
4. A fast start-up if amplifier circuit according to claim 1, wherein: the follower is a voltage follower.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021244636.8U CN212463161U (en) | 2020-06-30 | 2020-06-30 | Intermediate frequency amplifying circuit capable of being started quickly |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021244636.8U CN212463161U (en) | 2020-06-30 | 2020-06-30 | Intermediate frequency amplifying circuit capable of being started quickly |
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| CN212463161U true CN212463161U (en) | 2021-02-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202021244636.8U Active CN212463161U (en) | 2020-06-30 | 2020-06-30 | Intermediate frequency amplifying circuit capable of being started quickly |
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