CN103067007A - Multi-stage amplifier and method used for compensating direct current offset of multi-stage amplifier - Google Patents
Multi-stage amplifier and method used for compensating direct current offset of multi-stage amplifier Download PDFInfo
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- CN103067007A CN103067007A CN2012105584005A CN201210558400A CN103067007A CN 103067007 A CN103067007 A CN 103067007A CN 2012105584005 A CN2012105584005 A CN 2012105584005A CN 201210558400 A CN201210558400 A CN 201210558400A CN 103067007 A CN103067007 A CN 103067007A
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Abstract
The invention provides a multi-stage amplifier and a method compensating direct current offset of the multi-stage amplifier. The multi-stage amplifier is provided with multiple gain stages in series connection, wherein each gain stage comprises a differential amplifier unit, the differential amplifier unit generates a pair of differential outputs from a pair of differential inputs. Specifically, a tail stage of the multiple gain stages comprises a digital direct current offset eliminating module which is configured to be used for compensating the direct current offset of a differential amplifier of the tail stage. The digital direct current offset eliminating module comprises a comparator, wherein the comparator is coupled to the pair of differential outputs of the differential amplifier unit of the tail stage so as to receive the differential outputs to use the differential outputs as input of the comparator. Preferably, the comparator is provided with little inherent direct current offset and non-tail stages of the amplifier comprises imitating direct current offset eliminating modules which are used for compensating the direct current offset of non-tail stages.
Description
Technical field
Relate generally to of the present invention is used for the direct current offset of casacade multi-amplifier and eliminates (DC Offset Cancellation, DCOC).Particularly, the present invention relates to the mixed DC skew and eliminate, it comprises the combination that the digital DC skew is eliminated and the analog DC skew is eliminated.
Background technology
Direct conversion receiver has been widely used in multiband, the multi standard wireless communication system.Even so, the existence of direct current offset also is a problem of this receiver usually.In this receiver, usually use programmable gain amplifier.Because programmable gain amplifier provides large gain usually, so large direct current offset may cause amplifier saturation.In addition, large direct current offset also may make the analogue-to-digital converters (ADC) of follow-up amplifier saturated.It also is general that the gain change of programmable gain amplifier may cause direct current offset to change.Expectation minimizes the direct current offset of amplifier, especially programmable gain amplifier.
In the art, a kind of direct current offset arrester based on analog circuit is disclosed in for example US20050110550 and US7969222.Typically, analog DC skew arrester comes the intrinsic direct current offset of Compensation Objectives amplifier with negative-feedback circuit.Sense amplifier is used for carrying out the low-pass filtering in the negative-feedback circuit.The existence of intrinsic direct current offset in the sense amplifier is so that residual direct current offset appears at output place of Target Intensifier.This residual direct current offset is random for the different integrated circuit embodiment of analog DC skew arrester.In US8260227, a kind of analog DC skew arrester is disclosed.This arrester is implemented in after the gain stage, thereby causes the possibility of amplifier saturation still to exist.
In the art, a kind of digital DC skew arrester is also disclosed.In US7215266, the rear digital DC skew of a kind of amplification arrester is disclosed.Because finish elimination by after amplifying, revising direct current offset, so there is the possibility of amplifier saturation.
US7203476 discloses a kind of mixing execution mode by direct current offset arrester that digital DC offset correction scheme is combined with analog DC offset correction scheme.Need the output of ADC switch target amplifier to be processed by digital arrester.This has increased the chip area that consumes in the integrated circuit embodiment.In addition, the skew elimination algorithm is complicated, thereby has further increased the chip area that needs.Digital DC skew arrester also had usually than the analog DC skew longer response time of arrester.
For the programmable gain amplifier of realizing having wide region and can arrange gain, casacade multi-amplifier is just progressively important.In the art, need a kind of direct current offset arrester, it can be in the situation that do not need ADC to reduce the residual direct current offset of casacade multi-amplifier, and ADC is chip area consumption-type element.
Summary of the invention
A kind of casacade multi-amplifier that comprises that direct current offset is eliminated is provided, and described direct current offset is eliminated the residual direct current offset for output place that reduces amplifier.This casacade multi-amplifier has a plurality of series gain levels, and each in described a plurality of series gain levels comprises the differential amplifier unit, and described differential amplifier cell location becomes from a pair of difference input to produce a pair of difference output.Particularly, the level of trailing in a plurality of series gain levels comprises that digital DC bias elimination module, described digital DC bias elimination module are configured to compensate the direct current offset of the differential amplifier unit of trailing level.In addition, described digital DC bias elimination module comprises comparator, and described comparator is coupled to a pair of difference output of the differential amplifier unit of trailing level, to receive this difference is exported the as a comparison a pair of input of device.Preferably, comparator arrangement becomes to have very little intrinsic direct current offset.The auto zero voltage comparator can be used as comparator.
In one embodiment, the digital DC bias elimination module comprises: digital to analog converter (DAC), it has this a pair of digital to analog converter output to the difference input that is coupled to the differential amplifier unit of trailing level, producing a pair of controllable current in this logarithmic mode transducer output place, thereby introduce extra voltage difference in the difference input of the differential amplifier unit of trailing level.The digital DC bias elimination module also comprises: the digital calibration module, and it is configured to based on the output as the comparator of input message, and the control digital to analog converter produces this to controllable current, trails the direct current offset of the differential amplifier unit of level with compensation.Thereby, do not needing to comprise compensating DC offset under the condition of analog to digital converter (ADC).The digital calibration module can be used successive approximation register (SAR) logic.
Preferably, the non-level of trailing of casacade multi-amplifier comprises analog DC offset calibration module, and it is configured to compensate the non-direct current offset of trailing level.The non-level of trailing can be programmable in gain.In one embodiment, the analog DC bias elimination module comprises: the input resistance ladder circuit, and it has and is couple to non-this pair of terminal to difference output of trailing the differential amplifier unit of level; Low pass filter, it produces the output of the first filter and the output of the second filter, inputs from the input of the first filter and the second filter that the input resistance ladder circuit obtains with low-pass filter; The first output resistor, the first terminal of the first output resistor are connected to the first filter output, and the second connecting terminals of the first output resistor is connected to one in the difference input of the non-differential amplifier unit of trailing level; And second output resistor, the first terminal of the second output resistor is connected to the output of the second filter, and the second connecting terminals of the second output resistor is connected in the difference input of the non-differential amplifier unit of trailing level another.
A kind of method of the direct current offset for compensating casacade multi-amplifier is also disclosed.Described method compensates the direct current offset of the differential amplifier unit of trailing level with the digital DC bias elimination module, wherein the digital DC bias elimination module has comparator, described comparator is coupled to a pair of difference output of differential amplifier unit, to receive this difference is exported the as a comparison a pair of input of device.Preferably, comparator arrangement becomes to have very little intrinsic direct current offset.The auto zero voltage comparator can be used as comparator.
Preferably, described method also comprises: the non-direct current offset of trailing level that uses analog DC bias elimination module compensation casacade multi-amplifier.
Description of drawings
Fig. 1 shows the example of the casacade multi-amplifier of prior art.
Fig. 2 shows the casacade multi-amplifier that direct current offset is eliminated that comprises according to the embodiment of the invention.
Fig. 3 shows the level of trailing according to the casacade multi-amplifier of the embodiment of the invention.
Fig. 4 shows the non-level of trailing according to the casacade multi-amplifier of the embodiment of the invention.
Embodiment
Casacade multi-amplifier comprises the gain stage of a plurality of series connection, and wherein, the number of gain stage is at least two.Alternatively, in the gain stage of series connection one or more the gain be programmable, thereby so that casacade multi-amplifier has programmable gain.
Fig. 1 shows the example of the casacade multi-amplifier of prior art.Casacade multi-amplifier 100 comprises N gain stage, comprises the first gain stage 131, the second gain stage 132, (N-1) gain stage 133 and N gain stage 134.Input signal 110 amplifies in the first gain stage 131.The amplifying signal of output place of the first gain stage 131 is supplied to the second gain stage 132.Gain stage subsequently repeats this processing, until N gain stage 134, the output of this grade produces the output signal 120 of casacade multi-amplifier 100.
As used herein, trailing level is last gain stage in a plurality of gain stages, and the non-level of trailing is gain stage except trailing level.In Fig. 1, the N gain stage is the level of trailing of casacade multi-amplifier 100, and the first gain stage 131, the second gain stage 132 and (N-1) gain stage 133 are the non-levels of trailing.
As defined herein, each gain stage comprises the differential amplifier unit that is configured to from a pair of difference output of a pair of difference input generation.The differential amplifier unit can comprise one or more independent differential amplifiers.No matter comprise one or a plurality of independent differential amplifiers in the differential amplifier unit, the differential amplifier unit all may have intrinsic direct current offset, and compensating intrinsic direct current offset is target of the present invention.
Such as in specification and appended claims use, direct current offset is eliminated and (is for example meaned certain electronic circuit, amplifier) intrinsic direct current offset is compensated by some modes, with can so that the direct current offset that produces in output place of this electronic circuit diminish, reduce, minimize or even eliminate.
One aspect of the present invention is to provide a kind of casacade multi-amplifier, and it comprises for reducing the direct current offset of the residual direct current offset of output place of amplifier eliminates.
For the casacade multi-amplifier with a plurality of gain stages, the inventor notices: if the direct current offset arrester is used for being right after the gain stage of intermediate gain level, a large amount of residual direct current offset that appears at output place of intermediate gain level can not persist in the output of the gain stage that is right after this intermediate gain level.The inventor also finds the inherent limitations (for example, being used in the intrinsic direct current offset of the sense amplifier in the aforesaid analog DC bias elimination module) of direct current offset arrester so that have new residual direct current offset in output place of this gain stage that is right after.By being controlled at the inherent limitations of trailing the direct current offset arrester that uses at the level place of casacade multi-amplifier, can reduce the residual direct current offset of output place of casacade multi-amplifier.The present invention is based on this result's research and development.
Exemplary embodiment of the present invention is shown in Figure 2.Casacade multi-amplifier 200 comprises the gain stage of N series connection, and the N gain stage is to trail level 234.Trail level 234 and comprise digital DC bias elimination module 244, it is configured to compensate the direct current offset of the differential amplifier unit of trailing level.As will proving very soon, the inventor notices that comparator can be as the input stage of digital DC bias elimination module 244.In addition, the inventor notice can be so that the intrinsic direct current offset of comparator be very little.For example, the auto zero voltage comparator can obtain the intrinsic direct current offset less than 1mV.On the other hand, the simulation execution mode of direct current offset arrester generally includes the input stage with sense amplifier, and sense amplifier has the approximately intrinsic direct current offset of 10mV usually.In the exemplary embodiment, digital DC bias elimination module 244 comprises comparator, and this comparator is coupled to a pair of difference output of the differential amplifier unit of trailing level 234, exports the as a comparison a pair of input of device with a pair of difference that receives differential amplifier.Preferably, comparator arrangement is become to have very little intrinsic direct current offset.Comparator can be the auto zero voltage comparator.
Compensated by digital DC bias elimination module 244 because appear at the non-direct current offset of trailing output place of grade (for example the first gain stage 231 among Fig. 2, second gain stage 232 and (N-1) gain stage 233), draw thus these non-direct current offsets of trailing level and eliminate less than the direct current offset elimination importance of trailing level 234.Alternatively, the not every non-level of trailing all uses direct current offset to eliminate.
Yet as mentioned above, digital DC skew arrester has the longer response time than analog DC skew arrester usually.In addition, the inventor has carried out following observation.For the gain stage of gain programmable, when gain changed, the response time of digital DC skew arrester that is used for this gain stage was usually long a lot of than the response time of analog DC skew arrester.In addition, when gain changed, digital DC skew arrester caused the residual direct current offset of output place of programmable-gain level to produce very large change usually.On the other hand, be used for the programmable-gain level if analog DC is offset arrester, even so when gain occurring and change, residual direct current offset is also highly stable.
Advantageously, for the non-level of trailing of selecting from the series gain level except trailing level 234, it is preferred using and being configured to compensate the non-analog DC bias elimination module of trailing the direct current offset of level.For example, optional analog DC bias elimination module 241,242 and 243 can be used in respectively in the gain stage 231,232 and 233.Using the non-level of trailing of analog DC bias elimination module can be programmable in gain.The simulation arrester is used for having the non-of programmable-gain trails level so that the residual direct current offset at output signal 220 places of casacade multi-amplifier 200 is eliminated (namely automatically, in real time or have a very short response time), and even when gain changes, the variation of basically removing residual direct current offset.
In one embodiment, the schematic diagram of the digital DC bias elimination module shown in Fig. 3, it is used in the level of trailing of casacade multi-amplifier.As shown in Figure 3, differential amplifier unit 350 is used in and trails level.Digital DC bias elimination module 310 comprises the comparator 320 of a pair of difference output that is coupled to differential amplifier unit 350.Although Fig. 3 shows the non-return input that the reverse output of differential amplifier 350 is connected to comparator 320, and the non-return output of differential amplifier 350 is connected to the reverse input of comparator 320, and the present invention is not restricted to this arrangement.Digital-analog convertor (DAC) 340 is included in the digital DC bias elimination module 310, and this digital-analog convertor has a pair of DAC output of a pair of difference input that is coupled to differential amplifier unit 350.DAC340 is used for that output place produces a pair of controllable current to DAC at this, thereby introduces extra voltage difference in the difference input of differential amplifier unit 350.Obtain extra voltage difference by two controllable currents are set to desired amount, thus when the part of controllable current flow through resistor 360,361 the time, the desired different voltage drop of intrinsic direct current offset that produces compensation difference amplifier unit 350.Digital DC bias elimination module 310 also comprises digital calibration module 330.The output of usage comparison device 320 is as input message, and digital calibration module 330 is configured to control DAC 340 producing a pair of controllable current, thus the direct current offset of compensation difference amplifier unit 350.Attention does not need to implement ADC in digital DC bias elimination module 310.
When a pair of controllable current was set to the desired amount that helps the compensating direct current deviation, digital calibration module 330 usefulness algorithms were controlled DAC 340.Alternatively, can use successive approximation register (SAR) logic to implement this algorithm.
In another embodiment, the schematic diagram of the analog DC bias elimination module shown in Fig. 4, it is used in the non-level of trailing of casacade multi-amplifier.As shown in Figure 4, analog DC bias elimination module 410 is used for compensating and is used in the non-intrinsic direct current offset of trailing the differential amplifier unit 450 in the level.Analog DC bias elimination module 410 comprises input resistance ladder circuit 420, and it has the pair of terminal of a pair of difference output that is coupled to differential amplifier unit 450.Input resistance ladder circuit 420 is used for processing this difference is exported, to produce two voltages that are used for being fed to low pass filter 430.As an example, low pass filter 430 is embodied as active RC filter as shown in Figure 4.Low pass filter 430 produces the first filter output the 433 and second filter output 434, inputs the 431 and second filter input 432 with the first filter that low-pass filter obtains from input resistance ladder circuit 420.This low-pass filter is so that low pass filter 430 produces the direct current offset value of a pair of difference output place that may appear at differential amplifier unit 450.The first output resistor 441 is used for connecting in the difference input of the output 433 of the first filter and differential amplifier unit 450.The second output resistor 440 is used for connecting another in the output 434 of the second filter and the difference input.By the magnitude of current being drawn or injecting by resistor 460,461, produced the extra voltage difference of the intrinsic direct current offset that is used for compensation differential amplifier 450.
Another aspect of the present invention is to provide a kind of method of the direct current offset for compensating casacade multi-amplifier.In the exemplary embodiment of the method, the digital DC bias elimination module is used in the level of trailing of casacade multi-amplifier, trail the direct current offset of the differential amplifier unit of level with compensation.Particularly, the digital DC bias elimination module has comparator, and it has a pair of input of a pair of difference output that is coupled to differential amplifier.Preferably, comparator arrangement is become to have very little intrinsic direct current offset.For this reason, can use the auto zero voltage comparator.Preferably, the method also comprises uses the analog DC bias elimination module, with the non-direct current offset of trailing level of compensation casacade multi-amplifier.
The present invention can be in the situation that do not deviate from its spirit or inner characteristic and implement with other particular forms.Therefore, can in all respects the present embodiment be seen as illustrative and nonrestrictive.Scope of the present invention represents by appended claims, rather than represented by aforementioned specification, and therefore, is intended to be included in wherein in equivalents and all changes in the scope of claims.
Claims (15)
1. a casacade multi-amplifier has a plurality of series gain levels, and each in described a plurality of series gain levels comprises the differential amplifier unit, and described differential amplifier cell location becomes from a pair of difference input to produce a pair of difference output, wherein:
The level of trailing in described a plurality of series gain levels comprises the digital DC bias elimination module, described digital DC bias elimination module is disposed for compensating the direct current offset of the differential amplifier unit of trailing level, wherein said digital DC bias elimination module comprises comparator, described comparator is coupled to a pair of difference output of the differential amplifier unit of trailing level, to receive this to a pair of input of difference output as described comparator.
2. casacade multi-amplifier according to claim 1, wherein one or more in the series gain level are programmable in gain, thus so that casacade multi-amplifier has programmable gain.
3. casacade multi-amplifier according to claim 1, wherein the differential amplifier unit of any in the series gain level comprises one or more independently differential amplifiers.
4. casacade multi-amplifier according to claim 1, wherein said comparator arrangement becomes to have very little intrinsic direct current offset.
5. casacade multi-amplifier according to claim 1, wherein said comparator is the auto zero voltage comparator.
6. casacade multi-amplifier according to claim 1, wherein said digital DC bias elimination module also comprises:
Digital to analog converter, it has this a pair of digital to analog converter output to the difference input that is coupled to the differential amplifier unit of trailing level, producing a pair of controllable current in this logarithmic mode transducer output place, thereby introduce extra voltage difference in the difference input of the differential amplifier unit of trailing level; And
The digital calibration module is configured to use the output of described comparator as the input message of digital calibration module, and the control digital to analog converter produces this to controllable current, trails the direct current offset of the differential amplifier unit of level with compensation;
Thereby so that direct current offset is compensated not needing to comprise under the condition of analog to digital converter.
7. casacade multi-amplifier according to claim 6, wherein the digital calibration module is used the successive approximation register logic.
8. casacade multi-amplifier according to claim 1, the non-level of trailing of wherein selecting from the series gain level except trailing level comprises the analog DC bias elimination module, it is configured to compensate the non-direct current offset of trailing level.
9. casacade multi-amplifier according to claim 8, wherein the non-level of trailing is programmable in gain.
10. casacade multi-amplifier according to claim 8, wherein the analog DC bias elimination module comprises:
The input resistance ladder circuit has and is couple to non-this pair of terminal to difference output of trailing the differential amplifier unit of level;
Low pass filter produces the output of the first filter and the output of the second filter, inputs from the input of the first filter and the second filter that the input resistance ladder circuit obtains with low-pass filter;
The first output resistor, the first terminal of the first output resistor are connected to the first filter output, and the second connecting terminals of the first output resistor is connected to one in the difference input of the non-differential amplifier unit of trailing level; And
The second output resistor, the first terminal of the second output resistor are connected to the second filter output, and the second connecting terminals of the second output resistor is connected in the difference input of the non-differential amplifier unit of trailing level another.
11. casacade multi-amplifier according to claim 10, wherein low pass filter is active RC filter.
12. method that is used for the direct current offset of compensation casacade multi-amplifier, described casacade multi-amplifier has a plurality of series gain levels, in described a plurality of series gain level each comprises the differential amplifier unit, described differential amplifier cell location becomes from a pair of difference input to produce a pair of difference output, and described method comprises:
For the level of trailing in described a plurality of series gain levels, use the compensation of digital DC bias elimination module to trail the direct current offset of the differential amplifier unit of level, wherein the digital DC bias elimination module has comparator, described comparator is coupled to a pair of difference output of the differential amplifier unit of trailing level, to receive this to a pair of input of difference output as described comparator.
13. method according to claim 12, wherein said comparator arrangement becomes to have very little intrinsic direct current offset.
14. method according to claim 12, wherein said comparator are the auto zero voltage comparators.
15. method according to claim 12 also comprises:
For the non-level of trailing of from the series gain level except trailing level, selecting, use the non-direct current offset of trailing level of analog DC bias elimination module compensation.
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Cited By (2)
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| CN104601186A (en) * | 2014-11-19 | 2015-05-06 | 深圳市中兴微电子技术有限公司 | Direct-current offset calibration method and device |
| CN110086467A (en) * | 2018-01-25 | 2019-08-02 | 亚德诺半导体无限责任公司 | The compensation of ADC digital gain error |
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| US7215266B2 (en) * | 2004-05-21 | 2007-05-08 | Wionics Research | Hybrid DC offset cancellation scheme for wireless receiver |
| CN101364796A (en) * | 2007-08-07 | 2009-02-11 | 曹志明 | DC drift eliminator applied to variable gain amplifier |
| CN102176662A (en) * | 2011-03-18 | 2011-09-07 | 北京工业大学 | Direct-current offset cancelling circuit applied to low-frequency variable gain amplifier |
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Patent Citations (4)
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| CN1369963A (en) * | 2001-02-14 | 2002-09-18 | 矽统科技股份有限公司 | DC drift eliminator for grain-variable amplifier |
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| CN101364796A (en) * | 2007-08-07 | 2009-02-11 | 曹志明 | DC drift eliminator applied to variable gain amplifier |
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| CN104601186A (en) * | 2014-11-19 | 2015-05-06 | 深圳市中兴微电子技术有限公司 | Direct-current offset calibration method and device |
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