CN103067007B - The method of the direct current offset of casacade multi-amplifier and compensation casacade multi-amplifier - Google Patents
The method of the direct current offset of casacade multi-amplifier and compensation casacade multi-amplifier Download PDFInfo
- Publication number
- CN103067007B CN103067007B CN201210558400.5A CN201210558400A CN103067007B CN 103067007 B CN103067007 B CN 103067007B CN 201210558400 A CN201210558400 A CN 201210558400A CN 103067007 B CN103067007 B CN 103067007B
- Authority
- CN
- China
- Prior art keywords
- level
- trailing
- amplifier
- direct current
- amplification unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
Abstract
The invention provides a kind of casacade multi-amplifier comprising direct current offset and eliminate.This amplifier has multiple series gain level, and each gain stage comprises the differential amplification unit producing a pair difference output from a pair Differential Input.Particularly, the digital DC offset cancellation module that level comprises the direct current offset being disposed for compensating the differential amplifier trailing level is trailed in multiple gain stage.Digital DC offset cancellation module comprises comparator, its be coupled to the differential amplification unit trailing level this to difference output, to receive the input of this difference output as comparator.Preferably, comparator has very little intrinsic direct current offset.Preferably, the non-level of trailing of amplifier comprises for compensating the non-analog DC bias elimination module trailing the direct current offset of level.
Description
Technical field
Relate generally to of the present invention eliminates (DCOffsetCancellation, DCOC) for the direct current offset of casacade multi-amplifier.Particularly, the present invention relates to mixed DC skew and eliminate, it comprises the combination that digital DC offset is eliminated and analog DC skew is eliminated.
Background technology
Direct conversion receiver has been widely used in multiband, multi standard wireless communication system.Even so, the existence of direct current offset is also a problem of this receiver usually.In this receiver, usually use programmable gain amplifier.Because programmable gain amplifier provides large gain usually, so large direct current offset may cause amplifier saturation.In addition, large direct current offset also may make the analogue-to-digital converters of follow-up amplifier (ADC) saturated.It is also general that the gain change of programmable gain amplifier may cause direct current offset to change.Expect that the direct current offset making amplifier minimizes, especially programmable gain amplifier.
In the art, in such as US20050110550 and US7969222, a kind of direct current offset arrester based on analog circuit has been disclosed.Typically, analog DC offset canceller uses negative-feedback circuit to carry out the intrinsic direct current offset of Compensation Objectives amplifier.Sense amplifier is used for carrying out the low-pass filtering in negative-feedback circuit.In sense amplifier, the existence of intrinsic direct current offset makes remnant dc offset the output appearing at Target Intensifier.The skew of this remnant dc is random for the different integrated circuit embodiment of analog DC offset canceller.In US8260227, disclose a kind of analog DC offset canceller.This arrester is implemented after gain stage, thus causes the possibility of amplifier saturation still to exist.
In the art, a kind of digital DC offset arrester is also disclosed.In US7215266, disclose the rear digital DC offset arrester of a kind of amplification.Because complete elimination by revising direct current offset after zooming, there is the possibility of amplifier saturation.
US7203476 discloses a kind of mixing execution mode of the direct current offset arrester by being combined with analog DC offset correction scheme by digital DC offset amendment scheme.Need the output of ADC switch target amplifier with by digital arrester process.Which increase the chip area consumed in integrated circuit embodiment.In addition, offset cancellation algorithm is complicated, thus further increases the chip area of needs.Digital DC offset arrester also has the response time longer than analog DC offset canceller usually.
Having wide region for realization can arrange for the programmable gain amplifier of gain, and casacade multi-amplifier is just progressively important.In the art, need a kind of direct current offset arrester, it can reduce the remnant dc skew of casacade multi-amplifier when not needing ADC, ADC is chip area consumption-type element.
Summary of the invention
Provide a kind of casacade multi-amplifier comprising direct current offset and eliminate, described direct current offset eliminates the remnant dc skew of the output for reducing amplifier.This casacade multi-amplifier has multiple series gain level, and each in described multiple series gain level comprises differential amplification unit, and described differential amplification unit is configured to produce a pair difference output from a pair Differential Input.Particularly, the level of trailing in multiple series gain level comprises digital DC offset cancellation module, and described digital DC offset cancellation module is configured to compensate the direct current offset of the differential amplification unit trailing level.In addition, described digital DC offset cancellation module comprises comparator, and described comparator is coupled to a pair difference output of the differential amplification unit trailing level, to receive this to a pair input of difference output as comparator.Preferably, comparator arrangement becomes to have very little intrinsic direct current offset.Auto zero voltage comparator can be used as comparator.
In one embodiment, digital DC offset cancellation module comprises: digital to analog converter (DAC), it has this that be coupled to the differential amplification unit of trailing level and exports a pair digital to analog converter of Differential Input, to produce a pair controllable current at this logarithmic mode convert output, thus introduce extra voltage difference on the Differential Input of differential amplification unit trailing level.Digital DC offset cancellation module also comprises: digital calibration block, and it is configured to the output based on the comparator as input information, and domination number weighted-voltage D/A converter produces this to controllable current, to compensate the direct current offset of the differential amplification unit trailing level.Thus, do not needing compensating DC offset under the condition comprising analog to digital converter (ADC).Digital calibration block can use successive approximation register (SAR) logic.
Preferably, the non-level of trailing of casacade multi-amplifier comprises analog DC offset calibration module, and it is configured to compensate the non-direct current offset trailing level.Non-level of trailing can be programmable in gain.In one embodiment, analog DC bias elimination module comprises: input resistance ladder circuit, its have be couple to non-trail the differential amplification unit of level this to the pair of terminal of difference output; Low pass filter, it produces the first filter and exports and the output of the second filter, inputs and the input of the second filter from the first filter that input resistance ladder circuit obtains with low-pass filter; First output resistor, the first terminal of the first output resistor is connected to the first filter and exports, and the second connecting terminals of the first output resistor is connected to non-of trailing in the Differential Input of the differential amplification unit of level; And second output resistor, the first terminal of the second output resistor is connected to the second filter and exports, and the second connecting terminals of the second output resistor be connected to non-trail in the Differential Input of the differential amplification unit of level another.
Also a kind of method of the direct current offset for compensating casacade multi-amplifier is disclosed.Described method uses digital DC offset cancellation module to compensate the direct current offset of the differential amplification unit trailing level, wherein digital DC offset cancellation module has comparator, described comparator is coupled to a pair difference output of differential amplification unit, to receive this to a pair input of difference output as comparator.Preferably, comparator arrangement becomes to have very little intrinsic direct current offset.Auto zero voltage comparator can be used as comparator.
Preferably, described method also comprises: use analog DC bias elimination module to compensate the non-direct current offset trailing level of casacade multi-amplifier.
Accompanying drawing explanation
Fig. 1 shows the example of the casacade multi-amplifier of prior art.
Fig. 2 shows the casacade multi-amplifier comprising direct current offset elimination according to the embodiment of the present invention.
Fig. 3 shows and trails level according to the casacade multi-amplifier of the embodiment of the present invention.
Fig. 4 shows and trails level according to the non-of casacade multi-amplifier of the embodiment of the present invention.
Embodiment
Casacade multi-amplifier comprises the gain stage of multiple series connection, and wherein, the number of gain stage is at least two.Alternatively, one or more in the gain stage of series connection are programmable in gain, thus make casacade multi-amplifier have programmable gain.
Fig. 1 shows the example of the casacade multi-amplifier of prior art.Casacade multi-amplifier 100 comprises N number of gain stage, comprises the first gain stage 131, second gain stage 132, (N-1) gain stage 133 and N gain stage 134.Input signal 110 amplifies in the first gain stage 131.The amplifying signal of the output of the first gain stage 131 is supplied to the second gain stage 132.Gain stage subsequently repeats this process, until N gain stage 134, the output of this grade produces the output signal 120 of casacade multi-amplifier 100.
As used herein, trailing level is last gain stage in multiple gain stage, and non-level of trailing is gain stage except trailing level.In FIG, N gain stage is the level of trailing of casacade multi-amplifier 100, and the first gain stage 131, second gain stage 132 and (N-1) gain stage 133 non-ly trail level.
As defined herein, each gain stage comprises the differential amplification unit being configured to produce a pair difference output from a pair Differential Input.Differential amplification unit can comprise one or more independent differential amplifier.Regardless of comprising one or multiple independent differential amplifier in differential amplification unit, differential amplification unit all may have intrinsic direct current offset, and compensating intrinsic direct current offset is target of the present invention.
As in specification and appended claims use, direct current offset is eliminated and is meaned certain electronic circuit (such as, amplifier) intrinsic direct current offset compensated by some modes, diminish so that the direct current offset produced in the output of this electronic circuit can be made, reduce, minimize or even eliminate.
One aspect of the present invention is to provide a kind of casacade multi-amplifier, and it comprises the direct current offset that the remnant dc for reducing the output of amplifier offsets and eliminates.
For the casacade multi-amplifier with multiple gain stage, inventor notices: if direct current offset arrester to be used for the gain stage of immediately intermediate gain level, and a large amount of remnant dc skew appearing at the output of intermediate gain level can not persist in the output of the gain stage of immediately this intermediate gain level.Inventor also finds that the inherent limitations (such as, being used in the intrinsic direct current offset of the sense amplifier in analog DC bias elimination module as above) of direct current offset arrester makes to there is new remnant dc skew in the output of this gain stage immediately.By controlling the inherent limitations of trailing the direct current offset arrester that level place uses at casacade multi-amplifier, the remnant dc skew of the output of casacade multi-amplifier can be reduced.The present invention is based on the research and development of this result.
Exemplary embodiment of the present invention is shown in Figure 2.Casacade multi-amplifier 200 comprises the gain stage of N number of series connection, and N gain stage trails level 234.Trail level 234 and comprise digital DC offset cancellation module 244, it is configured to compensate the direct current offset of the differential amplification unit trailing level.As will be proved very soon, inventor will notice that comparator can be used as the input stage of digital DC offset cancellation module 244.In addition, inventor notices that the intrinsic direct current offset that can make comparator is very little.Such as, auto zero voltage comparator can obtain the intrinsic direct current offset being less than 1mV.On the other hand, the simulation execution mode of direct current offset arrester generally includes the input stage with sense amplifier, and sense amplifier has the intrinsic direct current offset of about 10mV usually.In the exemplary embodiment, digital DC offset cancellation module 244 comprises comparator, and this comparator is coupled to a pair difference output of the differential amplification unit trailing level 234, to receive a pair input of a pair difference output as comparator of differential amplifier.Preferably, comparator arrangement is become to have very little intrinsic direct current offset.Comparator can be auto zero voltage comparator.
Because appear at the non-direct current offset trailing the output of level (first gain stage 231, second gain stage 232 and (N-1) gain stage 233 in such as Fig. 2) to be compensated by digital DC offset cancellation module 244, show that the direct current offset elimination importance that these non-direct current offsets trailing level are eliminated than trailing level 234 is little thus.Alternatively, not every non-level of trailing all uses direct current offset to eliminate.
But as mentioned above, digital DC offset arrester has the longer response time than analog DC offset canceller usually.In addition, inventors performed following observation.For the gain stage of gain programmable, when gain changes, the response time for the digital DC offset arrester of this gain stage is usually longer than the response time of analog DC offset canceller a lot.In addition, when gain changes, digital DC offset arrester causes the remnant dc of the output of programmable-gain level to offset the very large change of generation usually.On the other hand, if analog DC offset canceller is used for programmable-gain level, even if so when occurring that gain changes, remnant dc skew is also highly stable.
Advantageously, non-ly trail level for what select from the series gain level except trailing level 234, use that to be configured to compensate the non-analog DC bias elimination module trailing the direct current offset of level be preferred.Such as, optional analog DC bias elimination module 241,242 and 243 can be used in gain stage 231,232 and 233 respectively.The non-level of trailing using analog DC bias elimination module can be programmable in gain.The non-level of trailing being used for simulation arrester to have programmable-gain makes the remnant dc skew at output signal 220 place of casacade multi-amplifier 200 automatically eliminate (namely, in real time or there is very short response time), and even when gain changes, substantially remove the change of remnant dc skew.
In one embodiment, the schematic diagram of the digital DC offset cancellation module shown in Fig. 3, what it was used in casacade multi-amplifier trails level.As shown in Figure 3, differential amplification unit 350 is used in and trails level.Digital DC offset cancellation module 310 comprises the comparator 320 of a pair difference output being coupled to differential amplification unit 350.Although the reverse output that Fig. 3 shows differential amplifier 350 is connected to the non-return input of comparator 320, and the non-return output of differential amplifier 350 is connected to the reverse input of comparator 320, the present invention is not restricted to this arrangement.Digital-analog convertor (DAC) 340 is included in digital DC offset cancellation module 310, and a pair DAC that this digital-analog convertor has a pair Differential Input being coupled to differential amplification unit 350 exports.DAC340 is used for producing a pair controllable current at this to DAC output, thus introduces extra voltage difference on the Differential Input of differential amplification unit 350.Obtain extra voltage difference by two controllable currents are set to desired amount, thus when a part for controllable current flows through resistor 360,361, produce the different voltage drop desired by intrinsic direct current offset compensating differential amplification unit 350.Digital DC offset cancellation module 310 also comprises digital calibration block 330.Use the output of comparator 320 as input information, digital calibration block 330 is configured to control DAC340 to produce a pair controllable current, thus compensates the direct current offset of differential amplification unit 350.Note in digital DC offset cancellation module 310, do not need to implement ADC.
When a pair controllable current is set to the desired amount contributing to compensating direct current deviation, digital calibration block 330 uses algorithm to control DAC340.Alternatively, successive approximation register (SAR) logic can be used to implement this algorithm.
In another embodiment, the schematic diagram of the analog DC bias elimination module shown in Fig. 4, it is used in the non-of casacade multi-amplifier and trails level.As shown in Figure 4, analog DC bias elimination module 410 is used for compensating the intrinsic direct current offset being used in the non-differential amplification unit 450 trailed in level.Analog DC bias elimination module 410 comprises input resistance ladder circuit 420, and it has the pair of terminal of a pair difference output being coupled to differential amplification unit 450.Input resistance ladder circuit 420 is used for processing this to difference output, to produce two voltages for being fed to low pass filter 430.As an example, low pass filter 430 is embodied as active RC filter as shown in Figure 4.Low pass filter 430 produce first filter export 433 and second filter export 434, with low-pass filter from input resistance ladder circuit 420 obtain first filter input 431 and second filter input 432.This low-pass filter makes low pass filter 430 produce the DC offset value that may appear at a pair difference output place of differential amplification unit 450.First output resistor 441 be used for connection first filter export 433 and differential amplification unit 450 Differential Input in one.Second output resistor 440 be used for connection second filter export 434 and Differential Input in another.By being introduced through by the magnitude of current or injecting by resistor 460,461, create the extra voltage difference of the intrinsic direct current offset for compensating differential amplifier 450.
Another aspect of the present invention is a kind of method providing direct current offset for compensating casacade multi-amplifier.In the exemplary embodiment of the method, what digital DC offset cancellation module is used in casacade multi-amplifier trails level, to compensate the direct current offset of the differential amplification unit trailing level.Particularly, digital DC offset cancellation module has comparator, and it has a pair input of a pair difference output being coupled to differential amplifier.Preferably, comparator arrangement is become to have very little intrinsic direct current offset.For this reason, auto zero voltage comparator can be used.Preferably, the method also comprises use analog DC bias elimination module, to compensate the non-direct current offset trailing level of casacade multi-amplifier.
The present invention can implement in other specific forms when not deviating from its spirit or inner characteristic.Therefore, can in all respects the present embodiment be seen as illustrative and nonrestrictive.Scope of the present invention is represented by appended claims, instead of is represented by aforementioned specification, and therefore, all changes in the equivalents and scope of claims are intended to be included in wherein.
Claims (13)
1. a casacade multi-amplifier, has multiple series gain level, and each in described multiple series gain level comprises differential amplification unit, and described differential amplification unit is configured to produce a pair difference output from a pair Differential Input, wherein:
Level of trailing in described multiple series gain level comprises digital DC offset cancellation module, described digital DC offset cancellation module is disposed for compensating the direct current offset of the differential amplification unit trailing level, wherein said digital DC offset cancellation module comprises comparator, described comparator is coupled to a pair difference output of the differential amplification unit trailing level, to receive this to a pair input of difference output as described comparator; And
The non-level of trailing selected from the series gain level except trailing level comprises analog DC bias elimination module, and it is configured to compensate the non-direct current offset trailing level.
2. casacade multi-amplifier according to claim 1, one or more wherein in series gain level are programmable in gain, thus make casacade multi-amplifier have programmable gain.
3. casacade multi-amplifier according to claim 1, the differential amplification unit of any one wherein in series gain level comprises one or more independently differential amplifier.
4. casacade multi-amplifier according to claim 1, wherein said comparator arrangement becomes to have very little intrinsic direct current offset.
5. casacade multi-amplifier according to claim 1, wherein said comparator is auto zero voltage comparator.
6. casacade multi-amplifier according to claim 1, wherein said digital DC offset cancellation module also comprises:
Digital to analog converter, it has this that be coupled to the differential amplification unit of trailing level and exports a pair digital to analog converter of Differential Input, to produce a pair controllable current at this logarithmic mode convert output, thus introduce extra voltage difference on the Differential Input of differential amplification unit trailing level; And
Digital calibration block, be configured to the input information using the output of described comparator as digital calibration block, domination number weighted-voltage D/A converter produces this to controllable current, to compensate the direct current offset of the differential amplification unit trailing level;
Thus direct current offset is compensated under the condition not needing to comprise analog to digital converter.
7. casacade multi-amplifier according to claim 6, wherein digital calibration block uses successive approximation register logic.
8. casacade multi-amplifier according to claim 1, wherein non-level of trailing is programmable in gain.
9. casacade multi-amplifier according to claim 1, wherein analog DC bias elimination module comprises:
Input resistance ladder circuit, have be couple to non-trail the differential amplification unit of level this to the pair of terminal of difference output;
Low pass filter, produces the first filter and exports and the output of the second filter, input and the input of the second filter with low-pass filter from the first filter that input resistance ladder circuit obtains;
First output resistor, the first terminal of the first output resistor is connected to the first filter and exports, and the second connecting terminals of the first output resistor is connected to non-of trailing in the Differential Input of the differential amplification unit of level; And
Second output resistor, the first terminal of the second output resistor is connected to the second filter and exports, and the second connecting terminals of the second output resistor be connected to non-trail in the Differential Input of the differential amplification unit of level another.
10. casacade multi-amplifier according to claim 9, wherein low pass filter is active RC filter.
11. 1 kinds for compensating the method for the direct current offset of casacade multi-amplifier, described casacade multi-amplifier has multiple series gain level, each in described multiple series gain level comprises differential amplification unit, described differential amplification unit is configured to produce a pair difference output from a pair Differential Input, and described method comprises:
For trailing level in described multiple series gain level, digital DC offset cancellation module is used to compensate the direct current offset trailing the differential amplification unit of level, wherein digital DC offset cancellation module has comparator, described comparator is coupled to a pair difference output of the differential amplification unit trailing level, to receive this to a pair input of difference output as described comparator; And
Non-ly trail level for what select from the series gain level except trailing level, use analog DC bias elimination module to compensate the non-direct current offset trailing level.
12. methods according to claim 11, wherein said comparator arrangement becomes to have very little intrinsic direct current offset.
13. methods according to claim 11, wherein said comparator is auto zero voltage comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210558400.5A CN103067007B (en) | 2012-12-20 | 2012-12-20 | The method of the direct current offset of casacade multi-amplifier and compensation casacade multi-amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210558400.5A CN103067007B (en) | 2012-12-20 | 2012-12-20 | The method of the direct current offset of casacade multi-amplifier and compensation casacade multi-amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103067007A CN103067007A (en) | 2013-04-24 |
| CN103067007B true CN103067007B (en) | 2015-11-11 |
Family
ID=48109493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210558400.5A Expired - Fee Related CN103067007B (en) | 2012-12-20 | 2012-12-20 | The method of the direct current offset of casacade multi-amplifier and compensation casacade multi-amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103067007B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104601186B (en) | 2014-11-19 | 2017-05-17 | 深圳市中兴微电子技术有限公司 | Direct-current offset calibration method and device |
| US10312930B1 (en) * | 2018-01-25 | 2019-06-04 | Analog Devices Global Unlimited Company | ADC digital gain error compensation |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369963A (en) * | 2001-02-14 | 2002-09-18 | 矽统科技股份有限公司 | DC drift eliminator for grain-variable amplifier |
| US7215266B2 (en) * | 2004-05-21 | 2007-05-08 | Wionics Research | Hybrid DC offset cancellation scheme for wireless receiver |
| CN101364796A (en) * | 2007-08-07 | 2009-02-11 | 曹志明 | DC drift eliminator applied to variable gain amplifier |
| CN102176662A (en) * | 2011-03-18 | 2011-09-07 | 北京工业大学 | Direct-current offset cancelling circuit applied to low-frequency variable gain amplifier |
-
2012
- 2012-12-20 CN CN201210558400.5A patent/CN103067007B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1369963A (en) * | 2001-02-14 | 2002-09-18 | 矽统科技股份有限公司 | DC drift eliminator for grain-variable amplifier |
| US7215266B2 (en) * | 2004-05-21 | 2007-05-08 | Wionics Research | Hybrid DC offset cancellation scheme for wireless receiver |
| CN101364796A (en) * | 2007-08-07 | 2009-02-11 | 曹志明 | DC drift eliminator applied to variable gain amplifier |
| CN102176662A (en) * | 2011-03-18 | 2011-09-07 | 北京工业大学 | Direct-current offset cancelling circuit applied to low-frequency variable gain amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103067007A (en) | 2013-04-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8829989B2 (en) | DC offset cancellation for a multi-stage amplifier | |
| JP6011273B2 (en) | amplifier | |
| CN1993883B (en) | Amplifier circuit with automatic gain correction | |
| US8126087B2 (en) | DC offset correction circuit for canceling a DC offset in a real time and a receiving system having the same | |
| TW200822534A (en) | Peak detector and fixed gain amplifier circuit for automatic gain control and variable gain amplifier circuit and method thereof | |
| US6903593B2 (en) | Gain amplifier with DC offset cancellation circuit | |
| CN102497216A (en) | Configurable received signal strength indicating circuit | |
| US8725105B2 (en) | Low noise amplifier and saw-less receiver with low-noise amplifier | |
| US8050642B2 (en) | Variable gain amplifier and receiver including the same | |
| US20180123535A1 (en) | Differential current to voltage converter | |
| US8217719B2 (en) | Variable gain RF amplifier | |
| CN103067007B (en) | The method of the direct current offset of casacade multi-amplifier and compensation casacade multi-amplifier | |
| US20060279344A1 (en) | Circuit for DC offset cancellation | |
| US11264956B2 (en) | DC offset cancellation circuit and DC offset cancellation method | |
| US8285769B2 (en) | Signal processing apparatus and the correcting method | |
| US20080305759A1 (en) | Mixer Circuit | |
| KR20070001460A (en) | Apparatus and method for cancelling dc output offset | |
| CN116865695A (en) | Common mode signal suppression circuit of variable gain amplifier | |
| CN111800152B (en) | Circuit for extracting received signal strength in receiver | |
| US20020030544A1 (en) | System and method providing level shifting in single ended to differential conversion | |
| CN115865018A (en) | Variable gain amplifier | |
| CN116232245A (en) | Variable gain amplifying circuit applied to Ethernet communication | |
| CN107769735B (en) | Amplifying circuit, filter and delta-sigma modulator | |
| CN212518924U (en) | Intermediate frequency gain control circuit for navigation receiver | |
| CN221688310U (en) | Digital-analog hybrid current equalizing circuit, power module and digital power system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151111 Termination date: 20211220 |