CN101847973B - Automatic gain control circuit for receiving end of power-line carrier communication system - Google Patents

Abstract

The invention relates to an automatic gain control circuit for the receiving end of a power-line carrier communication system. A gain stage comprises at least two gain amplifiers, each gain amplifier is a dual-end differential input and dual-end differential output amplifier with the adjustable gain, wherein a differential input positive end and a differential input negative end of a second stage are connected with a differential output positive end and a differential output negative end of a first stage respectively; the differential input positive end of each gain amplifier is connected with the differential output positive end and the differential output negative end through a positive and negative end input biasing resistor and a positive end gain adjusting resistor; each gain amplifier also comprises a common mode feedback circuit and an amplifier biasing circuit; and the common mode feedback circuit detects the common mode electrical level of the differential output end, compares the common mode electrical level with reference voltage, and returns errors to the amplifier biasing circuit. The automatic gain control circuit realizes damped automatic gain control and is large in range of input voltage.

Description

The automatic gain control circuit that is used for receiving end of power-line carrier communication system

Technical field

The present invention relates to the automatic gain control circuit of a kind of OFDM of being used for (Orthogonal Frequency Division Multiplexing, i.e. orthogonal frequency division multiplexi) receiving end of power-line carrier communication system.

Background technology

In the OFDM power-line carrier communication system; Because the distance between transmitting terminal and the receiving terminal and the transmitting power of transmitting terminal are different; Signal amplitude in that receiving terminal receives is very inconsistent; This just needs the input voltage range of receiving terminal automatic gain control circuit big as far as possible, and needs the receiving terminal automatic gain control circuit to decay to the received signal or amplify, and meets the requirements of input signal amplitude.In present existing automatic gain control circuit, basically all be that input voltage range is big inadequately, have only the gain enlarging function not have the gain reduction function, be difficult to find existing big input voltage range, have the automatic gain control circuit of gain reduction function again.The automatic gain control circuit of this existing dual input dual output as shown in Figure 1 just has such shortcoming.

Summary of the invention

The object of the invention solves the aforementioned problems in the prior exactly, proposes a kind of automatic gain control circuit that is used for receiving end of power-line carrier communication system, and existing big input voltage range has the gain reduction function again.

For this reason; The automatic gain control circuit that is used for receiving end of power-line carrier communication system of the present invention comprises: two differential input ends, two difference output end and gain stage; Said pair of differential input end is first differential input end and second differential input end, and said pair of difference output end is first difference output end and second difference output end; Said gain stage comprises at least two gain amplifiers; Each gain amplifier is the input of both-end difference and the both-end difference output amplifier of Gain Adjustable; Wherein partial difference input anode links to each other with first order difference output plus terminal, and partial difference input negative terminal links to each other with first order difference output negative terminal; Said first differential input end connects the difference input anode of first order gain amplifier through first anode input biasing resistor; The difference input anode of first order gain amplifier connects the difference output plus terminal of first order gain amplifier through the first anode gain-adjusted resistance; The difference output plus terminal of first order gain amplifier connects the difference input anode of second level gain amplifier through second anode input biasing resistor; The difference input anode of second level gain amplifier is through the difference output plus terminal of second anode gain-adjusted resistance connection second level gain amplifier, and the difference output plus terminal of second level gain amplifier connects said first difference output end; Said second differential input end connects the difference input negative terminal of first order gain amplifier through first negative terminal input biasing resistor; The difference input negative terminal of first order gain amplifier connects the difference output negative terminal of first order gain amplifier through the first negative terminal gain-adjusted resistance; The difference output negative terminal of first order gain amplifier connects the difference input negative terminal of second level gain amplifier through second negative terminal input biasing resistor; The difference input negative terminal of second level gain amplifier is exported negative terminal through the difference that the second negative terminal gain-adjusted resistance connects second level gain amplifier, and the difference output negative terminal of second level gain amplifier connects said second difference output end; Each gain amplifier also comprises common mode feedback circuit, amplifier biasing circuit; Common mode feedback circuit detects the common mode electrical level of the difference output end of gain amplifier; Same reference voltage relatively; Send error back to the amplifier biasing circuit, thereby the common mode electrical level of the difference output end of gain amplifier is stabilized in said reference voltage.

Preferably, said common mode feedback circuit comprises anode feedback resistance, negative terminal feedback resistance, comparator circuit; Said amplifier biasing circuit comprises controllable current source; Anode feedback resistance, negative terminal feedback resistance detect the common mode electrical level of output, with the common mode electrical level that detects and reference voltage relatively, control the electric current of controllable current source by the comparative result error, and the common mode electrical level of exporting is stabilized in reference voltage.

Preferably, said controllable current source comprises the 4th switching tube that the 3rd switching tube that fixed current is flowed through and variable current are flowed through, and the 3rd switching tube links to each other with fixed bias voltage, and the 4th switching tube links to each other with error signal; The 3rd switching tube and the parallel connection of the 4th switching tube.

Preferably; Said fixed bias voltage derives from following circuit: circuit comprises the 3rd fixed current source, the 5th switching tube, the 3rd fixed current source one termination power, a termination the 5th switching tube anode; The 5th switching tube negativing ending grounding, control end are the fixed bias voltage output; The 5th switching tube and the 3rd switching tube form current-mirror structure.

Preferably, each gain amplifier adopts identical circuit structure and parameter.

Preferably, in each gain amplifier, anode input biasing resistor and negative terminal input biasing resistor resistance equate that anode gain-adjusted resistance and negative terminal gain-adjusted resistance are synchronous.

Owing to adopted such scheme, two difference inputs, two difference output amplifier, input anode and its gain of linear regulation separately separately of input negative terminal realize that gain can just can bear, and promptly scalablely also can decay; Meanwhile, then its biasing circuit is controlled between the positive and negative terminal, made the common mode electrical level between the positive-negative output end constant, thereby guarantee can not regulate the signal imbalance that is caused separately separately because of positive and negative terminal through common mode feedback circuit.By this, the present invention has realized the automatic gain control circuit that can decay.

Through multi-stage superimposed, the present invention makes input voltage range and the optional scope of gain all obtain enlarging.

Description of drawings

Fig. 1 is a kind of automatic gain control circuit structural representation of the prior art.

Fig. 2 a is the applied environment sketch map of automatic gain control circuit of the present invention.

Fig. 2 b is the structural representation of embodiment of the invention automatic gain control circuit.

Fig. 2 c is AMP in the embodiment of the invention automatic gain control circuit (Amplifier, an amplifying circuit) module diagram.

Fig. 3 is an embodiment of the invention integrated circuit principle schematic.

Fig. 4 is the example schematic of the controllable current source I0 among Fig. 3.

Fig. 5 is the standing part in the control signal (fixed bias voltage) VBN source sketch map among Fig. 4.

Embodiment

Embodiment one:

Shown in Fig. 2 a-5; The gain principle that the automatic gain control circuit of present embodiment adopts the common-mode voltage feedback principle and adopts the ratio between the resistance to come control circuit; Existing big input voltage range has the gain reduction function again, and the single ended input voltage scope is from 0.15V～3.15V; Basically reach supply voltage (3.3V) and ground (0V), provide-17.6dB ,-11.8dB ,-5.9dB gain reduction.

Like Fig. 2 a; FEINP, FEINN are the input signal of automatic gain control circuit AGC; FEOUTP, FEOUTN are the output signal of automatic gain control circuit AGC; So this AGC is the dual input dual output, comprise the first differential input end INP and the second differential input end INN, the first difference output end OUTP and the second difference output end OUTN.Resistance R P, RN are that voltage is provided is the direct voltage of VREF for input signal FEINP, FEINN through RP, RN.The design adopts two-stage gain stage structure; The gain of first order gain stage is-11.7dB ,-5.9dB, 0dB ,+5.9dB ,+11.8dB ,+17.7dB ,+23.4dB ,+28.8dB, the gain of second level gain stage is-5.9dB, 0dB ,+5.9dB ,+11.8dB ,+17.7dB ,+23.4dB ,+28.8dB.Select through the different gains between the two-stage gain stage, obtain minimum-17.6dB, the gain multiple of maximum+57.6dB.

Like Fig. 2 b, be depicted as the electrical block diagram of AGC.R11, R12, R13, R14, R21, R22, R23, R24 are resistance among the figure, change the gain of AGC through the resistance of regulating R13, R14, R23, R24.Two AMP are the amplifying circuit module.Present embodiment is that the two-stage amplification mode (but the invention is not restricted to two-stage; Can adopt multistage); Two AMP modules all adopt both-end difference input (X1, Y1 or X2, Y2) and both-end difference output (ON, OP or ON ', OP ') amplifier of Gain Adjustable; Wherein partial difference input anode links to each other with first order difference output plus terminal, and partial difference input negative terminal links to each other with first order difference output negative terminal.The said first differential input end INP connects the difference input anode X1 of first order gain amplifier through first anode input biasing resistor R11; The difference input anode X1 of first order gain amplifier connects the difference output plus terminal ON of first order gain amplifier through the first anode gain-adjusted resistance R 13; The difference output plus terminal ON of first order gain amplifier connects the difference input anode X2 of second level gain amplifier through second anode input biasing resistor R21; The difference input anode X2 of second level gain amplifier is through the difference output plus terminal of the second anode gain-adjusted resistance R, 23 connection second level gain amplifiers, and the difference output plus terminal of second level gain amplifier connects the said first difference output end OUTP.The said second differential input end INN connects the difference input negative terminal Y1 of first order gain amplifier through first negative terminal input biasing resistor R12; The difference input negative terminal Y1 of first order gain amplifier connects the difference output negative terminal OP of first order gain amplifier through the first negative terminal gain-adjusted resistance R 14; The difference output negative terminal OP of first order gain amplifier connects the difference input negative terminal Y2 of second level gain amplifier through second negative terminal input biasing resistor R22; The difference input negative terminal Y2 of second level gain amplifier is through the difference output negative terminal of the second negative terminal gain-adjusted resistance R, 24 connection second level gain amplifiers, and the difference output negative terminal of second level gain amplifier connects the said second difference output end OUTN.

Shown in Fig. 2 c; The amplifier circuit of gain stage adopts the common-mode voltage feedback arrangement; Common mode feedback circuit is through the common mode electrical level of resistance detection difference output end, and same reference voltage VREF relatively sends error VERR back in the amplifier biasing circuit controllable current source I0.Metal-oxide-semiconductor M1, M2 are the differential input stage circuit; I1, I2 are constant current source, and I0 is a controllable current source.

Fig. 3 makes up an embodiment who obtains after the also refinement with Fig. 2 a, 2b, 2c; Wherein there is explanation in the source of fixed bias voltage VBN in Fig. 5; Wherein common-mode voltage feedback arrangement and amplifier biasing circuit are in the AMP of circuit module; Common mode feedback circuit is made up of resistance R 1, R2, comparator circuit, and the amplifier biasing circuit is made up of current source I0, and resistance R 1, R2 detect the common mode electrical level of output; Common mode electrical level that detects and reference voltage VREF are compared; Come the electric current of Control current source I0 by comparative result error VERR, the common mode electrical level of output is stabilized in VREF, that is: the common mode electrical level with the output (being ON and OP, ON ' and the OP ' among Fig. 3) of AMP modular circuit is stabilized in VREF.Among Fig. 3, because two AMP modules identical (but the present invention is not limited to two identical situations of AMP module) so wherein used circuit element symbol adopts same numbering, do not influence explanation and understand.

As shown in Figure 4; Send error VERR back to the amplifier biasing circuit; Be current source I0 part, I0 is made up of two parts electric current, two parts parallel connection: a part is fixing electric current; Another part is variable electric current: the M3's that flows through among Fig. 4 is fixed current part (VBN is a fixed bias voltage), and the M4's that flows through is variable current part (VERR is the comparative result of " common mode electrical level of detection and reference voltage VREF compare ").

Shown in Figure 5 is a kind of source embodiment of fixed bias voltage VBN, but it is not limited to this a kind of execution mode.The 3rd fixed current source I3 one termination power, a termination the 5th switching tube M5 anode, the 5th switching tube M5 negativing ending grounding, control end are fixed bias voltage VBN output; The 5th switching tube M5 and the 3rd switching tube form current-mirror structure.

Can realize gain reduction through this circuit of proof of deriving below.

First order gain stage X1 node,

$\frac{\mathrm{ON}-X1}{R13}+\frac{\mathrm{FEINP}-X1}{R11}=0$

First order gain stage Y1 node,

$\frac{\mathrm{OP}-Y1}{R14}+\frac{\mathrm{FEINN}-Y1}{R12}=0$

ON-OP=-A again _V(X1-Y1); Suppose R11=R12, R13=R14;

Obtain $\mathrm{ON}-\mathrm{OP}=\frac{-A_{V}R13}{R11+\mathrm{<figure-callout\; id="13"\; label="R"\; filenames="HDA0000110139300000031.png"\; state="\{\{state\}\}">R</figure-callout>}13+A_{V}R11}(\mathrm{FEINP}-\mathrm{FEINN})$

$=\frac{-R13}{\frac{R11+R13}{A_V}+R11}(\mathrm{FEINP}-\mathrm{FEINN})$

$\&cong;\frac{-R13}{R11}(\mathrm{FEINP}-\mathrm{FEINN})---\left(1\right)$

In like manner, second level gain stage X2 node,

$\frac{\mathrm{FEOUTP}-X2}{R23}+\frac{\mathrm{ON}-X2}{R21}=0$

Second level gain stage Y2 node,

$\frac{\mathrm{FEOUTN}-Y2}{R24}+\frac{\mathrm{OP}-Y2}{R22}=0$

FEOUTP-FEOUTN=-A again _V(X2-Y2); Suppose R21=R22, R23=R24;

Obtain $\mathrm{FEOUTP}-\mathrm{FEOUTN}=\frac{-A_{V}R23}{R21+R23+A_{V}R21}(\mathrm{ON}-\mathrm{OP})$

$=\frac{-R23}{\frac{R21+R23}{A_V}+R21}(\mathrm{ON}-\mathrm{OP})$

$\&cong;\frac{-R23}{R21}(\mathrm{ON}-\mathrm{OP})---\left(2\right)$

By (1), (2) formula, obtain

$\mathrm{FEOUTP}-\mathrm{FEOUTN}=\frac{R23R13}{R21R11}(\mathrm{FEINP}-\mathrm{FEINN})$

FEOUTP-FEOUTN is difference output; FEINP-FEINN is the difference input, and

is the gain of AGC.

After obtaining this gain expressions, can explain very clearly that promptly the present invention can realize gain reduction.It is seen for convenient calculating, supposes R11=R12, R13=R14, R21=R22, R23=R24; (this hypothesis does not influence generality, even also suppose like this, can obtain negative gain too, i.e. gain reduction)

The gain of first order gain stage:

$\mathrm{ON}-\mathrm{OP}\&cong;\frac{-R13}{R11}(\mathrm{FEINP}-\mathrm{FEINN})$

So, $\mathrm{Gain}\left(\mathrm{DB}\right)=20\mathrm{Log}\frac{R13}{R11},$ When $\frac{R13}{R11}=\frac{1}{4},\frac{1}{2},\mathrm{1,2,4,8,16,32}$ The time, the gain that circuit simulation obtains is about-11.7dB ,-5.9dB, 0dB ,+5.9dB ,+11.8dB ,+17.7dB ,+23.4dB ,+28.8dB

In like manner, the gain of second level gain stage:

$\mathrm{FEOUTP}-\mathrm{FEOUTN}\&cong;\frac{-R23}{R21}(\mathrm{ON}-\mathrm{OP})$

So, $\mathrm{Gain}\left(\mathrm{DB}\right)=20\mathrm{Log}\frac{R23}{R21},$ When $\frac{R23}{R21}=\frac{1}{2},\mathrm{1,2,4,8,16,32}$ The time, the gain that circuit simulation obtains is about-5.9dB, 0dB ,+5.9dB ,+11.8dB ,+17.7dB ,+23.4dB ,+28.8dB

The gain of AGC:

$\mathrm{FEOUTP}-\mathrm{FEOUTN}=\frac{R23R13}{R21R11}(\mathrm{FEINP}-\mathrm{FEINN})$

So, when $\frac{R13}{R11}=\frac{1}{4},$ $\frac{R23}{R21}=\frac{1}{2}$ The time, $\mathrm{FEOUTP}-\mathrm{FEOUTN}=\frac{1}{8}(\mathrm{FEINP}-\mathrm{FEINN}),$ With 8 times of outputs of differential input signal decay (be about-17.6dB);

When $\frac{R13}{R11}=\frac{1}{2},$ $\frac{R23}{R21}=\frac{1}{2}$ The time, $\mathrm{FEOUTP}-\mathrm{FEOUTN}=\frac{1}{4}(\mathrm{FEINP}-\mathrm{FEINN}),$ With 4 times of outputs of differential input signal decay (be about-11.8dB);

When $\frac{R13}{R11}=\frac{1}{2},$ $\frac{R23}{R21}=1$ The time, $\mathrm{FEOUTP}-\mathrm{FEOUTN}=\frac{1}{2}(\mathrm{FEINP}-\mathrm{FEINN}),$ With 2 times of outputs of differential input signal decay (be about-5.9dB).

A in the formula in the top derivation _VThe open-loop gain of expression AMP modular circuit.

For first order gain stage:

$\mathrm{ON}-\mathrm{OP}=\frac{-R13}{\frac{R11+R13}{A_V}+R11}(\mathrm{FEINP}-\mathrm{FEINN})$

In this circuit, design $\frac{R13}{R11}=(\frac{1}{4},\frac{1}{2},\mathrm{1,2,4,8,16,32}),$ And design A _V>=1000,

Therefore, $\frac{R11+R13}{A_V}$ Be far smaller than R11, $\frac{R11+R13}{A_V}+R11\&cong;R11,$ So following formula is approximately:

$\mathrm{ON}-\mathrm{OP}\&cong;\frac{-R13}{R11}(\mathrm{FEINP}-\mathrm{FEINN})$

In like manner, for second level gain stage:

$\mathrm{FEOUTP}-\mathrm{FEOUTN}=\frac{-R23}{\frac{R21+R23}{A_V}+R21}(\mathrm{ON}-\mathrm{OP})$

Design $\frac{R23}{R21}=(\frac{1}{2},\mathrm{1,2,4,8,16,32}),$ And design A _V>=1000, therefore, $\frac{R21+R23}{A_V}$ Be far smaller than R21,

So following formula is approximately:

$\mathrm{FEOUTP}-\mathrm{EOUTN}\&cong;\frac{-R23}{R21}(\mathrm{ON}-\mathrm{OP})$

Because in first order gain stage and second level gain stage, we have adopted same AMP modular circuit, so, in two-stage gain stage formula, used same A _VThe open-loop gain of expression AMP modular circuit, A _VThe expression formula at place

With

In derivation of equation process, ignored by approximate.In the two-stage gain stage, we also can adopt different A _VThe AMP modular circuit, the result is the same.

Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.

Claims (6)

1. automatic gain control circuit that is used for receiving end of power-line carrier communication system; Comprise two differential input ends (INP, INN), two difference output end (OUTP, OUTN) and gain stage; Said pair of differential input end (INP, INN) is first differential input end (INP) and second differential input end (INN), and said pair of difference output end (OUTP, OUTN) is first difference output end (OUTP) and second difference output end (OUTN); It is characterized in that: said gain stage comprises at least two gain amplifiers (AMP); Each gain amplifier (AMP) is the input of both-end difference and the both-end difference output amplifier of Gain Adjustable; Wherein partial difference input anode links to each other with first order difference output plus terminal, and partial difference input negative terminal links to each other with first order difference output negative terminal; Said first differential input end (INP) connects the difference input anode (X1) of first order gain amplifier through first anode input biasing resistor (R11); The difference input anode (X1) of first order gain amplifier connects the difference output plus terminal (ON) of first order gain amplifier through the first anode gain-adjusted resistance (R13); The difference output plus terminal (ON) of first order gain amplifier connects the difference input anode (X2) of second level gain amplifier through second anode input biasing resistor (R21); The difference of second level gain amplifier input anode (X2) connects the difference output plus terminal (ON ') of second level gain amplifier through the second anode gain-adjusted resistance (R23), and the difference output plus terminal of second level gain amplifier (ON ') connects said first difference output end (OUTP); Said second differential input end (INN) connects the difference input negative terminal (Y1) of first order gain amplifier through first negative terminal input biasing resistor (R12); The difference input negative terminal (Y1) of first order gain amplifier connects the difference output negative terminal (OP) of first order gain amplifier through the first negative terminal gain-adjusted resistance (R14); The difference output negative terminal (OP) of first order gain amplifier connects the difference input negative terminal (Y2) of second level gain amplifier through second negative terminal input biasing resistor (R22); The difference of second level gain amplifier input negative terminal (Y2) connects the difference output negative terminal (OP ') of second level gain amplifier through the second negative terminal gain-adjusted resistance (R24), and the difference output negative terminal of second level gain amplifier (OP ') connects said second difference output end (OUTN); Each gain amplifier (AMP) also comprises common mode feedback circuit, amplifier biasing circuit; Common mode feedback circuit detects the common mode electrical level of the difference output end (ON, OP or ON ', OP ') of gain amplifier; Same reference voltage (VREF) relatively; (VERR) sends the amplifier biasing circuit back to error, thereby the common mode electrical level of the difference output end of gain amplifier is stabilized in said reference voltage (VREF).

2. the automatic gain control circuit that is used for receiving end of power-line carrier communication system as claimed in claim 1 is characterized in that: said common mode feedback circuit comprises anode feedback resistance (R1), negative terminal feedback resistance (R2), comparator circuit; Said amplifier biasing circuit comprises controllable current source (I0); Anode feedback resistance (R1), negative terminal feedback resistance (R2) detect the common mode electrical level of output; Common mode electrical level that detects and reference voltage (VREF) are compared; Control the electric current of controllable current source (I0) by comparative result error (VERR), the common mode electrical level of output is stabilized in reference voltage (VREF).

3. the automatic gain control circuit that is used for receiving end of power-line carrier communication system as claimed in claim 2; It is characterized in that: said controllable current source (I0) comprises the 4th switching tube (M4) that the 3rd switching tube (M3) that fixed current is flowed through and variable current are flowed through; The 3rd switching tube (M3) links to each other with fixed bias voltage (VBN), and the 4th switching tube (M4) links to each other with error signal (VERR); The 3rd switching tube (M3) and the 4th switching tube (M4) parallel connection.

4. the automatic gain control circuit that is used for receiving end of power-line carrier communication system as claimed in claim 3; It is characterized in that: said fixed bias voltage (VBN) derives from following circuit: circuit comprises the 3rd fixed current source (I3), the 5th switching tube (M5); The 3rd fixed current source (I3) termination power; One termination the 5th switching tube (M5) anode, the 5th switching tube (M5) negativing ending grounding, control end are fixed bias voltage (VBN) output; The 5th switching tube (M5) forms current-mirror structure with the 3rd switching tube.

5. according to claim 1 or claim 2 the automatic gain control circuit that is used for receiving end of power-line carrier communication system, it is characterized in that: each gain amplifier (AMP) adopts identical circuit structure and parameter.

6. according to claim 1 or claim 2 the automatic gain control circuit that is used for receiving end of power-line carrier communication system; It is characterized in that: in each gain amplifier (AMP); Anode input biasing resistor (R11, R21) and negative terminal input biasing resistor (R12, R22) resistance equate that anode gain-adjusted resistance (R13, R23) and negative terminal gain-adjusted resistance (R14, R24) are synchronous.

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