CN212278334U - Video processing apparatus and display system - Google Patents

Abstract

The embodiment of the utility model discloses video processing equipment and a display system, video processing equipment includes: the first switching module comprises a first Ethernet PHY chip; the main control card comprises a second Ethernet PHY chip and a first connector connected with the second Ethernet PHY chip, the first connector is connected with the main control connector, and the main control connector is connected with the first Ethernet PHY chip through a plurality of first differential signal lines; the video input card comprises a third Ethernet PHY chip and a second connector connected with the third Ethernet PHY chip, the second connector is connected with the input connector, and the input connector is connected with the first Ethernet PHY chip through a plurality of second differential signal lines; the video output card comprises a third connector, and the third connector is connected with the output connector. The utility model discloses can satisfy the big and long requirement of transmission distance of transmission data volume between the integrated circuit board.

Description

Video processing apparatus and display system

Technical Field

The utility model relates to a show technical field, especially relate to a video processing equipment and a display system.

Background

At present, the communication distance between the control chip and each sub-module in the video processing equipment is short, and the transmitted data volume is small, so that simple communication modes such as IIC can be used. However, when the number of boards of the video processing device increases and the amount of data to be transmitted increases, the common protocols IIC, USB, SPI, and the like for on-board communication at present cannot meet the requirements of the amount of data and the transmission distance, thereby reducing the stability of the entire video processing device.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a video processing equipment and display system can satisfy the long requirement of transmission data volume big and transmission distance between the integrated circuit board.

Specifically, the embodiment of the utility model provides a video processing device, include: a back plate provided with a plurality of connectors; a first switching module comprising: a first Ethernet PHY chip; the first programmable logic device is connected with the first Ethernet PHY chip; the first microcontroller is connected with the first programmable logic device; the master control card includes: a second microcontroller; the second programmable logic device is connected with the second microcontroller; the second Ethernet PHY chip is connected with the second programmable logic device; a first connector connecting the second ethernet PHY chip and a master connector of the plurality of connectors, wherein the master connector is connected to the first ethernet PHY chip via a plurality of first differential signal lines; at least one video input card, each said video input card comprising: a video input interface; the third programmable logic device is connected with the video input interface; the third microcontroller is connected with the third programmable logic device; the third Ethernet PHY chip is connected with the third programmable logic device; a second connector connecting the third Ethernet PHY chip and an input connector of the plurality of connectors, wherein the input connector connects the first Ethernet PHY chip via a plurality of second differential signal lines; at least one video output card, each said video output card comprising: a third connector connecting an output connector of the plurality of connectors.

When the number of board cards of the video processing equipment is increased and the data volume to be transmitted is increased, the common protocols IIC, USB or SPI for the on-board communication cannot meet the requirements of the data volume and the transmission distance, so that the stability of the whole video processing equipment is reduced; the embodiment of the utility model discloses a master control card is connected through the difference signal line to first programmable logic device in the first exchange module among the video processing equipment, video input card and video output card, avoid the agreement IIC that inboard communication is used always, the condition that USB or SPI etc. can not satisfy data volume and transmission distance's requirement, can satisfy the long requirement of transmission data volume between the integrated circuit board big and transmission distance, realize signal control, and reduce cost effectively, reduce the cloth board degree of difficulty, improve development time.

In an embodiment of the present invention, the first switch module is located on the backplane, and the first ethernet PHY chip is electrically connected to the plurality of connectors; or the first switching module further comprises: a fourth connector connecting the first Ethernet PHY chip and a first switch connector of the plurality of connectors; the first Ethernet PHY chip, the first programmable logic device, the first microcontroller and the fourth connector are located on the same daughter card.

In an embodiment of the present invention, each of the video output cards further includes: a fourth Ethernet PHY chip connected to the third connector; the fourth programmable logic device is connected with the fourth Ethernet PHY chip; and the fourth microcontroller is connected with the fourth programmable logic device, wherein the output connector is connected with the first Ethernet PHY chip through a plurality of third differential signal lines.

In an embodiment of the present invention, the fourth connector includes a plurality of first GPIO pins, a plurality of second GPIO pins, and a plurality of third GPIO pins, wherein the plurality of first GPIO pins are connected to the main control connector, the plurality of second GPIO pins are connected to the input connector, and the plurality of third GPIO pins are connected to the output connector.

In an embodiment of the present invention, the main control connector is connected to the first ethernet PHY chip through four pairs of first differential signal lines, the input connector is connected to the first ethernet PHY chip through two pairs of second differential signal lines, and the output connector is connected to the first ethernet PHY chip through two pairs of third differential signal lines.

In an embodiment of the present invention, the back plate further includes: a second switching module connecting the plurality of connectors, the second switching module including a data switching chip.

In an embodiment of the present invention, the video processing apparatus further includes: a second switching module comprising: the data exchange chip and a fifth connector connected with the data exchange chip; the data exchange chip and the fifth connector are located on the same daughter card, and the fifth connector is further connected with a second exchange connector in the plurality of connectors.

In an embodiment of the present invention, the at least one video output card is a plurality of video output cards, the plurality of video output cards include a first video output card, the first video output card further includes: and the video source output interface is connected with the fourth programmable logic device.

In an embodiment of the present invention, the at least one video output card is a plurality of video output cards, the plurality of video output cards include a second video output card, the second video output card further includes: the fifth programmable logic device is connected with the fourth programmable logic device and the fourth microcontroller; the fifth Ethernet PHY chip is connected with the fifth programmable logic device; the network transformer is connected with the fifth Ethernet PHY chip; the Ethernet interface is connected with the network transformer; the optical module is connected with the fifth programmable logic device; and the optical fiber interface is connected with the optical module.

Furthermore, an embodiment of the present invention provides a display system, including: any one of the video processing devices described above; and the display equipment is connected with the video output card of the video processing equipment.

The technical scheme in the embodiment has the following advantages or beneficial effects: the condition that common protocols IIC, USB or SPI of the in-board communication cannot meet the requirements of data volume and transmission distance is avoided, the requirements of large data volume transmission and long transmission distance between the board cards can be met, signal control is achieved, cost is effectively reduced, board distribution difficulty is reduced, and development time is prolonged.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a video processing apparatus according to a first embodiment of the present invention.

Fig. 2 is another schematic structural diagram of a video processing apparatus according to the first embodiment of the present invention.

Fig. 3 is a diagram illustrating an exemplary pin connection relationship between a third ethernet PHY chip and a third programmable logic device in the video processing apparatus shown in fig. 1 or fig. 2.

Fig. 4 is a schematic pin diagram of a fourth connector in the video processing apparatus shown in fig. 2.

Fig. 5 is another schematic structural diagram of a video processing apparatus according to the first embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a video processing apparatus according to the first embodiment of the present invention.

Fig. 7 is a schematic structural diagram of a first video output card in a video processing apparatus according to a first embodiment of the present invention.

Fig. 8 is a schematic structural diagram of a second video output card in the video processing apparatus according to the first embodiment of the present invention.

Fig. 9 is a schematic structural diagram of a display system according to a second embodiment of the present invention.

[ brief description of the drawings ]

10: a video processing device; 11: a back plate; 111: a master control connector; 112: an input connector; 113: an output connector; 114: a first switching connector; 115: a second switching connector; 12: a first switching module; 121: a first Ethernet PHY chip; 122: a first programmable logic device; 123: a first microcontroller; 124: a fourth connector; 1241: a first GPIO pin; 1242: a second GPIO pin; 1243: a third GPIO pin; 13: a master control card; 131: a second microcontroller; 132: a second programmable logic device; 133: a second Ethernet PHY chip; 134: a first connector; 14: a video input card; 141: a video input interface; 142: a third programmable logic device; 143: a third microcontroller; 144: a third Ethernet PHY chip; 145: a second connector; 15: a video output card; 151. 151a, 151 b: a third connector; 152. 152a, 152 b: a fourth Ethernet PHY chip; 153. 153a, 153 b: a fourth programmable logic device; 154. 154a, 154 b: a fourth microcontroller; 155 a: a video source output interface; 156 b: a fifth programmable logic device; 157 b: a fifth Ethernet PHY chip; 158 b: a network transformer; 159 b: an Ethernet interface; 160 b: an optical module; 161 b: an optical fiber interface; 16: a second switching module; 161: a data exchange chip; 162: a fifth connector;

30: a display system; 31: a video processing device; 32: a display device.

Detailed Description

It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict. The invention will be described with reference to the accompanying drawings in conjunction with embodiments.

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that the division of the embodiments in the present invention is only for convenience of description and should not be construed as a limitation, and features in various embodiments may be combined and referred to each other without contradiction.

[ first embodiment ] A method for manufacturing a semiconductor device

Referring to fig. 1, a first embodiment of the present invention discloses a video processing apparatus. As shown in fig. 1, the video processing apparatus 10 includes, for example: a backplane 11, a first switching module 12, a master card 13, at least one video input card 14, and at least one video output card 15. Fig. 1 illustrates a video input card 14 and a video output card 15, but the present invention is not limited thereto, and the number of the video input card 14 and the video output card 15 may be set according to actual needs.

Specifically, the back panel 11 includes, for example, a plurality of connectors. The first switching module 12 includes, for example: a first ethernet PHY chip 121, a first programmable logic device 122, and a first microcontroller 123, wherein the first programmable logic device 122 is connected to the first ethernet PHY chip 121, and the first microcontroller 123 is connected to the first programmable logic device 122. The master card 13 includes, for example: the second microcontroller 131, the second programmable logic device 132, the second ethernet PHY chip 133, and the first connector 134, wherein the second programmable logic device 132 is connected to the second microcontroller 131, the second ethernet PHY chip 133 is connected to the second programmable logic device 132, and the first connector 134 is connected to the second ethernet PHY chip 133 and the main control connector 111 of the plurality of connectors, wherein the main control connector 111 is connected to the first ethernet PHY chip 121 through a plurality of first differential signal lines. The video input card 14 includes, for example: the video input interface 141, the third programmable logic device 142, the third microcontroller 143, the third ethernet PHY chip 144, and the second connector 145, wherein the third programmable logic device 142 is connected to the video input interface 141, the third microcontroller 143 is connected to the third programmable logic device 142, the third ethernet PHY chip 144 is connected to the third programmable logic device 142, and the second connector 145 is connected to the third ethernet PHY chip 144 and the input connector 112 of the plurality of connectors, wherein the input connector 112 is connected to the first ethernet PHY chip 121 through a plurality of second differential signal lines. The video output card 15 includes, for example: a third connector 151, wherein the third connector 151 connects the output connector 113 of the plurality of connectors.

Further, as shown in FIG. 1, the first switch module 12 is located on the backplane 11, and the first Ethernet PHY chip 121 electrically connects a plurality of connectors on the backplane 11.

Further, the first switch module 12 may be connected to the backplane 11 in the form of a daughter card. As shown in fig. 2, the first switch module 12 further includes, for example: and a fourth connector 124 connecting the first ethernet PHY chip 121 and the first switching connector 114 of the plurality of connectors. Wherein the first ethernet PHY chip 121, the first programmable logic device 122, the first microcontroller 123 and the fourth connector 124 are located on the same daughter card. The first switching module 12 is connected with the backboard 11 in a daughter card mode, so that the first switching module 12 can be reused among different derivative models of the video processing equipment, the PCB layout difficulty is reduced, and the defect that a derivative model development hardware structure needs to be redeveloped is avoided.

Further, as shown in fig. 2, the video output card 15 further includes, for example: a fourth ethernet PHY chip 152, a fourth programmable logic device 153, and a fourth microcontroller 154, wherein the fourth ethernet PHY chip is connected to the third connector, the fourth programmable logic device 153 is connected to the fourth ethernet PHY chip 152, the fourth microcontroller 154 is connected to the fourth programmable logic device 153, and the output connector 113 is connected to the first ethernet PHY chip 121 through a plurality of third differential signal lines.

The connectors on the backplane 11, such as the main control connector 111, the input connector 112, the output connector 113, and the first switch connector 114, are female connectors, such as the first connector 134 in the main control card 13, the second connector 145 in the video input card 13, the third connector 151 in the video output card 15, and the fourth connector 124 in the first switch module 12, are pin header connectors, which are connected to the female connectors by plugging, and the mentioned pin header connectors are, for example, simple ox horn pin header connectors, which are abbreviated as "simple cow" connectors, and are composed of square plastic sockets and several regularly arranged square pins, of course, the connectors on the backplane 12 and the sub-cards, such as the main control card, the video input card, and the connectors on the video output card, may also be other types of connectors, etc. The aforementioned first Microcontroller 123, third Microcontroller 143 and fourth Microcontroller 154 are, for example, MCUs (Microcontroller units), also called Single Chip microcomputers (Single Chip microcomputers) or Single-Chip microcomputers, for example, the model of the MCUs is STM32F 207. The second mentioned microcontroller 131 is for example an ARM processor or a DSP processor, in particular an ARM processor such as an ARM11 system processor, for example an ARM processor model such as ARM1176 JZ-S. The mentioned video input interface 141 is, for example, any one or any combination of an HDMI interface, a DVI interface, an SDI interface, and a DP interface. The first Programmable logic device 122, the second Programmable logic device 132, the third Programmable logic device 142, and the fourth Programmable logic device 153 are, for example, an FPGA (Field-Programmable Gate Array) or other similar logic devices. For example, the model number of the FPGA is 410TFFG900, for example. The first, second, third and fourth ethernet PHY chips 121, 133, 144, 152 are referred to as gigabit network PHY chips, or hundred mega network PHY chips, for example. For example, the third ethernet PHY chip 144 is, for example, a hundred mega network PHY chip model, and its model is, for example, LAN8720 or LAN8211, where the pin connection relationship between LAN8211 and the third programmable logic device 142, such as an FPGA, can be seen in fig. 3.

Further, as shown in fig. 4, the fourth connector 124 includes, for example, a plurality of first GPIO pins 1241, a plurality of second GPIO pins 1242, and a plurality of third GPIO pins 1243, wherein the plurality of first GPIO pins 1241 are connected to the main control connector 111, the plurality of second GPIO pins 1242 are connected to the input connector 112, and the plurality of third GPIO pins 1243 are connected to the output connector 113. It should be noted that fig. 4 illustrates four first GPIO pins 1241, two second GPIO pins 1242 and two third GPIO pins 1243, but the present invention is not limited thereto, for example, the first GPIO pins 1241 are eight GPIO pins, and the eight GPIO pins are connected by four pairs of differential signal lines. The plurality of second GPIO pins 1242 are, for example, four GPIO pins connected, for example, by two pairs of differential signal lines. The third GPIO pins 1243 are, for example, four GPIO pins connected, for example, by two pairs of differential signal lines. It is understood herein that the specific number of the first GPIO pin 1241, the second GPIO pin 1242 and the third GPIO pin 1243 may be set according to practical situations.

Further, the main control connector 111 is connected to the first ethernet PHY chip 121 through four pairs of first differential signal lines, the input connector 112 is connected to the first ethernet PHY chip 121 through two pairs of second differential signal lines, and the output connector 113 is connected to the first ethernet PHY chip 121 through two pairs of third differential signal lines. That is, the master card 13 communicates with the first switch module 12 via, for example, a gigabit network, and the video input card 14 and the video output card 15 communicate with the first switch module 12 via a hundred megabyte network. Therefore, the requirements of application scenes of large transmission data volume and long transmission distance are further met.

Further, as shown in fig. 5, the back plate 11 further includes, for example: a second switching module 16 to which a plurality of connectors are connected, the second switching module 16 including, for example, a data switching chip 161. It is to be understood here that the second switching module 16 is arranged, for example, on the backplane 11.

Further, the aforementioned second switch module 16 may establish a connection with the backplane 11 in the form of a daughter card. As shown in fig. 6, the second switching module 16 includes, for example: the data exchange chip 161 and a fifth connector 162 connected to the data exchange chip 161, wherein the data exchange chip 161 and the fifth connector 162 are located on the same daughter card, and the fifth connector 162 is further connected to the second exchange connector 114 of the plurality of connectors. The second switching module 16 is connected with the back plate 11 in a daughter card mode, so that the first switching module 16 can be reused among different derivative models of the video processing equipment, the difficulty of PCB layout is reduced, and the defect that a derivative model development hardware structure needs to be redeveloped is avoided.

Specifically, the fifth connector includes, for example, a plurality of SerDes pins, and the data exchange chip 161 is connected to the plurality of SerDes pins, where the data exchange chip 161 mainly exchanges image data and transmits the image data through the SerDes pins, so that the exchange efficiency of the image data is higher. The data exchange chip 161 is, for example, a Crosspoint exchange chip. The fifth connector 162 is, for example, a pin header connector, and the second switching connector 114 is, for example, a female header connector.

Further, the aforementioned at least one video output card 15 is, for example, a plurality of video output cards 15, as shown in fig. 7, the plurality of video output cards 15 includes, for example, a first video output card 15a, and the first video output card 15a includes, in addition to the aforementioned third connector 151a, fourth ethernet PHY chip 152a, fourth programmable logic device 153a and fourth microcontroller 154 a: and a video source output interface 155a connected to the fourth programmable logic device 153 a.

Specifically, the video source output interface 155a is, for example, any one or any combination of an HDMI interface, a DVI interface, an SDI interface, and a DP interface.

Further, as shown in fig. 8, the aforementioned plurality of video output cards 15 includes, for example, a second video output card 15b, and the second video output card 15b includes, for example, in addition to the aforementioned third connector 151b, a fourth ethernet PHY chip 152b, a fourth programmable logic device 153b, and a fourth microcontroller 154 b: a fifth programmable logic device 156b, a fifth ethernet PHY chip 157b, a network transformer 158b, an ethernet interface 159b and/or optical module 160b, and an optical fiber interface 161 b. The fifth programmable logic device 156b is connected to the fourth programmable logic device 153b and the fourth microcontroller 154b, the fifth ethernet PHY chip 157b is connected to the fifth programmable logic device 156b, the network transformer 158b is connected to the fifth ethernet PHY chip 157b, the ethernet interface 159b is connected to the network transformer 158b, the optical module 160b is connected to the fifth programmable logic device 156b, and the optical fiber interface 161b is connected to the optical module 160 b. The fifth ethernet PHY chip 157b is connected to the LED display screen as a main interface, and the optical fiber interface 161b is used as a backup interface.

Specifically, the fifth Programmable logic device 156b is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic device. For example, the model number of the FPGA is 410TFFG900, for example. Fifth ethernet PHY chip 157b is, for example, a hundred mega network PHY chip, such as a hundred mega network PHY chip model number LAN8720 or LAN 8211. Ethernet interface 159b is, for example, a hundred megabyte or gigabit port, such as an RJ45 port. The optical module 160b is, for example, an SFP optical module. The optical fiber interface 161b is, for example, a 10G optical fiber interface, a 20G optical fiber interface, or a 40G optical fiber interface.

It should be noted that the difference between the first video output card 15a and the second video output card 15b is that the first video output card 15a can be connected to the LCD display through the video source output interface 155a, and if the first video output card 15a wants to connect to the LED display, an external connection transmitting card is required to connect to the LED display; and the second video output card 15b can be directly connected to the LED display screen via the ethernet interface 159b, or connected to the photoelectric conversion device via the optical fiber interface 161b and then connected to the LED display screen, so as to avoid external connection of the transmitting card. The mentioned LED display screen includes, for example, a display control card and an LED display screen body connected to the display control card, where the display control card is also called as a receiving card or a scanning card in the LED display screen control system, and includes: the LED display screen comprises a network interface, a programmable logic device connected with the network interface, a microcontroller connected with the programmable logic device, a memory and the like, wherein the network interface is RJ45, the memory is volatile memory SDRAM, the programmable logic device is FPGA, the microcontroller is MCU, the LED display screen body is formed by splicing a plurality of LED modules, each LED module is provided with a display control card, and a single LED module comprises an LED lamp panel (or LED unit panel) or a plurality of LED lamp panels spliced together.

It should be noted that the video processing device 10 disclosed in the present embodiment is, for example, a card-insertion type device having a video processing function, such as a video processor or a video splicer.

To sum up, the utility model discloses a video processing equipment can avoid the condition that can not satisfy the requirement of data volume and transmission distance such as the agreement IIC that inboard communication was used commonly, USB or SPI, can satisfy the big and long requirement of transmission distance of transmission data volume between the integrated circuit board, realizes signal control, and reduce cost effectively, reduces the cloth board degree of difficulty, improves development time.

[ second embodiment ]

As shown in fig. 9, a second embodiment of the present invention discloses a display system 30, for example, including: a video processing device 31 and a display device 32.

Wherein the display device 32 is connected to a video output card in the video processing device 31. The video processing device 31 is, for example, the video processing device 10 disclosed in the foregoing first embodiment, and for the description of the video processing device 31, reference may be made to the foregoing first embodiment, which is not repeated herein for brevity.

Specifically, the display device 32 is, for example, an LCD display screen, and the display device 32 is connected to a video source output interface of a first video output card in the video processing device 31, where the mentioned first video output card is, for example, the first video output card 15a disclosed in the first embodiment, and includes, for example: the device comprises a third connector, a fourth Ethernet PHY chip, a fourth programmable logic device, a fourth microcontroller and a video source output interface, wherein the fourth programmable logic device is connected with the fourth Ethernet PHY chip, the video source output interface and the fourth microcontroller, and the third connector is connected with the fourth Ethernet PHY chip.

In addition, the display device 32 is, for example, an LED display screen, and a first video output card in the video processing device 31 thereof may be connected to the LED display screen through a video source output interface connection transmitting card, or a second video output card of the video processing device 31 is directly connected to the LED display screen, and the mentioned second video output card is, for example, the second video output card 15b disclosed in the first embodiment, and includes, for example: the optical module comprises a third connector, a fourth Ethernet PHY chip, a fourth programmable logic device, a fifth programmable logic device, a fourth microcontroller, a fifth Ethernet PHY chip, a network transformer, an Ethernet interface, an optical module and an optical fiber interface, wherein the fourth programmable logic device is connected with the third connector through the fourth Ethernet PHY chip, the seventh programmable logic device is connected with the sixth programmable logic device, the fourth microcontroller is connected with the sixth programmable logic device, the fourth programmable logic device is also connected with the fourth microcontroller and the fifth programmable logic device, the fifth programmable logic device is connected with the fourth microcontroller, the fifth Ethernet PHY chip and the optical module, the fifth Ethernet PHY chip is connected with the Ethernet interface through the network transformer, and the optical fiber interface is connected with the optical module.

Specifically, the third connector is, for example, a pin header connector, and the pin header connector is, for example, a simple pin header connector, which is abbreviated as "simple pin" connector and consists of a square plastic socket and a plurality of regularly arranged square pins, and of course, other types of connectors and the like are also possible. The fourth Programmable logic device and the fifth Programmable logic device are, for example, an FPGA (Field-Programmable Gate Array) or other similar logic devices. For example, the model number of the FPGA is 410TFFG900, for example. The fourth Microcontroller is, for example, an MCU (Microcontroller Unit), also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer; or other microprocessors with certain data processing and computing capabilities, such as ARM processors and DSP processors, for example, of the type STM32F 207. The mentioned video source output interface is, for example, any one or any combination of an HDMI interface, a DVI interface, an SDI interface, and a DP interface. The optical module is, for example, an SFP optical module. The mentioned fiber interfaces are for example 10G fiber interfaces, 20G fiber interfaces or 40G fiber interfaces. The fourth and fifth ethernet PHY chips mentioned are for example hundred mega network PHY chips, for example, of the type LAN8720 or LAN 8211. The mentioned ethernet interface is for example a hundred mega or gigabit port, for example an RJ45 port.

To sum up, the utility model discloses a video processing equipment can avoid the condition that agreement IIC, USB or SPI that the inboard communication was used commonly can not satisfy data volume and transmission distance's requirement among the display system that the second embodiment discloses, can satisfy the requirement that transmission data volume is big and transmission distance is long between the integrated circuit board, realizes signal control, and reduce cost effectively, reduces the cloth board degree of difficulty, improves development time.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention in its corresponding aspects.

Claims (10)

1. A video processing apparatus, comprising:

a back plate provided with a plurality of connectors;

a first switching module comprising:

a first Ethernet PHY chip;

the first programmable logic device is connected with the first Ethernet PHY chip;

the first microcontroller is connected with the first programmable logic device;

the master control card includes:

a second microcontroller;

the second programmable logic device is connected with the second microcontroller;

the second Ethernet PHY chip is connected with the second programmable logic device;

a first connector connecting the second ethernet PHY chip and a master connector of the plurality of connectors, wherein the master connector is connected to the first ethernet PHY chip via a plurality of first differential signal lines;

at least one video input card, each said video input card comprising:

a video input interface;

the third programmable logic device is connected with the video input interface;

the third microcontroller is connected with the third programmable logic device;

the third Ethernet PHY chip is connected with the third programmable logic device;

a second connector connecting the third Ethernet PHY chip and an input connector of the plurality of connectors, wherein the input connector connects the first Ethernet PHY chip via a plurality of second differential signal lines;

at least one video output card, each said video output card comprising:

a third connector connecting an output connector of the plurality of connectors.

2. The video processing device of claim 1, wherein the first switching module is located on the backplane and the first ethernet PHY chip electrically connects the plurality of connectors; or

The first switching module further comprises:

a fourth connector connecting the first Ethernet PHY chip and a first switch connector of the plurality of connectors; wherein the first ethernet PHY chip, the first programmable logic device, the first microcontroller, and the fourth connector are located on the same daughter card.

3. The video processing device of claim 1, wherein each of the video output cards further comprises:

a fourth Ethernet PHY chip connected to the third connector;

the fourth programmable logic device is connected with the fourth Ethernet PHY chip;

and the fourth microcontroller is connected with the fourth programmable logic device, wherein the output connector is connected with the first Ethernet PHY chip through a plurality of third differential signal lines.

4. The video processing device of claim 2, wherein the fourth connector comprises a plurality of first GPIO pins, a plurality of second GPIO pins, and a plurality of third GPIO pins, wherein the plurality of first GPIO pins connect the master connector, the plurality of second GPIO pins connect the input connector, and the plurality of third GPIO pins connect the output connector.

5. The video processing device of claim 1, wherein the master connector is connected to the first ethernet PHY chip via four pairs of first differential signal lines, wherein the input connector is connected to the first ethernet PHY chip via two pairs of second differential signal lines, and wherein the output connector is connected to the first ethernet PHY chip via two pairs of third differential signal lines.

6. The video processing device of claim 1, wherein the backplane further comprises: a second switching module connecting the plurality of connectors, the second switching module including a data switching chip.

7. The video processing device according to claim 1, further comprising: a second switching module comprising: the data exchange chip and a fifth connector connected with the data exchange chip; the data exchange chip and the fifth connector are located on the same daughter card, and the fifth connector is further connected with a second exchange connector in the plurality of connectors.

8. The video processing device of claim 3, wherein the at least one video output card is a plurality of video output cards including a first video output card, the first video output card further comprising:

and the video source output interface is connected with the fourth programmable logic device.

9. The video processing device of claim 3, wherein the at least one video output card is a plurality of video output cards including a second video output card, the second video output card further comprising:

the fifth programmable logic device is connected with the fourth programmable logic device and the fourth microcontroller;

the fifth Ethernet PHY chip is connected with the fifth programmable logic device;

the network transformer is connected with the fifth Ethernet PHY chip;

the Ethernet interface is connected with the network transformer;

the optical module is connected with the fifth programmable logic device;

and the optical fiber interface is connected with the optical module.

10. A display system, comprising:

the video processing device of any of claims 1-9; and

and the display equipment is connected with the video output card of the video processing equipment.

Images