CN212113688U - Chip packaging structure and electronic equipment - Google Patents
Chip packaging structure and electronic equipment Download PDFInfo
- Publication number
- CN212113688U CN212113688U CN202021160422.2U CN202021160422U CN212113688U CN 212113688 U CN212113688 U CN 212113688U CN 202021160422 U CN202021160422 U CN 202021160422U CN 212113688 U CN212113688 U CN 212113688U
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- Prior art keywords
- chip
- substrate
- connector
- package structure
- chip package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a chip packaging structure and electronic equipment, wherein, the chip packaging structure comprises a substrate, a chip, a connector and a plastic package layer, the substrate is provided with a first surface; the chip is electrically connected to the first surface; the connector is electrically connected to the first surface and is arranged at intervals with the chip, and a protection piece is arranged on the surface of the connector, which is far away from the substrate; the plastic packaging layer covers the first surface and the chip, an avoiding groove is formed in the surface deviating from the first surface, and at least the surface of the protection piece deviating from the substrate is exposed out of the avoiding groove. The utility model discloses technical scheme's chip package structure stability is good and low cost.
Description
Technical Field
The utility model relates to an encapsulation technology field, in particular to chip packaging structure and electronic equipment.
Background
In order to improve the stability of the main components of the electronic product, the product is generally packaged, and a substrate local plastic package process is often used for system-in-package products, so that on one hand, devices integrated on the substrate are protected, and on the other hand, a base of the connector is exposed, thereby facilitating the signal extraction and interconnection from the devices to a PCB of the system. The conventional local plastic package schemes comprise two types, namely single injection molding and integral injection molding, all the conventional local plastic package schemes need to process jigs matched with product structures, and the processing cost and the processing period are high.
SUMMERY OF THE UTILITY MODEL
The main object of the present invention is to provide a chip package structure, which is low in cost and stable in structure.
To achieve the above object, the chip package structure provided by the present invention comprises a substrate having a first surface;
a chip electrically connected to the first surface;
the connector is electrically connected to the first surface and is arranged at a distance from the chip, and a protection piece is arranged on the surface of the connector, which is far away from the substrate; and
and the plastic packaging layer covers the first surface and the chip, an avoiding groove is formed in the surface deviating from the first surface, and at least the surface deviating from the substrate of the protection piece is exposed in the avoiding groove.
In an alternative embodiment, the surface area of the guard is the same as the area of the surface of the connector that conforms to the guard.
In an alternative embodiment, the guard is a protective tape.
In an optional embodiment, an opening area of the avoiding groove is larger than a surface area of the connector facing away from the substrate.
In an optional embodiment, the chip further includes a passive device electrically connected to the first surface and spaced apart from the chip, and the molding compound covers the passive device.
In an alternative embodiment, the connector is attached to the substrate.
In an optional embodiment, a plurality of tin solder balls are convexly arranged on the surface of the chip facing the substrate, and the tin solder balls are connected with the substrate.
In an optional embodiment, a gap is formed between every two of the solder balls, and the gap is filled with transparent adhesive.
In an optional embodiment, the substrate further has a second surface, and the second surface is provided with a plurality of pads arranged at intervals in a protruding manner.
The utility model discloses provide an electronic equipment again, include the casing and locate chip package structure in the casing, chip package structure is as above chip package structure.
The utility model discloses technical scheme's chip package structure includes the base plate, the electricity is connected in the chip and the connector of base plate, and the connector is used for going out the signal of telecommunication transmission of chip. The first surface of base plate is covered to the plastic envelope layer to encapsulate chip and connector simultaneously, and the plastic envelope layer has been seted up in the position that corresponds the connector and has been dodged the groove, can realize connector and external electricity and transmission signal, and shelter from through the protector when not connecting, effectively guarantee the connection performance of connector. The structure can ensure that the connector is connected and the stability of the connector is realized through plastic package; meanwhile, the groove is avoided, so that the requirement on the primary forming process of the plastic packaging layer is avoided, the jig for matching the product structure is reduced, the processing cost is effectively saved, and the processing period is shortened.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a cross-sectional view of an embodiment of the chip package structure of the present invention;
fig. 2 is a cross-sectional view of the chip package structure of the present invention in a first state during the processing;
fig. 3 is a cross-sectional view of the chip package structure of the present invention in a second state during the processing;
fig. 4 is a cross-sectional view of the chip package structure of the present invention in the connection process.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | |
50 | Connector with a |
| 10 | |
60 | |
| 11 | |
70 | |
| 13 | |
71 | Dodging |
| 131 | |
80 | |
| 30 | Chip and method for manufacturing the same | 90 | |
| 31 | Tin solder ball |
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In the present application, unless expressly stated or limited otherwise, the terms "connected" and "fixed" are to be construed broadly, e.g., "fixed" may be fixedly connected or detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In addition, descriptions in the present application as to "first", "second", and the like are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a chip package structure 100.
Referring to fig. 1, in the embodiment of the present invention, a chip package structure 100 includes a substrate 10, where the substrate 10 has a first surface 11;
a chip 30, said chip 30 being electrically connected to said first surface 11;
a connector 50, wherein the connector 50 is electrically connected to the first surface 11 and is spaced apart from the chip 30, and a protection member 60 is disposed on a surface of the connector 50 facing away from the substrate 10; and
the molding compound layer 70 covers the first surface 11 and the chip 30, and an avoiding groove 71 is formed on a surface away from the first surface 11, and at least a surface of the protection member 60 away from the substrate 10 is exposed to the avoiding groove 71.
In this embodiment, the substrate 10 is a PCB, the substrate 10 has a first surface 11 and a second surface 13 opposite to each other, and the first surface 11 is provided with a circuit trace required for implementing a corresponding function and signal transmission after being electrically connected to the chip 30 and the connector 50. Specifically, the type of the chip 30 is not limited, and may be, for example, a Micro Controller Unit (MCU), or other chips 30 such as sensors. The connector 50 may be of a type of FPC (Flexible Printed Circuit) mainly used for connecting a Flexible board, but may be of other types such as a strip connector, a press-on connector, or the like. The surface of the connector 50 facing away from the substrate 10 is provided with a protection member 60, and the protection member 60 may be a protection tape, which may be made of teflon, pet, or the like, has characteristics of high temperature resistance, and the like, and can protect the connector 50. Of course, the shielding member 60 may be a metal gasket, which also has high temperature resistance. The surface area of the guard 60 may be equal to or less than the surface area of the connector 50 facing away from the substrate 10, ensuring that the connection portion is not damaged.
The plastic packaging layer 70 is made of plastic, and can be formed after inward injection molding after covering the substrate 10 by a common mold, and the plastic packaging layer 70 wraps the first surface 11, the chip 30 and the connector 50, so that a plurality of components on the substrate 10 can be fixed, and the structural stability is improved. Here, the shape and thickness of the molding layer 70 may be determined according to actual conditions, and are not limited herein. The avoiding groove 71 formed in the plastic sealing layer 70 may or may not match the shape of the connector 50, and only the protecting member 60 needs to be exposed, so that the connector 50 can be connected to the outside after the protecting member 60 is uncovered. Of course, when the area of the protection member 60 is smaller than the surface area of the connector 50, the surface of the connector 50 facing away from the substrate 10 may be exposed.
The utility model discloses technical scheme's chip package structure 100 includes base plate 10, the electricity is connected in chip 30 and connector 50 of base plate 10, and connector 50 is used for going out chip 30's signal of telecommunication. The molding compound layer 70 covers the first surface 11 of the substrate 10, encapsulates the chip 30 and the connector 50 at the same time, and the avoiding groove 71 is formed at a position of the molding compound layer 70 corresponding to the connector 50, so that the connector 50 can be electrically connected with the outside to transmit signals, and the shielding part 60 shields the signal when the signal is not connected, thereby effectively ensuring the connection performance of the connector 50. The arrangement of the structure can ensure that the connector 50 realizes connection and simultaneously realizes the stability of the connector 50 through plastic package; meanwhile, the avoidance of the groove 71 can ensure that no requirement is made on the primary forming process of the plastic packaging layer 70, reduce the jig for matching the product structure, effectively save the processing cost and shorten the processing period.
In an alternative embodiment, the surface area of the guard 60 is the same as the area of the surface of the connector 50 that conforms to the guard 60.
In this embodiment, in order to improve the protection performance of the connector 50, the surface area of the protection component 60 is set to be equal to the surface area of the connector 50, where the surface of the connector 50 is a surface that is attached to the protection component 60, that is, a surface that is away from the substrate 10, and the surface may be a plane, a curved surface, a step surface, or the like, without limitation, and the corresponding connector 50 is selected according to actual requirements, and correspondingly, the protection component 60 is attached to the surface, so that a relatively stable protection effect is achieved, and the service life of the connector 50 is prolonged.
In an alternative embodiment, the opening area of the avoiding groove 71 is larger than or equal to the surface area of the connector 50 facing away from the substrate 10.
In this embodiment, in order to be able to conveniently connect the connector 50 to the outside when in use, the opening area of the avoiding groove 71 is set to be large, and is greater than or equal to the surface area of the connector 50 departing from the substrate 10, if the connector 50 is a male connector, when the female connector 80 is connected to the male connector, the handheld female connector 80 can be conveniently held to enter the avoiding groove 71, and the convenience of assembly is improved.
In an alternative embodiment, the chip module further includes a passive device 90, the passive device 90 is electrically connected to the first surface 11 and is spaced apart from the chip 30, and the molding compound layer 70 covers the passive device 90.
In this embodiment, the chip package structure 100 further includes a passive device 90, and the passive device 90 is an element that can perform some electrical functions without an external power source, for example, an element such as a resistor, a capacitor, or another inductor. The passive device 90 and the chip 30 are arranged at an interval, so that the function of the chip packaging structure 100 can be improved, the signal of the passive device 90 can be transmitted to a system through the substrate 10 and the connector 50, signal transmission is realized, the passive device 90 is also covered by the plastic packaging layer 70, and the stability of the structure can be ensured.
In a specific embodiment, the passive device 90 and the connector 50 are bonded to the substrate 10, that is, the passive device 90 and the connector 50 are both connected to the substrate 10 by a Surface Mount Technology (SMT), so that the structure is stable and the processing is convenient. Certainly, the mounting can also be performed in a wafer mounting manner, and since the above processes are all in the existing mounting manner, detailed description of the specific operations is omitted.
Referring to fig. 1, in an alternative embodiment, a plurality of solder balls 31 are protruded from the surface of the chip 30 facing the substrate 10, and the solder balls 31 are connected to the substrate 10.
In this embodiment, the chip 30 is connected to the substrate 10 through a plurality of solder balls 31, that is, the chip is directly soldered to the substrate 10 in a solder ball implanting manner, and the connection manner can stabilize the chip 30, thereby preventing the chip from falling off and improving the stability of the chip package structure 100. Of course, metal wires may also be used to electrically connect the chip 30 to the circuit board.
In an alternative embodiment, a gap is formed between every two of the solder balls 31, and the gap is filled with transparent adhesive. Here, in order to further stabilize the connection structure of the chip 30, after the chip 30 is soldered, transparent adhesive is filled between the chip 30 and the substrate 10, so that gaps between every two of the solder balls 31 are also filled, and of course, the transparent adhesive may be filled in the peripheral gap of the chip 30, and the transparent adhesive can play a role in connecting the substrate 10 and the chip 30, and is connected with the solder balls 31, so as to further improve the stability of the connection structure, and ensure that the chip 30 is stably mounted.
In an alternative embodiment, the substrate 10 further has a second surface 13, and the second surface 13 is provided with a plurality of pads 131 disposed at intervals in a protruding manner.
In this embodiment, in order to fix the substrate 10, the substrate 10 is provided with the pads 131 on the second surface 13, and the substrate 10 and the device are fixed by soldering through the pads 131, so that the stable mounting of the substrate 10 is realized, and the stability of the chip packaging structure 100 and the stability of the electrical signal transmission are also ensured. Of course, the base plate 10 may be fixed by a screw connection, a snap connection, or the like.
Referring to fig. 2 to 4, specifically, the steps of the processing method of all the embodiments are as follows:
firstly, providing a clean substrate 10, mounting a connector 50 and a passive device 90 on a first surface 11 of the substrate 10 through a surface mounting process, connecting a flip chip 30 to the first surface 11 in a tin ball mounting mode, arranging the substrate 10, the chip 30 and the passive device 90 at intervals, and filling transparent adhesive into a gap between the chip 30 and the substrate 10 after the chip 30 is connected;
then, attaching a protective member 60 to a surface of the connector 50 opposite to the substrate 10, where the protective member 60 can be attached by an automatic film attaching device, where a surface area of the protective member 60 is equal to a surface area of the connector 50, so that the protective member 60 completely covers the connector 50, and then forming a molding layer 70 on the first surface 11 by injection molding through a common mold, where the molding layer 70 wraps the chip 30, the connector 50 and the passive device 90, and a shape and a thickness of the molding layer 70 are set according to actual needs;
then, a groove is formed through the positioning point on the periphery of the substrate 10 at a position corresponding to the connector 50 on the surface of the molding layer 70 facing away from the substrate 10 to expose the surface of the protection member 60 and the connector 50 facing away from the substrate 10. Here, the plastic sealing layer 70 may be ablated by a laser, thereby forming the escape groove 71.
Finally, when the connector 50 is required to be connected, the protection member 60 is removed, so that the surface of the connector 50 for connection is exposed, and if the connector 50 is a male connector, the corresponding female connector 80 is inserted into the male connector to be connected therewith, and the other end of the female connector 80 opposite to the male connector is connected to an external device through a lead, thereby realizing signal extraction of the device and the chip 30.
The chip 30 is packaged in the processing mode, the protection piece 60 is attached to the surface of the connector 50, which is far away from the substrate 10, and the method of removing the plastic package material groove by laser ablation is utilized, so that the local plastic package of the substrate 10 of the universal mold is realized, the processing cost of a special mold is saved, the processing cost is effectively saved, the arrangement of the connector 50 is more flexible, and the efficient processing is realized.
The utility model provides an electronic equipment (not shown in the drawing) again, include the casing and locate chip packaging structure 100 in the casing, above-mentioned embodiment is referred to the specific structure of chip packaging structure 100, because this electronic equipment's chip packaging structure 100 has adopted the whole technical scheme of above-mentioned all embodiments, consequently has all beneficial effects that the technical scheme of above-mentioned embodiment brought at least, and it is here no longer repeated.
The electronic device can be a small-sized functional electronic device, such as a wearable electronic device, a sound box or a mobile terminal, or a large-sized electronic device, such as a manufacturing device or a detection device.
The above only is the preferred embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structure changes made by the contents of the specification and the drawings under the inventive concept of the present invention, or the direct/indirect application in other related technical fields are included in the patent protection scope of the present invention.
Claims (10)
1. A chip package structure, comprising:
a substrate having a first surface;
a chip electrically connected to the first surface;
the connector is electrically connected to the first surface and is arranged at a distance from the chip, and a protection piece is arranged on the surface of the connector, which is far away from the substrate; and
and the plastic packaging layer covers the first surface and the chip, an avoiding groove is formed in the surface deviating from the first surface, and at least the surface deviating from the substrate of the protection piece is exposed in the avoiding groove.
2. The chip package structure according to claim 1, wherein a surface area of the shielding member is equal to an area of a surface of the connector attached to the shielding member.
3. The chip packaging structure according to claim 2, wherein the shielding member is a protective tape.
4. The chip package structure according to claim 2, wherein an opening area of the avoiding groove is larger than a surface area of the connector facing away from the substrate.
5. The chip package structure of claim 1, further comprising a passive device electrically connected to the first surface and spaced apart from the chip, the molding compound covering the passive device.
6. The chip package structure of claim 1, wherein the connector is attached to the substrate.
7. The chip package structure according to any one of claims 1 to 6, wherein a surface of the chip facing the substrate is provided with a plurality of solder balls, and the solder balls are connected to the substrate.
8. The chip package structure according to claim 7, wherein a gap is formed between every two of the solder balls, and the gap is filled with a transparent adhesive.
9. The chip package structure of claim 1, wherein the substrate further has a second surface, and the second surface is provided with a plurality of pads disposed at intervals.
10. An electronic device, comprising a housing and a chip packaging structure disposed in the housing, wherein the chip packaging structure is as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021160422.2U CN212113688U (en) | 2020-06-19 | 2020-06-19 | Chip packaging structure and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021160422.2U CN212113688U (en) | 2020-06-19 | 2020-06-19 | Chip packaging structure and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212113688U true CN212113688U (en) | 2020-12-08 |
Family
ID=73614990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021160422.2U Active CN212113688U (en) | 2020-06-19 | 2020-06-19 | Chip packaging structure and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212113688U (en) |
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2020
- 2020-06-19 CN CN202021160422.2U patent/CN212113688U/en active Active
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