CN212111671U - Test carrier plate and test system - Google Patents

Abstract

The embodiment of the application discloses a test carrier plate and a test system. The test carrier plate is used for testing a device to be tested on a board to be tested, the board to be tested is provided with a replaceable device, and the test carrier plate comprises a first substrate and a signal test circuit arranged on the first substrate; the first substrate is provided with a device area and a hollowed-out area, the signal testing circuit is located in the device area, and a hollowed-out structure is arranged in the hollowed-out area and corresponds to the position, where the replaceable device is located, on the board to be tested. The test carrier plate provided by the embodiment of the application can improve the test accuracy and flexibility of the device.

Description

Test carrier plate and test system

Technical Field

The embodiment of the application relates to the technical field of device testing, in particular to a test carrier plate and a test system.

Background

The frequency of the communication system is higher and higher at present, the requirements for the circuit are also improved, and the correct performance and the stable performance of the function of the high-frequency circuit are determined by the signal performance to a great extent as well as the correctness of the circuit principle. Therefore, the test of the current high-speed communication board not only needs to verify the function, but also needs to test the signal performance.

When the signal performance is tested, the transmission of the signal to be tested is realized by inserting the socket of the test carrier plate into the socket on the board to be tested, wherein the chip to be tested and the circuit to be debugged are arranged on the board to be tested, the signal to be tested is transmitted to the socket of the test carrier plate through the socket on the board to be tested, and then the signal is tested through the test carrier plate. In the testing stage, the device in the circuit to be debugged on the board to be tested needs to be replaced for many times to achieve the expected signal performance, during replacement, the socket pair on the board to be tested needs to be pulled out from the socket pair on the testing carrier board, and after replacement, the socket pair on the board to be tested is inserted into the socket pair on the testing carrier board. The signal performance of the board to be tested and the socket are greatly influenced by a large amount of plugging, so that the testing accuracy is influenced.

SUMMERY OF THE UTILITY MODEL

The application provides a test carrier plate and a test system to realize the effect of improving the accuracy and flexibility of device test.

In a first aspect, an embodiment of the present application provides a test carrier plate, where the test carrier plate may be used to test a device to be tested on a board to be tested, where the board to be tested is provided with a replaceable device, and the test carrier plate includes a first substrate and a signal test circuit disposed on the first substrate;

the first substrate is provided with a device area and a hollowed-out area, the signal testing circuit is located in the device area, and a hollowed-out structure is arranged in the hollowed-out area at a position corresponding to the position of the replaceable device on the board to be tested, so that the replaceable device can be replaced or adjusted through the hollowed-out structure and the first substrate.

The test carrier plate mentioned in the embodiment of the present application can be used for testing electronic devices (such as communication equipment, radar chips, etc.) which are detected and communicated by high frequency signals, because when the test carrier plate is used for testing, a board to be tested provided with a device to be tested (such as a millimeter wave radar chip) needs to be fixed on the test carrier plate, and then a part of the device can be shielded, and in the actual test operation process, sometimes the shielded device needs to be replaced or adjusted, the board to be tested needs to be detached from the test carrier plate, the operation is very inconvenient, the device integrated on the board can be damaged in the detaching process, and the service life and the fixing firmness performance of the fixing device can be seriously affected by multiple detaching, and a hollow area is arranged in the test carrier plate in the embodiment of the present application corresponding to the area where the device needs to be adjusted or replaced in the test process, make the tester need adjust or change the device (like electric capacity or crystal oscillator etc.) when the test and need not to dismantle the operation again to when convenient operation, can also avoid on the board integrated device because of dismantling the damage that the operation caused, and then the number of times of significantly reducing dismantlement, thereby effectively promote the life and the fixed firm performance of fixed device.

It should be noted that the hollowed-out structure in the embodiment of the present application may be a hollowed-out area according to the size and shape required for adjusting or replacing the device without affecting the normal operation of the test carrier.

The signal test circuit can be used for receiving test signals such as analog signals, digital signals and/or clock signals from a test board to be tested and transmitting the test signals to test equipment so as to carry out various test operations on the test signals by using the test equipment.

In an optional embodiment, the test carrier may further include a connection module, and the first substrate further has a connection module disposing region; the connection module is positioned in the connection module setting area;

and the board to be tested is connected with the signal testing circuit through the connecting module.

In an alternative embodiment, the connection module may comprise a plurality of plug-in units of different types.

In an alternative embodiment, the plug unit may comprise different types of counter-sockets and shackles.

In an alternative embodiment, the signal testing circuit may include an analog signal circuit unit, a digital signal circuit unit, a clock signal circuit unit, and the like.

In an optional embodiment, the analog signal circuit unit, the digital signal circuit unit and the clock signal circuit unit each include a plurality of hook rings and a plurality of socket bars for corresponding connection with the connection module.

In an optional embodiment, the signal test circuit arrangement area at least partially surrounds the hollow-out area.

In an alternative embodiment, the exchangeable device comprises a crystal oscillator and/or a capacitor.

In a second aspect, an embodiment of the present application further provides a test system, which may include:

the test board to be tested comprises a second substrate, a chip to be tested and a circuit to be debugged, wherein the chip to be tested and the circuit to be debugged are arranged on the second substrate and are mutually connected, and the circuit to be debugged comprises a replaceable device; and

a test carrier according to any one of the preceding claims;

the test board to be tested is fixed on the test carrier board and used for testing the chip to be tested;

the first substrate is provided with a device area and a hollowed-out area, the signal testing circuit is located in the device area, and a hollowed-out structure is arranged at a position, corresponding to the position of the replaceable device on the board to be tested, in the hollowed-out area and used for replacing the replaceable device.

In an optional embodiment, the chip to be tested comprises a millimeter wave radar chip, and the replaceable device comprises a crystal oscillator and/or a capacitor.

In an alternative embodiment, when the board to be tested is fixed on the test carrier board, the replaceable device is disposed on a side of the second substrate adjacent to the first substrate.

In an optional embodiment, when the board to be tested is connected and fixed with the test carrier board for testing, a vertical projection of the replaceable device on a plane where the second substrate is located and a vertical projection of the hollow structure on the plane where the second substrate is located are at least partially overlapped.

The technical scheme that this application embodiment provided, through set up hollow out construction on first base plate, expose the removable device on the examination board of awaiting measuring through hollow out construction, so, need not the connection repeatedly and disconnection test support plate and the examination board of awaiting measuring, can realize the change of the removable device on the examination board of awaiting measuring, not only can avoid the collision that integrated device caused because of the operation of repeated connection and disconnection test support plate and examination board of awaiting measuring on the examination board of awaiting measuring, and then the problem of influencing the device performance, can also avoid simultaneously a large amount of connections and disconnection test support plate and the examination board of awaiting measuring to treat the signal nature of examining the board and influence great problem, realize improving the effect of test accuracy.

Drawings

Fig. 1 is a schematic structural diagram of a test carrier provided in an embodiment of the present application;

fig. 2 is a schematic side view illustrating a relative position between a test carrier and a board to be tested according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another test carrier provided in the embodiment of the present application;

fig. 4 is a schematic structural diagram of another test carrier provided in the embodiment of the present application;

fig. 5 is a schematic structural diagram of a test system according to an embodiment of the present application.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a test carrier board according to an embodiment of the present disclosure, and fig. 2 is a schematic structural diagram of a side surface of a relative position between the test carrier board and a board to be tested according to an embodiment of the present disclosure, as shown in fig. 1 and fig. 2, the test carrier board 100 is used for testing a device to be tested on a board to be tested 200, a replaceable device 210 is disposed on the board to be tested 200, and the test carrier board 100 includes a first substrate 10 and a signal testing circuit 20 disposed on the first substrate; wherein, the first substrate 10 has a device region 11 and a hollow region 12; the signal testing circuit 20 is located in the device region 11, and a hollow structure 30 is disposed in the hollow region 12 corresponding to a position of the replaceable device 210 on the board to be tested 200.

Wherein the board to be tested 200 is connected to the test carrier board 100 (not shown in the figure), and optionally, the connection manner between the board to be tested 200 and the test carrier board 100 includes electrical connection and/or signal connection. When the board 200 is connected to the test carrier board 100, the signal testing circuit 20 receives the test signal such as analog signal, digital signal and/or clock signal from the board 200 and transmits the test signal to the testing equipment (not shown) for testing the signal. Optionally, the test carrier board 100 may be electrically connected to the test equipment through a specific test connector, and transmit the signal to be tested to the test equipment through the specific test connector, so that the test equipment tests the signal to be tested. The test connection may comprise a patch panel, for example.

Specifically, the signal testing circuit 20 transmits a test signal such as an analog signal, a digital signal and/or a clock signal received from the board under test 200 to the testing equipment, so that the testing equipment tests the signal under test, and in the testing stage, the replaceable device on the board under test 200 needs to be debugged and replaced to achieve the expected signal performance. In this embodiment, the hollow structure 30 is disposed on the test carrier plate 100, and the replaceable device 210 on the board 200 to be tested is exposed through the hollow structure 30, so that the replaceable device 210 can be directly replaced without repeatedly connecting and disconnecting the test carrier plate 100 and the board 200 to be tested, thereby avoiding a large amount of connection and disconnection of the test carrier plate 100 and the board 200 to be tested from greatly affecting the signal of the board to be tested, and achieving the effect of improving the test accuracy.

It should be noted that the size and shape of the hollow-out structure 30 are not specifically limited in this embodiment, as long as the replaceable device 210 on the board to be tested 200 can be exposed. Fig. 1 illustrates only the hollow structure 30 having a rectangular shape.

It should be noted that, in the present embodiment, a specific position of the signal testing circuit 20 is not limited, and fig. 1 is only an embodiment, and does not constitute a limitation to the present application.

The specific type of the test board 200 may be various in actual products. Different types of boards 200 to be tested differ from one device to another in the signal testing circuits 20 in the corresponding test carrier board 100. In the following, a typical example is described in detail, in which the board to be tested 200 is a radar antenna board, a device to be tested on the radar antenna board includes a chip to be tested, the chip to be tested may be a radar chip (e.g., an FMCW millimeter wave radar chip), and the replaceable device 210 is a crystal oscillator and a peripheral circuit. None of the following is a limitation of the present application. As long as the device needs to be replaced during the test, the hollow structure 30 may be disposed in the test carrier 100.

Exemplarily, a signal testing circuit 20 on a test carrier board 100 receives a signal to be tested output by a radar antenna board, wherein the signal to be tested includes an analog signal, a digital signal and/or a clock signal, and the signal to be tested is transmitted to a testing device through the signal testing circuit 20, so that the testing device tests the signal to be tested, and in a testing stage, a crystal oscillator and a peripheral circuit on the radar antenna board need to be debugged and replaced to achieve an expected signal performance of a radar chip, because a hollow structure 30 is arranged on the test carrier board 100, the crystal oscillator and the peripheral circuit on the radar antenna board are exposed through the hollow structure 30, so that when the crystal oscillator itself provides the clock signal, the crystal oscillator or an adaptive capacitor can be directly replaced; when an external signal source provides a clock signal, the crystal oscillator connecting circuit can be directly disconnected through the resistor and the capacitor without repeatedly connecting and disconnecting the test carrier plate 100 and the radar antenna plate, so that the problem that the performance of a signal to be tested output by a radar chip on the radar antenna plate is greatly influenced by a large number of connection and disconnection test carrier plates 100 and the radar antenna plate is solved, and the effect of improving the test accuracy is realized.

On the basis of the above solution, optionally, fig. 3 is a schematic structural diagram of another test carrier provided in the embodiment of the present application, and as shown in fig. 3, the first substrate 10 further includes: a connection module 40, the first substrate 10 further having a connection module disposition region 13; the connection module 40 is located in the connection module setting area 13; wherein, the board to be tested 200 is connected to the signal testing circuit 20 through the connection module 40.

The signal testing circuit 20 receives a test signal waiting for the test board 200, such as an analog signal, a digital signal and/or a clock signal, through the connection module 40.

Optionally, fig. 4 is a schematic structural diagram of another test carrier provided in the embodiment of the present application, and as shown in fig. 4, the connection module 40 includes a plurality of plug units 41 with different types.

The plurality of plug-in units 41 with different types can meet the test requirements of different chips to be tested in different boards to be tested, i.e. the test carrier board is compatibly arranged, so that most boards to be tested can be compatibly tested, and the boards can be reused, thereby achieving the optimization of cost.

Optionally, the inserting unit 41 may include, for example, a socket and a hook ring, and correspondingly, the socket and the hook ring are also provided in the board 200 to be tested, so that transmission of a signal to be tested can be realized through the socket, and meanwhile, a fixed support effect can be exerted on the board 200 to be tested and the test carrier board 100, so that stability of signal transmission is further improved, test accuracy is improved, and extraction of the signal to be tested is facilitated. Optionally, when the plugging unit 41 is a socket, the first substrate 10 is provided with the hollow structure 30 to expose the replaceable device 210 to be tested on the board 200, so that the replaceable device 210 can be directly replaced without repeated plugging and unplugging to the socket, which not only can avoid the problem that a large amount of plugging and unplugging affects the signal performance of the socket to be tested greatly, but also can avoid the problem that a large amount of plugging and unplugging affects the performance of the socket.

Illustratively, the connection module arrangement area 13 is provided with two plug units 41, the plug units 41 being J1 pairs of receptacles and J2 pairs of receptacles, respectively. The test board 200 is a radar antenna board, the radar antenna board comprises a radar chip, and when the type of the radar chip is 2T4R, a pair of sockets on the radar antenna board need to be connected to J1 pairs of sockets of the test carrier board; when the type of the radar chip is 4T8R, the pair of sockets on the radar antenna board needs to be connected to the J1 pair of sockets and the J2 pair of sockets of the test carrier board at the same time. That is, the test carrier 100 can be compatible with testing most of the radar antenna boards, and can be reused, thereby achieving the cost optimization.

It should be noted that the number and the type of the plugging units 41 can be set according to the type of the chip to be tested in the board to be tested 200, the embodiment is not particularly limited, and fig. 4 only illustrates that two plugging units 41 are disposed in the connection module disposing area 13.

Alternatively, with continued reference to fig. 4, the signal test circuit 20 includes an analog signal circuit unit 21, a digital signal circuit unit 22, and a clock signal circuit unit 23.

The analog signal circuit unit 21 receives the analog signal from the board 200 and transmits the analog signal to the testing device, so as to perform a testing operation on the analog signal by using the testing device. The digital signal on the board to be tested 200 is received by the digital signal circuit unit 22 and transmitted to the testing device, so that the testing device can be used to perform the testing operation on the digital signal. The clock signal circuit unit 23 receives the clock signal from the board 200 and transmits the clock signal to the testing device, so as to test the clock signal by using the testing device.

It should be noted that the test for the analog signal, the digital signal, and the clock signal waiting test signal may be performed simultaneously, or a signal may be tested separately.

Optionally, the signal testing circuit 20 further includes: a power supply unit 50; the power unit 50 is used for sending a power signal to the board to be tested 200, so that the board to be tested 200 starts to operate according to the power signal.

It will be understood by those skilled in the art that fig. 4 simply shows the relative positional relationship among the power supply unit 50, the analog signal circuit unit 21, the digital signal circuit unit 22, and the clock signal circuit unit 23, and hereinafter, the power supply unit 50, the analog signal circuit unit 21, the digital signal circuit unit 22, and the clock signal circuit unit 23 are also shown in the drawings, but in practice, the power supply unit 50, the analog signal circuit unit 21, the digital signal circuit unit 22, and the clock signal circuit unit 23 include other signal lines, devices, and the like, which are not shown again.

It is also understood that fig. 4 shows only one positional relationship of the power supply unit 50, the analog signal circuit unit 21, the digital signal circuit unit 22, and the clock signal circuit unit 23, but does not constitute a limitation of the present application.

It should be noted that the circuits in the signal test circuit 20 can be adjusted according to the signals to be tested, and are not limited to the analog signal circuit unit 21, the digital signal circuit unit 22, and the clock signal circuit unit 23.

On the basis of the above scheme, optionally, with reference to fig. 4, the analog signal circuit unit 21, the digital signal circuit unit 22, and the clock signal circuit unit 23 each include a plurality of hook rings 50 and a plurality of power strips 60 for corresponding connection with the connection module 40.

According to the scheme, a large number of hook rings 60 and the power strip 70 are added, so that signals to be tested can be conveniently and directly extracted.

On the basis of the above scheme, optionally, with continued reference to fig. 1, the signal test circuit arrangement region 11 at least partially surrounds the hollow-out region 12.

The signal testing circuit setting area 11 can be arranged around the hollow area 12; or may partially surround the hollowed-out area 12. When the signal testing circuit setting area 11 at least partially surrounds the hollow area 12, that is, the hollow area 12 is located at one corner of the first substrate 10, the testing of the signal to be tested is not affected.

Fig. 5 is a schematic structural diagram of a test system according to an embodiment of the present disclosure, as shown in fig. 5, the test system includes a board to be tested 200, where the board to be tested 200 includes a second substrate 220, and a chip to be tested 230 and a circuit to be debugged 240 that are disposed on the second substrate 220 and are connected to each other; the circuit to be debugged 240 includes the replaceable device 210; and, a test carrier board 100 as in any of the above embodiments; it should be noted that, in order to clearly show the structure on the test carrier board 100 and the structure on the board 200 to be tested, fig. 5 does not show the position relationship between the board 200 to be tested and the test carrier board 100, and the test carrier board 100 is used to test the chip 230 to be tested; the first substrate 10 has a device region 11 and a hollow-out region 12, the signal testing circuit 20 is located in the device region 11, and a hollow-out structure 30 is disposed in the hollow-out region 12 at a position corresponding to a position of a replaceable device 210 on the board 200 to be tested, for replacing the replaceable device 210.

The chip 230 to be tested includes a millimeter wave radar chip, and the replaceable device 210 includes a crystal oscillator and/or a capacitor. It is to be understood that the chip under test and the replaceable device are not limited thereto.

Optionally, when the board to be tested 200 is fixed on the test carrier 100, the replaceable device 210 is disposed on a side of the second substrate 220 adjacent to the first substrate 10.

In this embodiment, the hollow structure 30 is disposed on the test carrier plate 100, and the replaceable device 210 on the board 200 to be tested is exposed through the hollow structure 30, so that the replaceable device 210 can be directly replaced without repeatedly connecting and disconnecting the test carrier plate 100 and the board 200 to be tested, thereby avoiding a large amount of connection and disconnection of the test carrier plate 100 and the board 200 to be tested from greatly affecting the signal of the board to be tested, and achieving the effect of improving the test accuracy.

The embodiment of the utility model provides a concrete realization of each component of test system can refer to the content of above-mentioned other embodiments, no longer gives unnecessary details here.

Optionally, with continued reference to fig. 5, the shape of the board to be tested 200 is the same as the test carrier board 100, and the size of the board to be tested 200 is the same as the test carrier board 100.

In consideration of the fact that if the board 200 to be tested is large, it will extend beyond the test carrier board 100, the board 200 to be tested cannot be well fixed to the test carrier board 100 through the screw holes. Therefore, in the embodiment, by setting the shapes of the board to be tested 200 and the test carrier board 100 to be the same, and the sizes of the board to be tested 200 and the test carrier board 100 to be the same, that is, adjusting the size and the shape of the test carrier board 100 properly for different boards to be tested 200, the board to be tested 200 and the test carrier board 100 can be fixed well by the screw holes, the stability of signal transmission is further improved, and the test accuracy is improved.

It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.

Claims (10)

1. A test carrier plate is characterized in that the test carrier plate is used for testing a device to be tested on a board to be tested, replaceable devices are arranged on the board to be tested, and the test carrier plate comprises a first substrate and a signal test circuit arranged on the first substrate;

the first substrate is provided with a device area and a hollowed-out area, the signal testing circuit is located in the device area, and a hollowed-out structure is arranged in the hollowed-out area and corresponds to the position, where the replaceable device is located, on the board to be tested.

2. The test carrier of claim 1, further comprising a connection module, wherein the first substrate further comprises a connection module placement area; the connection module is positioned in the connection module setting area;

and the board to be tested is connected with the signal testing circuit through the connecting module.

3. The test carrier of claim 2, wherein the connection modules comprise a plurality of different types of plug-in units.

4. The test carrier of claim 3, wherein the plug units comprise different types of mating sockets and hook rings.

5. The test carrier of claim 2, wherein the signal test circuit comprises an analog signal circuit unit, a digital signal circuit unit and a clock signal circuit unit.

6. The test carrier of claim 5, wherein the analog signal circuit unit, the digital signal circuit unit and the clock signal circuit unit each comprise a plurality of hook rings and a plurality of socket bars for corresponding connection with the connection module.

7. The test carrier of claim 1, wherein the signal test circuit layout area at least partially surrounds the hollow area.

8. The test carrier of claim 1, wherein the replaceable device comprises a crystal oscillator and/or a capacitor.

9. A test system, comprising:

the test board to be tested comprises a second substrate, a chip to be tested and a circuit to be debugged, wherein the chip to be tested and the circuit to be debugged are arranged on the second substrate and are mutually connected, and the circuit to be debugged comprises a replaceable device; and

the test carrier of any one of claims 1-8;

the test board to be tested is fixed on the test carrier board and used for testing the chip to be tested;

the first substrate is provided with a device area and a hollowed-out area, the signal testing circuit is located in the device area, and a hollowed-out structure is arranged at a position, corresponding to the position of the replaceable device on the board to be tested, in the hollowed-out area and used for replacing the replaceable device.

10. The test system of claim 9, wherein the interchangeable device is located on a side of the second substrate adjacent to the first substrate when the board to be tested is mounted on the test carrier board.

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