CN212034479U - Interposer and electronic device - Google Patents

Interposer and electronic device Download PDF

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Publication number
CN212034479U
CN212034479U CN201890001332.3U CN201890001332U CN212034479U CN 212034479 U CN212034479 U CN 212034479U CN 201890001332 U CN201890001332 U CN 201890001332U CN 212034479 U CN212034479 U CN 212034479U
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China
Prior art keywords
mounting surface
interposer
interlayer connection
conductor
laminate
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CN201890001332.3U
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Chinese (zh)
Inventor
饭田汗人
小山展正
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

The utility model provides an interposer and electronic equipment who possesses this interposer. The interposer is provided with: a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are opposed to each other; a plurality of conductor patterns formed on the laminated body and extending in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface; an interlayer connection conductor formed in the laminate body and extending in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, the interlayer connection conductor connecting the plurality of conductor patterns to each other; a1 st electrode formed on the 1 st mounting surface; and a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor, wherein the 1 st mounting surface and the 2 nd mounting surface are surfaces parallel to a stacking direction of the plurality of insulating base material layers, and a length in the 1 st direction between the 1 st mounting surface and the 2 nd mounting surface is longer than a total length in the 2 nd direction of the interlayer connection conductor.

Description

Interposer and electronic device
Technical Field
The present invention relates to an interposer for connecting a plurality of members each forming a predetermined circuit to each other, and an electronic apparatus including the interposer.
Background
As a circuit board and an electronic component included in an electronic device are highly integrated, and as a circuit board having different wiring densities is mixed, a structure in which a plurality of circuit boards are electrically connected to each other via an interposer may be adopted as necessary.
For example, patent document 1 discloses a structure in which an interposer is sandwiched between a1 st member (1 st circuit board) and a2 nd member (2 nd circuit board) and electrically connected via the interposer, wherein the 1 st member (1 st circuit board) and the 2 nd member (2 nd circuit board) are arranged apart in a thickness direction. The interposer is configured such that a wiring for connecting the 1 st member and the 2 nd member is formed by a conductor pattern formed in a laminate of a plurality of insulating base material layers and an interlayer connection conductor formed in the laminate and extending in the thickness direction (the lamination direction of the plurality of insulating base material layers, the direction in which the 1 st member and the 2 nd member are separated).
Prior art documents
Patent document
Patent document 1: international publication No. 2014/002592
SUMMERY OF THE UTILITY MODEL
Problem to be solved by utility model
However, in the structure shown in patent document 1, when an interposer having a large thickness (thickness in the stacking direction of the plurality of insulating base material layers) is required, the following problems occur.
(a) It is difficult to form an interlayer connection conductor having a shape elongated in the thickness direction by using, for example, a plating method.
(b) In the case of a laminate having a large number of stacked insulating base material layers, a method of forming an interlayer connection conductor having a shape elongated in the thickness direction by connecting a plurality of via conductors (for example, via conductors obtained by filling an opening formed in an insulating base material layer with a conductive paste and curing the conductive paste by a heat and pressure treatment) to each other is conceivable. However, in this case, the number of necessary via conductors increases, and the connection positions of the via conductors increase, thereby lowering the electrical connection reliability.
An object of the present invention is to provide an interposer that can improve the reliability of electrical connection of a wiring between a1 st member and a2 nd member by a simple structure even when a thickness dimension (a distance between the 1 st member and the 2 nd member) is large, and an electronic apparatus including the interposer.
Means for solving the problems
(1) The utility model discloses an interposer is disposed between 1 st component and 2 nd component and will the 1 st component with the interposer that the 2 nd component electricity is connected, its characterized in that possesses:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are opposed to each other;
a plurality of conductor patterns formed on the laminate and extending in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface;
an interlayer connection conductor formed in the laminate body and extending in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, the interlayer connection conductor connecting the plurality of conductor patterns to each other;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the 1 st mounting surface and the 2 nd mounting surface are surfaces parallel to a stacking direction of the plurality of insulating base material layers,
the length in the 1 st direction between the 1 st mounting surface and the 2 nd mounting surface is longer than the total length in the 2 nd direction of the interlayer connection conductor.
(2) The utility model discloses an interposer is disposed between 1 st component and 2 nd component and will the 1 st component with the interposer that the 2 nd component electricity is connected, its characterized in that possesses:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are parallel to each other;
a plurality of conductor patterns formed on the laminate;
an interlayer connection conductor formed on the laminate;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the laminate has a rising portion in which the direction of lamination of the plurality of insulating base material layers is parallel to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the plurality of conductor patterns extend in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the interlayer connection conductor extends in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, and connects the plurality of conductor patterns to each other,
in the standing portion, a length in the 1 st direction is longer than a total length in the 2 nd direction of the interlayer connection conductor.
In this structure, a relatively long wiring extending in the 1 st direction (the direction in which the 1 st member and the 2 nd member are separated) is formed by the conductor pattern. Therefore, as compared with the case where a long wiring extending in the 1 st direction is formed by the interlayer connection conductor, an interposer with high reliability of electrical connection of wirings connecting the 1 st electrode and the 2 nd electrode can be easily realized.
(3) In the above (2), one of the 1 st mounting surface and the 2 nd mounting surface may be an end surface of the laminate parallel to the lamination direction.
(4) Preferably, in any one of the above (1) to (3), the plurality of conductor patterns and the interlayer connection conductor are connected by solid-phase diffusion bonding. With this configuration, the bonding strength between the conductor pattern and the interlayer connection conductor can be improved by an easy manufacturing method, compared to a case where an interlayer connection conductor connected to a plurality of conductor patterns is formed by plating or the like.
(5) Preferably, in any one of the above (1) to (3), the interlayer connection conductor is a metal formed by plating. According to this configuration, compared to the case where the interlayer connection conductor is a via conductor formed by curing a conductive paste, the conductor loss of the wiring (signal line) connecting the 1 st electrode and the 2 nd electrode can be further reduced.
(6) Preferably, in any one of the above (1) to (4), the plurality of insulating base material layers are made of a resin as a main material, and the interlayer connection conductor includes a resin material. In general, a via conductor obtained by curing a conductive paste contains a resin component, and therefore has higher bonding strength to an insulating base material layer mainly composed of a resin than through hole plating or the like which is a simple metal. Therefore, the bonding strength between the interlayer connection conductor and the insulating base layer is improved as compared with the case where the interlayer connection conductor is formed by a plating method. Therefore, an interposer with high mechanical strength and high electrical connection reliability can be realized.
(7) Preferably, in any one of the above (1) to (6), the plurality of insulating base material layers are made of resin as a main material, the interlayer connection conductors are formed in a plurality of different insulating base material layers, and the plurality of interlayer connection conductors are arranged at positions not overlapping with each other when viewed from the 2 nd direction. Generally, a laminate formed by laminating a plurality of insulating base material layers mainly made of resin is easily deformed by external force, impact, or the like. In addition, when a plurality of interlayer connection conductors are continuously arranged in the laminate, stress is concentrated on the interlayer connection conductors when the laminate is deformed, and the interlayer connection conductors are easily damaged due to displacement. On the other hand, according to this structure, since the plurality of interlayer connection conductors are not continuously arranged in the stacking direction, when an external force, an impact, or the like is applied to the stacked body, stress applied to each interlayer connection conductor is dispersed. Therefore, even when an external force or the like is applied to the laminate, damage or the like of the interlayer connection conductor can be suppressed, and the connection reliability of the interlayer connection conductor with respect to the external force can be improved.
(8) Preferably, any one of the above (1) to (7) further includes: and a planar conductor formed on the laminate, wherein at least a part of the plurality of conductor patterns overlaps the planar conductor when viewed from the 2 nd direction. According to this configuration, by the shielding effect by the planar conductor, unnecessary radiation from the signal line (the plurality of conductor patterns or the interlayer connection conductor) can be suppressed or an influence of noise from the outside on the signal line can be suppressed with respect to an article or the like located in at least one of the 2 nd direction as viewed from the interposer. Further, according to this configuration, when the stacking direction of the plurality of insulating base material layers forming the stacked body is parallel to the 1 st direction (the direction in which the 1 st member and the 2 nd member are separated), the shielding property against the signal line is improved as compared with a configuration in which a plurality of interlayer connection conductors extending in the 1 st direction are arranged around the signal line (on the 2 nd direction side with respect to the signal line). Therefore, the isolation between the signal line and the outside can be improved.
(9) Preferably, in the above (8), the number of the planar conductors is plural, and the plural planar conductors are arranged at positions sandwiching the plural conductor patterns or the interlayer connection conductors in the 2 nd direction. According to this configuration, the shielding effect by the planar conductor is further improved for both sides of the signal line in the 2 nd direction. Therefore, when the articles and the like located on both sides in the 2 nd direction are viewed from the interposer, the unwanted radiation from the signal line (the plurality of conductor patterns or the interlayer connection conductor) can be further suppressed, or the influence of noise from the outside on the signal line can be further suppressed.
(10) Preferably, in any one of the above (1) to (9), the plurality of insulating base material layers are composed of a thermoplastic resin. With this configuration, it is possible to realize an interposer that can be easily plastically deformed and can maintain (hold) a desired shape. Further, according to this structure, the interposer can be easily deformed into a desired shape, and therefore, even when high dimensional accuracy is required for the interposer, the interposer can be easily connected to the 1 st member or the 2 nd member.
(11) The utility model discloses an electronic equipment's characterized in that possesses:
a1 st member;
a2 nd member; and
an interposer disposed between the 1 st member and the 2 nd member, electrically connecting the 1 st member and the 2 nd member;
the interposer has:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are opposed to each other;
a plurality of conductor patterns formed on the laminate and extending in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface;
an interlayer connection conductor formed in the laminate body and extending in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, the interlayer connection conductor connecting the plurality of conductor patterns to each other;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the 1 st mounting surface and the 2 nd mounting surface are surfaces parallel to a stacking direction of the plurality of insulating base material layers,
a length in the 1 st direction between the 1 st mounting surface and the 2 nd mounting surface is longer than a total length in the 2 nd direction of the interlayer connection conductors,
the 1 st electrode is electrically connected to the 1 st member, and the 2 nd electrode is electrically connected to the 2 nd member.
(12) The utility model discloses an electronic equipment's characterized in that possesses:
a1 st member;
a2 nd member; and
an interposer disposed between the 1 st member and the 2 nd member, electrically connecting the 1 st member and the 2 nd member;
the interposer has:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are parallel to each other;
a plurality of conductor patterns formed on the laminate;
an interlayer connection conductor formed on the laminate;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the laminate has a rising portion in which the direction of lamination of the plurality of insulating base material layers is parallel to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the plurality of conductor patterns extend in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the interlayer connection conductor extends in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, and connects the plurality of conductor patterns to each other,
a length in the 1 st direction is longer than a total length in the 2 nd direction of the interlayer connection conductor in the standing portion,
the 1 st electrode is electrically connected to the 1 st member, and the 2 nd electrode is electrically connected to the 2 nd member.
According to this structure, an electronic apparatus can be realized in which the reliability of electrical connection of the wiring between the 1 st member and the 2 nd member can be improved even when the thickness dimension (the distance between the 1 st member and the 2 nd member) is large.
(13) Preferably, in the above (11) or (12), the effective elastic modulus of the laminate is smaller than that of the 1 st member and the 2 nd member. According to this structure, since the interposer has higher flexibility than the 1 st member and the 2 nd member, breakage of the joint portion due to stress applied to the 1 st member and the 2 nd member can be suppressed.
(14) Any one of the above (11) to (13) may further include: and a component mounted on the 1 st member or the 2 nd member and disposed between the 1 st member and the 2 nd member.
(15) Preferably, in the above (14), the interposer has a planar conductor formed in the laminate, and at least a part of the planar conductor is located between the plurality of conductor patterns and the member. According to this configuration, the shielding effect of the planar conductor against the member is improved, unnecessary radiation from the signal line (the plurality of conductor patterns or the interlayer connection conductor) to the member can be suppressed, and the influence of noise from the member on the signal line can be suppressed.
Effect of the utility model
According to the present invention, an interposer capable of improving the reliability of electrical connection of wiring between the 1 st member and the 2 nd member by a simple structure even when the thickness dimension (the distance between the 1 st member and the 2 nd member) is large can be realized. Further, an electronic device provided with the interposer can be realized.
Drawings
Fig. 1 is a sectional view of an interposer 301 according to embodiment 1.
Fig. 2 is a sectional view showing a main part of an electronic device 401 according to embodiment 1.
Fig. 3 is a sectional view sequentially showing the manufacturing process of the interposer 301.
Fig. 4 is a sectional view of the interposer 302 according to embodiment 2.
Fig. 5 is a sectional view showing the manufacturing process of the interposer 302 in order.
Fig. 6 is a sectional view of the interposer 303 according to embodiment 3.
Fig. 7 is an exploded top view of interposer 303.
Fig. 8 is a sectional view showing a main part of an electronic apparatus 403 according to embodiment 3.
Fig. 9 is a sectional view of the interposer 304 according to embodiment 4.
Fig. 10 is a sectional view of interposer 305 according to embodiment 5.
Fig. 11 is a sectional view showing a state before bending of interposer 305.
Detailed Description
Hereinafter, a plurality of modes for carrying out the present invention will be described with reference to the drawings and by way of specific examples. In the drawings, the same reference numerals are given to the same parts. The embodiments are separately shown for convenience in view of ease of explanation or understanding of the points, but partial replacement or combination of the structures shown in different embodiments can be made. In embodiment 2 and thereafter, descriptions of common matters with embodiment 1 are omitted, and only differences will be described. In particular, the same operational effects based on the same structure will not be mentioned in each embodiment.
EXAMPLE 1 embodiment
Fig. 1 is a sectional view of an interposer 301 according to embodiment 1.
The interposer of the present invention is disposed (sandwiched) between the 1 st member and the 2 nd member, and electrically connects the 1 st member and the 2 nd member. The electronic device of the present invention is a device including the interposer of the present invention, and examples thereof include a mobile phone terminal, a so-called smart phone, a tablet terminal, a notebook PC, a PDA, a wearable terminal (a so-called smart watch, smart glasses, and the like), a camera, a game machine, and a toy.
The interposer 301 includes a laminate 10, a plurality of conductor patterns 21 and 22, an interlayer connection conductor V1, a1 st electrode P1, and a2 nd electrode P2.
The laminate 10 is a rectangular parallelepiped insulator in which a plurality of flexible insulating base layers 11, 12, and 13 are laminated. The laminate 10 has a1 st main surface MS1 and a2 nd main surface MS2 opposed to each other. The 1 st main surface MS1 and the 2 nd main surface MS2 are surfaces perpendicular to the lamination direction (Z-axis direction) of the plurality of insulating base material layers 11, 12, 13. The laminate 10 has end surfaces SS1 and SS2 facing each other. The end surfaces SS1 and SS2 are surfaces (end surfaces of the laminate 10) parallel to the lamination direction (Z-axis direction). The insulating base material layers 11, 12, and 13 are sheets made of thermoplastic resin such as Liquid Crystal Polymer (LCP) or polyether ether ketone (PEEK), for example.
In the present embodiment, the end surface SS1 corresponds to the "1 st attachment surface" in the present invention, and the end surface SS2 corresponds to the "2 nd attachment surface" in the present invention.
The plurality of conductor patterns 21 and 22 are formed in the laminate 10 and extend in the 1 st direction (for example, the X-axis direction shown in fig. 1) perpendicular to the end surface SS1 (1 st mounting surface) and the end surface SS2 (2 nd mounting surface). The plurality of conductor patterns 21 and 22 are conductor patterns such as Cu foils.
The interlayer connection conductor V1 is a conductor formed in the laminate 10 and extending in the 2 nd direction (the Z-axis direction shown in fig. 1) parallel to the end surface SS1 (the 1 st mounting surface) and the end surface SS2 (the 2 nd mounting surface), and the interlayer connection conductor V1 connects the plurality of conductor patterns 21 and 22 to each other. The interlayer connection conductor V1 is, for example, a metal (e.g., Cu) formed by electroless plating.
The 1 st electrode P1 is a conductor formed on the end surface SS1 (1 st mounting surface), and the 2 nd electrode P2 is a conductor formed on the end surface SS2 (2 nd mounting surface). The 1 st electrode P1 and the 2 nd electrode P2 are electrically connected via the plurality of conductor patterns 21, 22 and the interlayer connection conductor V1. Specifically, the 1 st electrode P1 is connected to one end of the conductor pattern 21. The other end of the conductor pattern 21 is connected to one end of the conductor pattern 22 via the interlayer connection conductor V1, and the other end of the conductor pattern 22 is connected to the 2 nd electrode P2. The 1 st electrode P1 and the 2 nd electrode P2 are plating films of Cu or the like formed by electroless plating (or electroplating), for example.
In this manner, in the present embodiment, the wiring (signal line) for connecting the 1 st electrode P1 and the 2 nd electrode P2 is formed by the plurality of electrically connected conductor patterns 21 and 22 and the interlayer connection conductor V1.
As shown in fig. 1, the length La1 in the X axis direction (1 st direction) between the end surface SS1 (1 st mounting surface) and the end surface SS2 (2 nd mounting surface) is longer than the total length Lb1 in the Z axis direction (2 nd direction) of the interlayer connection conductor V1 (La1 > Lb 1). In other words, among the wirings connecting the 1 st electrode P1 and the 2 nd electrode P2, the length of the wiring (the electrical path of the plurality of conductor patterns 21 and 22) extending in the 1 st direction (X-axis direction) is longer than the length of the wiring (the interlayer connection conductor V1) extending in the 2 nd direction (Z-axis direction).
Next, an electronic device including the interposer 301 according to the present invention will be described with reference to the drawings. Fig. 2 is a sectional view showing a main part of an electronic device 401 according to embodiment 1.
The electronic device 401 includes the 1 st circuit board 101, the 2 nd circuit board 201, the interposer 301, the components 81 and 91, and the like. The 1 st circuit board 101 and the 2 nd circuit board 201 are disposed apart from each other in the 1 st direction (X-axis direction), and the interposer 301 and the components 81 and 91 are disposed (sandwiched) between the 1 st circuit board 101 and the 2 nd circuit board 201. The 1 st circuit board 101 and the 2 nd circuit board 201 are, for example, glass/epoxy boards. The components 81 and 91 are chip components such as chip inductors and chip capacitors, RFIC elements, impedance matching circuits, and the like.
In the present embodiment, the 1 st circuit board 101 corresponds to the "1 st member" in the present invention, and the 2 nd circuit board 201 corresponds to the "2 nd member" in the present invention.
As shown in fig. 2, the interposer 301 and the component 81 are mounted on the upper surface S1 of the 1 st circuit board 101. The component 91 is mounted on the lower surface S2 of the 2 nd circuit board 201. The interposer 301 is connected to the 1 st circuit board 101 and the 2 nd circuit board 201 in an upright state (a state in which the end surface SS1 (the 1 st mounting surface) of the laminate 10 faces the 1 st circuit board 101 and the end surface SS2 (the 2 nd mounting surface) of the laminate 10 faces the lower surface S2 of the 2 nd circuit board 201).
A plurality of lands 61, 62, 63 are formed on the upper surface S1 of the 1 st circuit board 101. The 1 st electrode P1 of the interposer 301 is directly soldered to the land 61. Thereby, the 1 st electrode P1 of the interposer 301 is electrically connected to the 1 st circuit substrate 101 (the 1 st member). The terminals of the member 81 are directly soldered to the lands 62 and 63, respectively.
A plurality of lands 71, 72, 73 are formed on the lower surface S2 of the 2 nd circuit board 201. The 2 nd electrode P2 of the interposer 301 is directly soldered to the land 71. Thereby, the 2 nd electrode P2 of the interposer 301 is electrically connected to the 2 nd circuit board 201 (the 2 nd member). The terminals of the member 91 are directly soldered to the lands 72 and 73, respectively.
In the present embodiment, the effective elastic modulus of the interposer 301 is smaller than the effective elastic modulus of the 1 st circuit board 101 and the 2 nd circuit board 201. For example, the Young's modulus of a glass/epoxy substrate is about 25 GPa. On the other hand, the young's modulus of the Liquid Crystal Polymer (LCP) of the laminate 10 as the interposer 301 is about 15 GPa.
The "effective elastic modulus" in the present specification is not limited to the "elastic modulus" of a single material, and refers to the "elastic modulus" of the entire composite material (composite material composed of a resin, a conductor pattern, an interlayer connection conductor, an adhesive, and the like).
The interposer 301 and the electronic device 401 according to the present embodiment provide the following effects.
(a) In the present embodiment, of the wirings between the 1 st electrode P1 and the 2 nd electrode P2, a relatively long wiring extending in the 1 st direction (X-axis direction. the direction in which the 1 st member and the 2 nd member are separated) is formed by the conductor patterns 21, 22. In the case of a typical interposer (an interposer including a laminate in which a plurality of insulating base material layers are laminated in the 1 st direction), wirings extending in the 1 st direction are formed by interlayer connection conductors such as via hole plating and via conductors (via conductors obtained by curing a conductive paste). In particular, when a long wiring extending in the 1 st direction is formed by through-hole plating, it is necessary to form a long and thin through-hole, and it is difficult to form a through-hole and to perform plating. In addition, when a long wiring extending in the 1 st direction is formed by a via conductor, a process of forming openings in each of the plurality of insulating base material layers and filling the openings with a conductive paste becomes necessary, and the manufacturing process becomes complicated. According to the above configuration, compared to the case where a long wiring extending in the 1 st direction is formed by an interlayer connection conductor (through-hole plating, via conductor), an interposer with high reliability of electrical connection of a signal line (wiring connecting between the 1 st electrode P1 and the 2 nd electrode P2) can be realized with a simple configuration.
(b) As described above, in the present embodiment, the long wiring extending in the 1 st direction of the signal line (the wiring connecting the 1 st electrode P1 and the 2 nd electrode P2) is formed by the conductor patterns 21 and 22. In general, the volume resistivity of a via conductor obtained by curing a conductive paste is higher than that of a conductor pattern (metal simple substance). Therefore, if all of the long wirings extending in the 1 st direction are formed of via conductors as in a normal interposer, the conductor loss increases. On the other hand, the conductor pattern can be easily adjusted in line width, and therefore conductor loss can be easily reduced by widening the line width of the conductor pattern. Therefore, with the above configuration, the conductor loss of the signal line can be easily reduced as compared with the case where a long wiring extending in the 1 st direction is formed by the via conductor.
(c) In this embodiment, the interlayer connection conductor V1 is plated with a through hole. With this configuration, compared to the case where the interlayer connection conductor is a via conductor formed by curing a conductive paste, the conductor loss of the signal line (the wiring connecting between the 1 st electrode P1 and the 2 nd electrode P2) can be further reduced.
(d) In the present embodiment, the interposer 301 is sandwiched between the 1 st member (1 st circuit board 101) and the 2 nd member (2 nd circuit board 201), and the 1 st member and the 2 nd member are electrically connected via the interposer 301. With this configuration, the space for mounting the components 81 and 91 can be secured on the surface of the 1 st member (the upper surface S1 of the 1 st circuit board 101) and the surface of the 2 nd member (the lower surface S2 of the 2 nd circuit board 201), and the 1 st circuit board 101 and the 2 nd circuit board 201 can be electrically connected in a separated state.
(e) In the electronic device according to the present embodiment, the 1 st electrode P1 of the interposer 301 is directly soldered to the land 61 of the 1 st circuit board 101, and the 2 nd electrode P2 of the interposer 301 is directly soldered to the land 71 of the 2 nd circuit board 201. According to this configuration, the interposer 301 and the 1 st circuit board 101 can be joined with almost no unnecessary gap, and therefore the interposer 301 can be disposed even in a narrow space in the electronic apparatus. Further, since there is almost no useless gap between the interposer 301 and the 1 st circuit substrate 101, useless radiation and energy loss due to leakage of electromagnetic waves can be suppressed. Further, according to this configuration, impedance mismatch is less likely to occur and reflection loss can be suppressed, as compared with the case where the interposer is connected to the 1 st circuit board via the connector. The same applies to the connection relationship between the interposer 301 and the 2 nd circuit board 201.
(f) The interposer 301 (laminate 10) according to the present embodiment has an effective elastic modulus smaller than that of the 1 st circuit substrate 101 (1 st member) and the 2 nd circuit substrate 201 (2 nd member), and has flexibility (deformability). According to this configuration, for example, the interposer can be attached to a portion of the 1 st member (or the 2 nd member) where the unevenness is slight. Further, since the interposer 301 has higher flexibility than the 1 st circuit board 101 and the 2 nd circuit board 201, damage to the joint portion (the joint portion between the 1 st electrode P1 and the land 61, and the joint portion between the 2 nd electrode P2 and the land 71) due to stress applied to the 1 st circuit board 101 and the 2 nd circuit board 201 can be suppressed.
In the present embodiment, the plurality of insulating base material layers 11, 12, and 13 forming the laminate 10 are made of a thermoplastic resin. With this configuration, it is possible to realize an interposer that can be easily plastically deformed and can maintain (hold) a desired shape. In addition, in the case where the interposer is directly connected to the 1 st and 2 nd members that are difficult to deform by solder, high dimensional accuracy is required for the interposer. On the other hand, according to the above configuration, since the laminate 10 in which a plurality of sheets made of thermoplastic resin are laminated is used, the interposer has flexibility (deformability), and the interposer is easily deformed into a desired shape. Therefore, in particular, even in the case where high dimensional accuracy is required for the interposer as described above, the interposer is deformed before connection, whereby connection of the 1 st member or the 2 nd member and the interposer becomes easy.
In addition, in the case of a normal interposer (an interposer including a laminate in which a plurality of insulating base material layers are laminated in the 1 st direction), it is difficult to stabilize the thickness (thickness dimension) in the 1 st direction. For example, when a laminate is formed by heating and pressing a plurality of laminated insulating base material layers, the amount of sinking of the electrode into the laminate varies, and the thickness of the interposer in the 1 st direction may vary. In addition, there is a case where unevenness is generated on a main surface (electrode formation surface) of the laminate due to the conductor pattern formed on the laminate. Further, when a protective film such as a solder resist is formed on the main surface of the laminate after the heating and pressing, variations in thickness may occur depending on the degree of wetting and viscosity of the protective film. On the other hand, in the electronic device 401 according to the present embodiment, since the interposer 301 is connected to the 1 st member and the 2 nd member in the standing state (the state where the end surface SS1 of the stacked body 10 faces the 1 st member and the end surface SS2 faces the 2 nd member), the thickness dimension in the 1 st direction is easily stabilized. This is because the interposer 301 is formed by cutting individual pieces from the collective substrate, as will be described later in detail. That is, the thickness (thickness dimension in the 1 st direction) of the interposer 301 is determined by the precision of dicing, and is not affected by variations in thickness dimension due to irregularities formed on the main surface of the laminate, the degree of wetting of the protective film, and the like.
The interposer 301 according to the present embodiment is manufactured, for example, by the following steps. Fig. 3 is a sectional view sequentially showing the manufacturing process of the interposer 301. In fig. 3, for convenience of explanation, a single chip (One chip) manufacturing process is described, but an actual interposer manufacturing process is performed in a collective substrate state.
First, as shown in fig. 3 (1), an insulating base layer 12 having conductor patterns 21 and 22 formed on both surfaces thereof is prepared. Specifically, a metal foil (for example, Cu foil) is laminated on both sides of the insulating base material layer 12 in a collective substrate state, and then the metal foil is patterned by photolithography. The insulating base layer 12 is a sheet made of, for example, a thermoplastic resin such as Liquid Crystal Polymer (LCP) or polyether ether ketone (PEEK).
Next, as shown in fig. 3 (2), an opening H1 is formed in the insulating base material layer 12. The opening H1 is a through hole extending from the front surface to the back surface of the insulating base layer 12. The opening H1 is formed by, for example, demolding by blanking or the like.
Then, as shown in (3) of fig. 3, the interlayer connection conductor V1 is formed on the insulating base material layer 12, and the insulating base material layers 11 and 13 are prepared. The interlayer connection conductor V1 is a metal formed by electroless plating or the like (through hole plating of Cu or the like), for example. The planar shape of the insulating substrate layers 11 and 13 is substantially the same as the planar shape of the insulating substrate layer 12. The insulating base layers 11 and 13 are sheets made of, for example, a Liquid Crystal Polymer (LCP) or a thermoplastic resin such as polyether ether ketone (PEEK).
Next, as shown in fig. 3 (4), the insulating base material layers 13, 12, and 11 are laminated in this order. Then, the laminated insulating base material layers 11, 12, and 13 are heated and pressed to form a laminated body 10 in a collective substrate state as shown in (5) in fig. 3, and then separated from the collective substrate into individual pieces.
Finally, the 1 st electrode P1 and the 2 nd electrode P2 were formed on the end surfaces SS1 and SS2 of the laminate 10, respectively, to obtain the interposer 301 shown in (6) in fig. 3. The 1 st electrode P1 and the 2 nd electrode P2 are plating films of Cu or the like formed by electroless plating (or electroplating), for example.
EXAMPLE 2 EXAMPLE
In embodiment 2, an example of an interposer having a different structure of interlayer connection conductors is shown.
Fig. 4 is a sectional view of the interposer 302 according to embodiment 2.
The interposer 302 is different from the interposer 301 according to embodiment 1 in that it includes an interlayer connection conductor V2. The other structure of the interposer 302 is the same as that of the interposer 301.
Hereinafter, a description will be given of a portion different from the interpolator 301 according to embodiment 1.
The interlayer connection conductor V2 is a conductor formed in the laminate 10 and extending in the 2 nd direction (the Z-axis direction shown in fig. 4) parallel to the end surface SS1 (the 1 st mounting surface) and the end surface SS2 (the 2 nd mounting surface), and the interlayer connection conductor V2 connects the plurality of conductor patterns 21 and 22 to each other. The interlayer connection conductor V2 is, for example, a via conductor provided by disposing a conductive paste containing one or more of Cu and Sn or an alloy thereof in an opening provided in the insulating base material layer 12, and then curing the conductive paste by a heat pressing treatment in a lamination process.
As shown in fig. 4, a length La2 in the X axis direction (1 st direction) between the end surface SS1 (1 st mounting surface) and the end surface SS2 (2 nd mounting surface) is longer than a total length Lb2 in the Z axis direction (2 nd direction) of the interlayer connection conductor V2 (La2 > Lb 2).
The interpolator 302 according to the present embodiment achieves the following effects in addition to the effects described in embodiment 1.
(g) In the present embodiment, the plurality of conductor patterns 21 and 22 and the interlayer connection conductor V2 are connected by solid-phase diffusion bonding. With this configuration, the bonding strength between the conductor pattern and the interlayer connection conductor can be improved by an easy manufacturing method, compared to a case where the interlayer connection conductor connected to the plurality of conductor patterns 21 and 22 is formed by plating or the like.
(h) In the present embodiment, the interlayer connection conductor V2 includes a resin material. Since the via conductor (interlayer connection conductor V2) obtained by curing the conductive paste contains a resin component, the bonding strength with the insulating base material layer mainly composed of a resin is higher than that of via hole plating or the like which is a simple metal. Therefore, the bonding strength between the interlayer connection conductor V2 and the insulating base layer 12 is improved as compared with the case where the interlayer connection conductor is formed by plating. Therefore, with this structure, an interposer with high mechanical strength and high electrical connection reliability can be realized.
(i) In the present embodiment, the plurality of insulating base material layers 11, 12, and 13 forming the laminate 10 are made of thermoplastic resin, and the interlayer connection conductor V2 is a via conductor formed by curing conductive paste. According to this configuration, as will be described in detail later, the laminated body 10 can be easily formed by collectively pressing the plurality of insulating base material layers 11, 12, and 13 that are laminated, so that the number of steps in the manufacturing process of the laminated body 10 can be reduced, and the cost can be reduced.
The interposer 302 according to the present embodiment is manufactured, for example, by the following steps. Fig. 5 is a sectional view showing the manufacturing process of the interposer 302 in order.
First, as shown in fig. 5 (1), insulating base material layers 11, 12, and 13 are prepared. Further, a conductor pattern 21 is formed on the insulating base layer 12, and a conductor pattern 22 is formed on the insulating base layer 13. Specifically, a metal foil (for example, Cu foil) is laminated on one surface of the insulating base material layers 12 and 13 in a collective substrate state, and then the metal foil is patterned by photolithography.
Further, an interlayer connection conductor V2 is formed on the insulating base material layer 12. The interlayer connection conductor V2 is formed by providing an opening in the insulating base layer 12 with a laser beam or the like, disposing (filling) a conductive paste containing one or more of Cu, Sn, and the like, or an alloy thereof, and then curing the conductive paste by a heat pressing treatment in a lamination process. Therefore, the interlayer connection conductor V2 is made of a material having a lower melting point (melting temperature) than the temperature at the time of heating and pressing later.
Next, as shown in fig. 5 (2), the insulating base material layers 13, 12, and 11 are laminated in this order. Then, the laminated insulating base material layers 11, 12, and 13 are heated and pressed to form a laminated body 10 in a collective substrate state as shown in (3) in fig. 5, and then separated from the collective substrate into individual pieces.
Finally, the 1 st electrode P1 and the 2 nd electrode P2 were formed on the end surfaces SS1 and SS2 of the laminate 10, respectively, to obtain the interposer 302 shown in (6) in fig. 5.
According to the above-described manufacturing method, the interposer 302 (the laminate 10) can be easily formed by collectively pressing the plurality of laminated insulating base material layers 11, 12, and 13, and therefore, the number of steps in the manufacturing process can be reduced, and the cost can be reduced.
EXAMPLE 3
In embodiment 3, an example of an interposer including a plurality of interlayer connection conductors and planar conductors is shown.
Fig. 6 is a sectional view of the interposer 303 according to embodiment 3. Fig. 7 is an exploded top view of interposer 303.
The interposer 303 includes a laminate 10A, a plurality of conductor patterns 21, 22, 23, planar conductors 31, 32, interlayer connection conductors V21, V22, a1 st electrode P1, a2 nd electrode P2, and ground electrodes GP11, GP12, GP21, GP 22.
The interposer 303 is different from the interposer 302 according to embodiment 2 in that it includes a laminate 10A, planar conductors 31 and 32, and ground electrodes GP11, GP12, GP21, and GP 22. In addition, the number of conductor patterns of the interposer 303 and the number of interlayer connection conductors are different from those of the interposer 302. The other structure of the interposer 303 is substantially the same as that of the interposer 302.
Hereinafter, a description will be given of a portion different from the interpolator 302 according to embodiment 2.
The laminate 10A is a rectangular parallelepiped insulator in which a plurality of flexible insulating base material layers 11a, 12a, 13a, 14a, 15a, 16a, and 17a are laminated. The laminate 10A has an end surface SS1 (1 st mounting surface) and an end surface SS2 (2 nd mounting surface) that face each other. The end surface SS1 is a surface (end surface of the laminate 10A) parallel to the lamination direction (Z-axis direction) of the plurality of insulating base material layers 11a to 17 a. The insulating substrate layers 11a to 17a are substantially the same as the insulating substrate layers 11, 12, and 13 described in embodiment 1.
The plurality of conductor patterns 21, 22, and 23 are formed in the laminate 10A and extend in the 1 st direction (for example, the X-axis direction shown in fig. 6) perpendicular to the end surface SS1 (1 st mounting surface) and the end surface SS2 (2 nd mounting surface). The planar conductors 31 and 32 are conductor patterns formed in the laminate 10A and extending in the 1 st direction. The conductor patterns 21, 22, and 23 and the planar conductors 31 and 32 are conductor patterns such as Cu foil, for example.
The interlayer connection conductors V21, V22 are conductors formed in the laminate 10A and extending in the 2 nd direction (the Z-axis direction shown in fig. 6) parallel to the end surface SS1 (the 1 st mounting surface) and the end surface SS2 (the 2 nd mounting surface), and the interlayer connection conductors V21, V22 connect the plurality of conductor patterns 21, 22, 23 to each other. The interlayer connection conductors V21 and V22 are via conductors provided by providing openings in an insulating base material layer with a laser or the like, then providing (filling) a conductive paste containing one or more of Cu, Sn, and the like, or an alloy thereof, and then curing the paste by a heat pressing treatment in a lamination process.
As shown in fig. 6 and 7, the interlayer connection conductors V21 and V22 are formed on different insulating base material layers. Specifically, the interlayer connection conductor V21 is formed on the insulating base material layer 14a, and the interlayer connection conductor V22 is formed on the insulating base material layer 15 a. The interlayer connection conductors V21, V22 are arranged at positions not overlapping each other when viewed from the 2 nd direction (Z-axis direction).
The 1 st electrode P1 and the ground electrodes GP11 and GP12 are conductors formed on the end surface SS1 (the 1 st mounting surface), and the 2 nd electrode P2 and the ground electrodes GP21 and GP22 are conductors formed on the end surface SS2 (the 2 nd mounting surface). The ground electrodes GP11, GP12, GP21, GP22 are plating films of Cu or the like formed by electroless plating (or electroplating), for example.
The 1 st electrode P1 and the 2 nd electrode P2 are electrically connected via the plurality of conductor patterns 21, 22, 23 and the interlayer connection conductors V21, V22. Specifically, as shown in fig. 6 and 7, the 1 st electrode P1 is connected to one end of the conductor pattern 21, and the other end of the conductor pattern 21 is connected to one end of the conductor pattern 22 via the interlayer connection conductor V21. The other end of the conductor pattern 22 is connected to one end of the conductor pattern 23 via the interlayer connection conductor V22, and the other end of the conductor pattern 23 is connected to the 2 nd electrode P2. The ground electrode GP11 and the ground electrode GP21 are electrically connected to each other via the planar conductor 31. The ground electrode GP12 and the ground electrode GP22 are electrically connected to each other via the planar conductor 32.
In this manner, in the present embodiment, the wiring (signal line) for connecting the 1 st electrode P1 and the 2 nd electrode P2 is formed by the plurality of electrically connected conductor patterns 21, 22, and 23 and the interlayer connection conductors V21 and V22.
In the present embodiment, the transmission line having a strip line structure is configured by the conductor pattern 21, the planar conductors 31 and 32, the insulating base material layers 12a and 13a sandwiched between the conductor pattern 21 and the planar conductor 31, and the insulating base material layers 14a, 15a, and 16a sandwiched between the conductor pattern 21 and the planar conductor 32. The conductor pattern 23, the planar conductors 31 and 32, the insulating base material layers 12a, 13a, 14a and 15a sandwiched between the conductor pattern 23 and the planar conductor 31, and the insulating base material layer 16a sandwiched between the conductor pattern 23 and the planar conductor 32 constitute a transmission line having a stripline structure.
As shown in fig. 6, a length La3 in the X axis direction (1 st direction) between the end surface SS1 (1 st mounting surface) and the end surface SS2 (2 nd mounting surface) is longer than a total length Lb3 in the Z axis direction (2 nd direction) of the interlayer connection conductors V21, V22 (La3 > Lb 3).
When viewed from the 2 nd direction (Z-axis direction), the entire plurality of conductor patterns 21, 22, and 23 overlap the planar conductors 31 and 32. The planar conductors 31 and 32 are disposed at positions sandwiching the plurality of conductor patterns 21, 22, and 23 or the interlayer connection conductors V21 and V22 in the 2 nd direction (Z-axis direction).
Next, an electronic device including the interposer 303 according to the present invention will be described with reference to the drawings. Fig. 8 is a sectional view showing a main part of an electronic apparatus 403 according to embodiment 3.
The electronic device 403 includes the 1 st circuit board 102 (1 st member), the 2 nd circuit board 202 (2 nd member), the interposer 303, the component 82, and the like. Although many components other than the component 82 are disposed on the 1 st circuit board 102 and the 2 nd circuit board 202, illustration thereof is omitted. The 1 st circuit board 102 and the 2 nd circuit board 202 are disposed apart in the 1 st direction (X-axis direction), and the interposer 303 and the component 82 are disposed between the 1 st circuit board 102 and the 2 nd circuit board 202. The structure of the 1 st circuit board 102 is substantially the same as the 1 st circuit board 101 described in embodiment 1. The structure of the 2 nd circuit board 202 is substantially the same as that of the 2 nd circuit board 201 described in embodiment 1. The component 82 is, for example, a chip capacitor or the like constituting an impedance matching circuit. Further, another member may be disposed close to the opposite side to the member 82 (the + Z direction side of the interposer 303) with the interposer 303 interposed therebetween.
As shown in fig. 8, the interposer 303 and the component 82 are mounted on the upper surface S1 of the 1 st circuit board 102. The end surface SS1 (1 st mounting surface) of the laminate 10A faces the 1 st circuit board 102, and the end surface SS2 (2 nd mounting surface) of the laminate 10A faces the lower surface S2 of the 2 nd circuit board 202.
A plurality of lands 61, 62, 63, 64, 65 are formed on the upper surface S1 of the 1 st circuit board 102. The 1 st electrode P1 of the interposer 303 is directly soldered to the land 61. Thereby, the 1 st electrode P1 of the interposer 303 is electrically connected to the 1 st circuit substrate 102 (the 1 st member). The ground electrodes GP11 and GP12 of the interposer 303 are directly soldered to the lands 62 and 63, respectively. Thereby, the ground electrodes GP11, GP12 of the interposer 303 are electrically connected to the ground of the 1 st circuit substrate 102. The terminals of the member 82 are directly soldered to the lands 64 and 65, respectively.
A plurality of lands 71, 72, 73 are formed on the lower surface S2 of the 2 nd circuit board 202. The 2 nd electrode P2 of the interposer 303 is directly soldered to the land 71. Thereby, the 2 nd electrode P2 of the interposer 303 is electrically connected to the 2 nd circuit substrate 202 (the 2 nd member). The ground electrodes GP21 and GP22 of the interposer 303 are directly soldered to the lands 72 and 73, respectively. Thereby, the ground electrodes GP21, GP22 of the interposer 303 are electrically connected to the ground of the 2 nd circuit substrate 202.
As shown in fig. 8, at least a part of the planar conductor 32 is positioned between the plurality of conductor patterns 21, 22, 23 and the member 82.
In this embodiment, the 1 st circuit board 102 and the 2 nd circuit board 202 are glass/epoxy substrates, and have an effective relative permittivity of about 4. On the other hand, the laminated body 10A of the interposer 303 is a Liquid Crystal Polymer (LCP), and the effective relative dielectric constant is about 3. That is, in the present embodiment, the effective relative permittivity of the laminated body 10A of the interposer 303 is smaller than the effective relative permittivities of the 1 st circuit substrate 102 and the 2 nd circuit substrate 202.
The "effective relative permittivity" in the present specification is not limited to the "relative permittivity" of a single material, and refers to the "relative permittivity" of the entire composite material (composite material made of resin, conductor pattern, interlayer connection conductor, adhesive, and the like).
According to the interposer 303 and the electronic device 403 according to the present embodiment, the following effects are obtained in addition to the effects described in embodiment 2.
(j) Generally, a laminate formed by laminating a plurality of insulating base material layers mainly made of resin is easily deformed by external force, impact, or the like. In addition, when a plurality of interlayer connection conductors are continuously arranged in the laminate, if the laminate is deformed, stress concentrates on the interlayer connection conductors, and the interlayer connection conductors are easily broken. On the other hand, in the present embodiment, the plurality of interlayer connection conductors V21, V22 are arranged at positions not overlapping each other when viewed from the 2 nd direction (Z-axis direction). According to this structure, since the plurality of interlayer connection conductors V21, V22 are not continuously arranged in the 2 nd direction, when an external force, an impact, or the like is applied to the multilayer body 10A (particularly, an external force in the Z-axis direction), the stress applied to the interlayer connection conductors V21, V22 is dispersed. Therefore, even when an external force or the like is applied to the multilayer body 10A, damage or the like of the interlayer connection conductors V21 and V22 can be suppressed, and the connection reliability of the interlayer connection conductors V21 and V22 with respect to the external force can be improved. Therefore, an interposer with high mechanical strength can be realized.
(k) The interposer 303 according to the present embodiment has a smaller effective relative permittivity than the 1 st circuit board 102 (1 st member) and the 2 nd circuit board 202 (2 nd member). Therefore, a capacitance component generated between the conductor patterns of the interposer 303 (for example, between the conductor pattern 21 and the planar conductor 32, or between the conductor pattern 23 and the planar conductor 31) can be reduced. Generally, the linear expansion coefficient of a circuit board on which a component is mounted needs to be matched with the linear expansion coefficient of the component to be mounted, and a glass/epoxy board containing a filler such as glass fiber has been used for the circuit board. In contrast, the interposer of the present invention is not equipped with many components as in the 1 st circuit board 102 and the 2 nd circuit board 202, and therefore, a material having a lower effective relative permittivity than the 1 st circuit board 102 and the 2 nd circuit board 202 can be used without such a limitation.
(1) In the present embodiment, the plurality of conductor patterns 21, 22, and 23 overlap the planar conductors 31 and 32 when viewed from the 2 nd direction (Z-axis direction). According to this configuration, by the shielding effect of the planar conductors 31 and 32, unnecessary radiation from the signal lines (the electrically connected conductor patterns 21, 22, and 23 and the interlayer connection conductors V21 and V22) can be suppressed, or the influence of noise from the outside (for example, the component 82) on the signal lines can be suppressed, for example, with respect to an article (for example, the component 82) or the like located in at least one direction in the 2 nd direction as viewed from the interposer 303. Further, according to this configuration, when the stacking direction of the plurality of insulating base material layers forming the stacked body is parallel to the 1 st direction (the direction in which the 1 st member and the 2 nd member are separated), the shielding property against the signal line is improved as compared with a configuration in which a plurality of interlayer connection conductors extending in the 1 st direction are arranged around the signal line (on the 2 nd direction side with respect to the signal line). Therefore, the isolation between the signal line and the outside can be improved.
In the present embodiment, although the configuration is shown in which the entire plurality of conductor patterns 21, 22, and 23 overlap the planar conductors 31 and 32 when viewed from the 2 nd direction (Z-axis direction), the configuration is not limited to this. The above-described effects can be achieved if at least a part of the plurality of conductor patterns overlaps the planar conductor when viewed from the 2 nd direction. However, in view of the above-described operation and effect, it is preferable that the entire plurality of conductor patterns overlap the planar conductor when viewed from the 2 nd direction.
(m) in the present embodiment, the plurality of planar conductors 31 and 32 are disposed at positions sandwiching the signal line in the 2 nd direction (Z-axis direction). According to this configuration, the shielding effect by the planar conductor is further improved for both sides of the signal line in the 2 nd direction. Therefore, with respect to the articles (for example, the components 82) and the like located on both sides in the 2 nd direction as viewed from the interposer 303, unnecessary radiation from the signal line can be further suppressed, or the influence of noise from the outside (for example, the components 82) on the signal line can be further suppressed.
In addition, (n) in the electronic apparatus 403 according to the present embodiment, at least a part of the planar conductor 32 is positioned between the plurality of conductor patterns 21, 22, and 23 and the member 82. According to this configuration, by the shielding effect by the planar conductor, unnecessary radiation from the signal line to the member 82 can be suppressed, or the influence of noise from the member 82 on the signal line can be suppressed.
In addition, although the signal line connecting the 1 st electrode P1 and the 2 nd electrode P2 is formed by the three conductor patterns 21, 22, and 23 and the two interlayer connection conductors V21 and V22 in this embodiment, the configuration of the signal line is not limited thereto. The number of conductor patterns and the number of interlayer connection conductors may be changed as appropriate within the range of achieving the operational effect of the present invention, and for example, signal lines may be formed by four or more conductor patterns and three or more interlayer connection conductors.
EXAMPLE 4 embodiment
In embodiment 4, an example is shown in which a planar conductor is formed on the surface of a laminate.
Fig. 9 is a sectional view of the interposer 304 according to embodiment 4.
The interposer 304 includes a laminate 10B, a plurality of conductor patterns 21 and 22, planar conductors 31A and 32A, interlayer connection conductors V21 and V22, a1 st electrode P1, and a2 nd electrode P2.
The interposer 304 is different from the interposer 302 according to embodiment 2 in that it includes the laminate 10B and the planar conductors 31A and 32A. Further, the interposer 304 differs in the number of interlayer connection conductors from the interposer 302. The other structure of the interposer 304 is substantially the same as that of the interposer 302.
Hereinafter, a description will be given of a portion different from the interpolator 302 according to embodiment 2.
The laminate 10B is a rectangular parallelepiped insulator in which a plurality of flexible insulating base material layers 11B, 12B, 13B, and 14B are laminated. The laminate 10B has a1 st main surface MS1 and a2 nd main surface MS2 that face each other. The 1 st main surface MS1 and the 2 nd main surface MS2 are surfaces perpendicular to the lamination direction (Z-axis direction) of the plurality of insulating base material layers 11b to 14 b. The insulating substrate layers 11b to 14b are substantially the same as the insulating substrate layers 11, 12, and 13 described in embodiment 1.
The plurality of conductor patterns 21 and 22 are formed in the laminate 10B and extend in the 1 st direction (for example, the X-axis direction shown in fig. 9) perpendicular to the end surface SS1 (1 st mounting surface) and the end surface SS2 (2 nd mounting surface). The planar conductor 31A is a conductor formed on the entire 1 st main surface MS1, and the planar conductor 32A is a conductor formed on the entire 2 nd main surface MS 2. The planar conductors 31A and 32A are plating films of Cu or the like formed by electroless plating (or electroplating), for example.
The entirety of the plurality of conductor patterns 21 and 22 overlaps the planar conductors 31A and 32A when viewed from the 2 nd direction (Z-axis direction) (not shown). The planar conductors 31A and 32A are disposed at positions sandwiching the plurality of conductor patterns 21 and 22 or the interlayer connection conductors V21 and V22 in the 2 nd direction (Z-axis direction).
The interlayer connection conductors V21, V22 are conductors formed in the laminate 10B and extending in the 2 nd direction (the Z-axis direction shown in fig. 9) parallel to the end surface SS1 (the 1 st mounting surface) and the end surface SS2 (the 2 nd mounting surface), and the interlayer connection conductors V21, V22 connect the plurality of conductor patterns 21, 22 to each other. The interlayer connection conductors V21 and V22 are via conductors provided by providing openings in an insulating base material layer with a laser or the like, then providing (filling) a conductive paste containing one or more of Cu, Sn, and the like, or an alloy thereof, and then curing the paste by a heat pressing treatment in a lamination process.
As shown in fig. 9, the interlayer connection conductors V21 and V22 are formed on different insulating base material layers. In the present embodiment, the interlayer connection conductors V21 and V22 are arranged at positions overlapping each other when viewed from the 2 nd direction (Z-axis direction).
The 1 st electrode P1 and the 2 nd electrode P2 are electrically connected via the plurality of conductor patterns 21, 22 and the interlayer connection conductors V21, V22. Specifically, as shown in fig. 9, the 1 st electrode P1 is connected to one end of the conductor pattern 21. The other end of the conductor pattern 21 is connected to one end of the conductor pattern 22 via interlayer connection conductors V21 and V22, and the other end of the conductor pattern 22 is connected to the 2 nd electrode P2.
In this manner, in the present embodiment, the wiring (signal line) for connecting the 1 st electrode P1 and the 2 nd electrode P2 is formed by the plurality of electrically connected conductor patterns 21 and 22 and the interlayer connection conductors V21 and V22.
In the present embodiment, the transmission line having a strip line structure is configured by the conductor pattern 21, the planar conductors 31A, 32A, the insulating base layer 11b sandwiched between the conductor pattern 21 and the planar conductor 31A, and the insulating base layers 12b, 13b, 14b sandwiched between the conductor pattern 21 and the planar conductor 32A. The transmission line having a strip line structure is constituted by the conductor pattern 22, the planar conductors 31A and 32A, the insulating base material layers 11b, 12b and 13b sandwiched between the conductor pattern 22 and the planar conductor 31A, and the insulating base material layer 14b sandwiched between the conductor pattern 22 and the planar conductor 32A.
Even with such a configuration, the same operational advantages as those of the interposer 303 according to embodiment 3 are achieved.
EXAMPLE 5 EXAMPLE
In embodiment 5, an example of an interposer including a laminate body having a portion bent is shown.
Fig. 10 is a sectional view of interposer 305 according to embodiment 5. Fig. 11 is a sectional view showing a state before bending of interposer 305.
The interposer 305 is different from the interposer 302 according to embodiment 2 in that it includes a laminate 10C, a1 st electrode P1A, and a plurality of interlayer connection conductors V21 and V22. The other structure of interposer 305 is substantially the same as that of interposer 302.
Hereinafter, a description will be given of a portion different from the interpolator 302 according to embodiment 2.
The laminate 10C is an L-shaped insulator in which a plurality of flexible insulating base material layers 11C, 12C, and 13C are laminated and a part of the insulating base material layers is bent. The laminate 10C has the 2 nd main surface MS2A and the end surface SS2 parallel to each other. In the present embodiment, a part of the 2 nd main surface MS2A and a part of the end surface SS2 face each other. The end surface SS2 is a surface (end surface of the laminate 10C) parallel to the lamination direction (Z-axis direction) of the plurality of insulating base material layers 11C, 12C, 13C.
In the present embodiment, the 2 nd main surface MS2A of the laminate 10C corresponds to the "1 st attachment surface" in the present invention, and the end surface SS2 corresponds to the "2 nd attachment surface" in the present invention.
The partially bent laminate 10C is obtained, for example, by folding a rectangular parallelepiped laminate 10C (a rectangular flat plate having a longitudinal direction aligned with the X-axis direction) shown in fig. 11 into an L shape along a folding line CL (a one-dot chain line in fig. 11) while heating and pressing the laminate. This makes it possible to obtain a laminate that maintains (retains) the bent shape. A part of the 2 nd main surface MS2 of the laminate 10C shown in fig. 11 is bent to become the 2 nd mounting surface (the 2 nd main surface MS2A) of the laminate 10C shown in fig. 10.
The partially curved laminate 10C has a standing portion SP. The standing portion SP is a portion in which the stacking direction of the plurality of insulating base material layers 11c, 12c, and 13c is parallel to the 1 st mounting surface (the 2 nd main surface MS2A) and the 2 nd mounting surface (the end surface SS 2).
The plurality of conductor patterns 21 and 22 are conductor patterns formed in the laminate 10C. In the rising portion SP, the plurality of conductor patterns 21 and 22 extend in the 1 st direction (for example, the X-axis direction shown in fig. 10) perpendicular to the 2 nd main surface MS2A (1 st mounting surface) and the end surface SS2 (2 nd mounting surface).
The interlayer connection conductors V21 and V22 are conductors formed in the multilayer body 10C. In the rising portion SP, the interlayer connection conductor V21 extends in the 2 nd direction (the Z-axis direction shown in fig. 10) parallel to the 2 nd main surface MS2A (the 1 st mounting surface) and the end surface SS2 (the 2 nd mounting surface), and connects the plurality of conductor patterns 21 and 22 to each other. The interlayer connection conductor V22 extends in the 1 st direction (X-axis direction) perpendicular to the 2 nd main surface MS2A (1 st mounting surface) and the end surface SS2 (2 nd mounting surface). The interlayer connection conductors V21 and V22 are via conductors provided by providing openings in an insulating base material layer with a laser or the like, then providing (filling) a conductive paste containing one or more of Cu, Sn, and the like, or an alloy thereof, and then curing the paste by a heat pressing treatment in a lamination process.
The interlayer connection conductors V21 and V22 are formed on different insulating base material layers. Specifically, the interlayer connection conductor V21 is formed on the insulating base material layer 12c, and the interlayer connection conductor V22 is formed on the insulating base material layer 13 c.
The 1 st electrode P1A is a conductor pattern formed on the 2 nd main surface MS2A (1 st mounting surface), and the 2 nd electrode P2 is a conductor formed on the end surface SS2 (2 nd mounting surface). The 1 st electrode P1A is, for example, a conductor pattern of Cu or the like, and the 2 nd electrode P2 is, for example, a plating film of Cu or the like formed by electroless plating (or electroplating).
The 1 st electrode P1A and the 2 nd electrode P2 are electrically connected via the plurality of conductor patterns 21, 22 and the interlayer connection conductors V21, V22. Specifically, as shown in fig. 10, the 1 st electrode P1A is connected to one end of the conductor pattern 22 via an interlayer connection conductor V22. The other end of the conductor pattern 22 is connected to one end of the conductor pattern 21 via the interlayer connection conductor V21. The other end of the conductor pattern 21 is connected to the 2 nd electrode P2.
In this manner, in the present embodiment, the wiring (signal line) for connecting the 1 st electrode P1A and the 2 nd electrode P2 is formed by the plurality of electrically connected conductor patterns 21 and 22 and the interlayer connection conductors V21 and V22.
Further, as shown in fig. 10, in the rising portion SP, the length La5 in the 1 st direction (X-axis direction) is longer than the total length Lb5 in the 2 nd direction (Z-axis direction) of the interlayer connection conductor V21 (La5 > Lb 5). In other words, among the wirings connecting the 1 st electrode P1A and the 2 nd electrode P2, the length of the wiring (the plurality of conductor patterns 21 and 22) extending in the 1 st direction (X-axis direction) in the rising portion SP is longer than the length of the wiring (the interlayer connection conductor V21) extending in the 2 nd direction (Z-axis direction) in the rising portion SP.
Even in the case of the laminate body partially bent in this manner, the same operational effects as those of the interposer 302 according to embodiment 2 can be achieved by satisfying the above-described configuration in the standing portion. In addition to the effects described in embodiment 2, the interposer 305 according to the present embodiment achieves the following effects.
In the present embodiment, the 1 st electrode P1A is a conductor pattern formed on a part of the main surface (the surface perpendicular to the lamination direction of the laminate) of the laminate 10C, and the 2 nd main surface MS2 of the laminate 10C shown in fig. 11. According to this structure, it is easier to increase the area of the 1 st electrode as compared with the case where the 1 st electrode is formed on the end face of the laminate. Therefore, by increasing the area of the 1 st electrode, the mountability of the interposer to the 1 st member is improved, and the bonding strength between the interposer and the 1 st member (the bonding strength between the 1 st electrode P1A and the land of the 1 st member) can be improved. In addition, when the 2 nd electrode is a conductor pattern formed on a part of the principal surface of the laminate, the 2 nd electrode can be easily increased in area, and the mountability of the interposer to the 1 st member can be improved.
(p) the interposer 305 according to the present embodiment is configured by bending a part of the flexible laminate 10C. With this structure, the interposer (laminate) can be easily deformed by the flexibility and the bent portion of the laminate 10C itself. Therefore, even when the distance between the 1 st member and the 2 nd member (the distance in the 1 st direction) varies slightly for each electronic device, the length of the interposer in the 1 st direction is changed (fine-tuned), whereby the interposer can be easily disposed between the 1 st member and the 2 nd member. Further, according to this structure, since the interposer is connected to the 1 st member and the 2 nd member by the flexible and bent portions of the laminate 10C itself, stress or the like applied to the 1 st member and the 2 nd member is not easily transmitted to the bonding portions (the bonding portion of the 1 st electrode P1A and the land of the 1 st member, and the bonding portion of the 2 nd electrode P2 and the land of the 2 nd member). Therefore, damage and the like of the joint portion due to stress and the like applied to the 1 st member and the 2 nd member can be suppressed, and the connection reliability between the 1 st member (or the 2 nd member) and the interposer can be improved.
In the present embodiment, an example is shown in which a part of the 1 st mounting surface (the 2 nd main surface MS2A) and a part of the 2 nd mounting surface (the end surface SS2) face each other, but the present invention is not limited to this configuration. The 1 st mounting surface and the 2 nd mounting surface do not necessarily have to face each other, and may be parallel to each other. Further, in the present embodiment, an example is shown in which the "1 st mounting surface" is the 2 nd main surface MS2A of the laminate 10C and the "2 nd mounting surface" is the end surface SS2, but the present invention is not limited thereto. For example, the "1 st mounting surface" may be an end surface of the laminate, and the "2 nd mounting surface" may be either the 1 st main surface or the 2 nd main surface of the laminate.
In the present embodiment, the example of the laminate 10C bent in the L shape is shown, but the shape of the bent laminate is not limited to this. The shape of the curved laminate can be appropriately changed within the range of achieving the operational effect of the present invention. The portion, direction, and the like of bending the laminate are not limited to the configurations described in the present embodiment, and can be appropriately modified within the range of achieving the operational effects of the present invention.
Other embodiments
In the above-described embodiments, the interposer is entirely disposed (sandwiched) between the 1 st member (1 st circuit board) and the 2 nd member (2 nd circuit board), but the present invention is not limited to this configuration. The interposer may be partially disposed between the 1 st member and the 2 nd member.
In addition, although in each of the embodiments described above, an example is shown in which the interposer and the 1 st member (1 st circuit board) are directly connected via solder, the interposer and the 1 st member may be connected via a connector. For example, a configuration may be adopted in which a plug is attached to the 1 st mounting surface of the interposer, a socket is attached to the 1 st member, and electrical and mechanical connection is performed by fitting the plug and the socket. Further, the interposer and the 2 nd member may also be connected via a connector. However, from the viewpoint of the above-described operation and effect (see (e) above), it is preferable that the interposer and the 1 st member are directly connected via solder, and the interposer and the 2 nd member are directly connected via solder.
In the above-described embodiments, the shape of the stacked body is a rectangular parallelepiped, but the present invention is not limited to this configuration. The shape of the laminate can be appropriately changed within the range of achieving the operational effect of the present invention, and the planar shape may be, for example, a polygon, a circle, an ellipse, an L-shape, a T-shape, a Y-shape, a crank shape, or the like.
In the above-described embodiments, examples of the laminate in which three, four, or seven insulating base material layers are laminated are shown, but the present invention is not limited to this structure. The number of layers of the insulating base material layer forming the laminate may be changed as appropriate within the range in which the operational effect of the present invention is achieved, and may be, for example, two, five, six, or eight or more.
In the above-described embodiments, an example in which a plurality of insulating base material layers made of thermoplastic resin are laminated to form a laminate is shown, but the present invention is not limited to this structure. Each insulating base layer may be a protective layer such as a sheet made of a thermosetting resin such as an epoxy resin, a solder resist, or a cover film. The laminate may be a composite material of a plurality of resins, and may be formed by laminating a thermosetting resin such as glass and an epoxy plate and a thermoplastic resin, for example. The laminate is not limited to a laminate in which a plurality of stacked insulating base material layers are heated and pressed to be welded to each other on the surfaces, and may have a structure in which an adhesive material layer is provided between the insulating base material layers.
In the above-described embodiments, the interposer is shown as an example including only the electrodes (the 1 st electrode, the 2 nd electrode, and the ground electrode) for electrically connecting the 1 st member (the 1 st circuit board) and the 2 nd member (the 2 nd circuit board), but the present invention is not limited to this configuration. For example, the interposer may include an auxiliary electrode (electrode that does not electrically connect the 1 st member and the 2 nd member). By providing the auxiliary electrode, the interposer can be solder-mounted to the 1 st member or the 2 nd member in the same manner as other components even when the interposer is long.
In the above-described embodiments, the interposer in which the plurality of conductor patterns are formed in the laminate is exemplified, but the present invention is not limited to this configuration. A part of the plurality of conductor patterns may be formed on the surface of the laminate.
The circuit structure formed in the interposer (laminate) is not limited to the structure described in each embodiment. The circuit formed in the interposer can be appropriately modified within the range that achieves the operation and effect of the present invention.
In the interposer, for example, inductors, capacitors, and the like other than the signal lines may be formed by conductor patterns. Further, the interpolator may be provided with a frequency filter such as various filters (a low-pass filter, a high-pass filter, a band-pass filter, and a band-stop filter). Various transmission lines (for example, microstrip lines, coplanar lines, etc.) other than the stripline structure may be formed in the interposer.
Further, the interposer of the present invention may be configured to mount (or embed) various components such as chip components.
Finally, the above description of the embodiments is illustrative in all respects and not restrictive. It is obvious to those skilled in the art that the modifications and variations can be appropriately made. The scope of the present invention is shown not by the above-described embodiments but by the claims. Further, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the claims.
Description of the reference numerals
H1: an opening;
la1, La2, La3, La 4: a length in a1 st direction between the 1 st electrode and the 2 nd electrode;
la 5: length in the 1 st direction in the upright;
lb1, Lb2, Lb3, Lb 4: the total length of the interlayer connection conductors in the 2 nd direction;
lb 5: a total length of the interlayer connection conductors in the standing portion in the 2 nd direction;
MS 1: a1 st main surface of the laminate;
MS2, MS 2A: a2 nd main surface of the laminate;
p1, P1A: a1 st electrode;
p2: a2 nd electrode;
GP11, GP12, GP21, GP 22: a ground electrode;
s1: the upper surface of the 1 st circuit substrate;
s2: the lower surface of the 2 nd circuit substrate;
SS1, SS 2: an end face of the laminate;
SP: an upright portion of the laminate;
v1, V2, V21, V22: an interlayer connection conductor;
10. 10A, 10B, 10C: a laminate;
11. 11a, 11b, 11c, 12a, 12b, 12c, 13a, 13b, 13c, 14a, 14b, 15 a: an insulating substrate layer;
21. 22, 23: a conductor pattern;
31. 31A, 32A: a planar conductor;
61. 62, 63, 64, 65, 71, 72, 73: a connecting disc;
81. 82, 91: a component;
101. 102: a1 st circuit board (1 st member);
201. 202: a2 nd circuit board (2 nd member);
301. 302, 303, 304, 305: an interpolator;
401. 403: an electronic device.

Claims (21)

1. An interposer disposed between a1 st member and a2 nd member, for electrically connecting the 1 st member and the 2 nd member, comprising:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are opposed to each other;
a plurality of conductor patterns formed on the laminate and extending in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface;
an interlayer connection conductor formed in the laminate body and extending in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, the interlayer connection conductor connecting the plurality of conductor patterns to each other;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the 1 st mounting surface and the 2 nd mounting surface are surfaces parallel to a stacking direction of the plurality of insulating base material layers,
the length in the 1 st direction between the 1 st mounting surface and the 2 nd mounting surface is longer than the total length in the 2 nd direction of the interlayer connection conductor.
2. The interposer of claim 1,
the plurality of conductor patterns and the interlayer connection conductor are connected by solid-phase diffusion bonding.
3. The interposer of claim 1,
the interlayer connection conductor is a metal formed by plating.
4. The interposer of claim 1,
the insulating base material layers are made of resin as a main material,
the interlayer connection conductor includes a resin material.
5. The interposer of claim 1,
the insulating base material layers are made of resin as a main material,
the interlayer connection conductor is a plurality of interlayer connection conductors formed on different insulating base material layers,
the plurality of interlayer connection conductors are arranged at positions not overlapping each other when viewed from the 2 nd direction.
6. The interposer of claim 1,
the disclosed device is provided with: a planar conductor formed on the laminate,
at least a part of the plurality of conductor patterns overlaps the planar conductor when viewed from the 2 nd direction.
7. The interposer of claim 1,
the plurality of insulating base material layers are made of thermoplastic resin.
8. An interposer disposed between a1 st member and a2 nd member, for electrically connecting the 1 st member and the 2 nd member, comprising:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are parallel to each other;
a plurality of conductor patterns formed on the laminate;
an interlayer connection conductor formed on the laminate;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the laminate has a rising portion in which the direction of lamination of the plurality of insulating base material layers is parallel to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the plurality of conductor patterns extend in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the interlayer connection conductor extends in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, and connects the plurality of conductor patterns to each other,
in the standing portion, a length in the 1 st direction is longer than a total length in the 2 nd direction of the interlayer connection conductor.
9. The interposer of claim 8,
either one of the 1 st mounting surface and the 2 nd mounting surface is an end surface of the laminated body parallel to the laminating direction.
10. The interposer of claim 8,
the plurality of conductor patterns and the interlayer connection conductor are connected by solid-phase diffusion bonding.
11. The interposer of claim 8,
the interlayer connection conductor is a metal formed by plating.
12. The interposer of claim 8,
the insulating base material layers are made of resin as a main material,
the interlayer connection conductor includes a resin material.
13. The interposer of claim 8,
the insulating base material layers are made of resin as a main material,
the interlayer connection conductor is a plurality of interlayer connection conductors formed on different insulating base material layers,
the plurality of interlayer connection conductors are arranged at positions not overlapping each other when viewed from the 2 nd direction.
14. The interposer of claim 8,
the disclosed device is provided with: a planar conductor formed on the laminate,
at least a part of the plurality of conductor patterns overlaps the planar conductor when viewed from the 2 nd direction.
15. The interposer of claim 8,
the plurality of insulating base material layers are made of thermoplastic resin.
16. An electronic device is characterized by comprising:
a1 st member;
a2 nd member; and
an interposer disposed between the 1 st member and the 2 nd member, electrically connecting the 1 st member and the 2 nd member;
the interposer has:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are opposed to each other;
a plurality of conductor patterns formed on the laminate and extending in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface;
an interlayer connection conductor formed in the laminate body and extending in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, the interlayer connection conductor connecting the plurality of conductor patterns to each other;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the 1 st mounting surface and the 2 nd mounting surface are surfaces parallel to a stacking direction of the plurality of insulating base material layers,
a length in the 1 st direction between the 1 st mounting surface and the 2 nd mounting surface is longer than a total length in the 2 nd direction of the interlayer connection conductors,
the 1 st electrode is electrically connected to the 1 st member, and the 2 nd electrode is electrically connected to the 2 nd member.
17. The electronic device of claim 16,
the effective elastic modulus of the laminate is smaller than that of the 1 st member and that of the 2 nd member.
18. The electronic device of claim 16,
further provided with: and a component mounted on the 1 st member or the 2 nd member and disposed between the 1 st member and the 2 nd member.
19. An electronic device is characterized by comprising:
a1 st member;
a2 nd member; and
an interposer disposed between the 1 st member and the 2 nd member, electrically connecting the 1 st member and the 2 nd member;
the interposer has:
a laminate which is formed by laminating a plurality of insulating base material layers, is held in a state of being partially bent, and has a1 st mounting surface and a2 nd mounting surface which are parallel to each other;
a plurality of conductor patterns formed on the laminate;
an interlayer connection conductor formed on the laminate;
a1 st electrode formed on the 1 st mounting surface; and
a2 nd electrode formed on the 2 nd mounting surface and electrically connected to the 1 st electrode via the plurality of conductor patterns and the interlayer connection conductor,
the laminate has a rising portion in which the direction of lamination of the plurality of insulating base material layers is parallel to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the plurality of conductor patterns extend in a1 st direction perpendicular to the 1 st mounting surface and the 2 nd mounting surface,
in the standing portion, the interlayer connection conductor extends in a2 nd direction parallel to the 1 st mounting surface and the 2 nd mounting surface, and connects the plurality of conductor patterns to each other,
a length in the 1 st direction is longer than a total length in the 2 nd direction of the interlayer connection conductor in the standing portion,
the 1 st electrode is electrically connected to the 1 st member, and the 2 nd electrode is electrically connected to the 2 nd member.
20. The electronic device of claim 19,
the effective elastic modulus of the laminate is smaller than that of the 1 st member and that of the 2 nd member.
21. The electronic device of claim 19,
further provided with: and a component mounted on the 1 st member or the 2 nd member and disposed between the 1 st member and the 2 nd member.
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