CN211959652U

CN211959652U - PCB laminated structure and PCB

Info

Publication number: CN211959652U
Application number: CN201921133422.0U
Authority: CN
Inventors: 马龙; 崔蜀巍
Original assignee: Shenzhen Jove Enterprise Co ltd
Current assignee: Shenzhen Jove Enterprise Co ltd
Priority date: 2019-07-18
Filing date: 2019-07-18
Publication date: 2020-11-17
Anticipated expiration: 2029-07-18

Abstract

The utility model provides a PCB laminated structure and PCB board, wherein, the PCB board by PCB laminated structure pressfitting forms, PCB laminated structure includes laminated structure and second laminated structure for the first time, second laminated structure is including setting up in the center laminated structure for the first time, set up in the L1 layer and the interlaminar dielectric layer of laminated structure one side for the first time, and set up in the L6 layer and the interlaminar dielectric layer of laminated structure opposite side for the first time. The utility model discloses a design for twice laminated structure, can produce under the condition of guaranteeing degree of alignment and symmetrical structure pressfitting between the layer, can effectually avoid the PCB sheet layer to scrap by inclined to one side, the board sticks up, and then improves the production yield, reduces the processing procedure degree of difficulty, realizes the inclined to one side visual conventional control of layer, guarantees PCB's requirement for quality.

Description

PCB laminated structure and PCB

Technical Field

The utility model relates to a PCB lamination technical field especially relates to a PCB laminated structure and PCB board.

Background

In the prior art of PCB, a part of PCB circuit boards have inconsistent voltage resistance requirements on each layer, and the thickness difference of dielectric layers is large, so that the lamination structure is usually designed to be asymmetric in the industry. For an asymmetric laminated structure, the film pre-stretching coefficient of each core plate of the inner layer is required to be adjusted according to the post-etching expansion and contraction data of each batch of core plates of the inner layer, and the expansion and contraction coefficient proportion between the thick core plate and the thin core plate is confirmed by combining the pressing FA data. However, due to the difference of raw material batches and the influence of factors such as process control on the amount of expansion and shrinkage deformation, the interlayer alignment cannot be ensured during lamination, and the bad board has a serious risk of warpage. In conclusion, the method improves the alignment degree between the multilayer boards when the laminated structure of the PCB is asymmetric, reduces the risk of open circuit and short circuit of the product and the risk of warping of the board caused by the deformation problem of the asymmetric structure, and is a technical problem to be solved urgently in the technical field of the PCB at present.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention provides a PCB laminated structure and a PCB, which aims to improve the alignment between layers of a multi-layer board when the laminated structure of the PCB is asymmetric, and reduce the risk of opening a circuit and short circuit of a product and the risk of warping of the board caused by the deformation problem of the asymmetric structure.

A PCB laminated structure comprises a first laminated structure and a second laminated structure, wherein the second laminated structure comprises the first laminated structure arranged at the center, an L1 layer and an interlayer dielectric layer arranged at one side of the first laminated structure, and an L6 layer and an interlayer dielectric layer arranged at the other side of the first laminated structure.

Further, the number of dielectric layers between the L1 layer and the first secondary laminated structure is the same as the number of dielectric layers between the L6 layer and the first secondary laminated structure.

Further, the number of dielectric layers between the L1 layer and the first secondary laminated structure and between the L6 layer and the first secondary laminated structure is at least 1.

Further, the number of dielectric layers between the L1 layer and the first-time lamination structure and between the L6 layer and the first-time lamination structure is 2.

Further, the first-time laminating structure comprises an L2 layer, an L3 layer, an L4 layer, an L5 layer and an interlayer dielectric layer arranged between the two adjacent layers.

Further, the number of dielectric layers between the L2 layer and the L3 layer is the same as the number of dielectric layers between the L4 layer and the L5 layer.

Further, the number of dielectric layers between the L2 layer and the L3 layer and between the L4 layer and the L5 layer is 3.

The utility model also provides a PCB board, the PCB board is formed by foretell PCB laminated structure pressfitting.

The utility model discloses beneficial effect: the utility model discloses a design for twice laminated structure, can produce under the condition of guaranteeing degree of alignment and symmetrical structure pressfitting between the layer, can effectually avoid the PCB sheet layer to scrap by inclined to one side, the board sticks up, and then improves the production yield, reduces the processing procedure degree of difficulty, realizes the inclined to one side visual conventional control of layer, guarantees PCB's requirement for quality.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic view of a prior art laminate structure asymmetrical with respect to a copper thickness structure of a PCB core;

FIG. 2 is a schematic diagram of a prior art laminate structure asymmetrical with respect to a PCB board core copper thickness structure;

fig. 3 is a schematic diagram of a PCB laminated structure provided in embodiment 1 of the present invention;

fig. 4 is a schematic view of a first-time laminated structure of a PCB laminated structure provided in embodiment 1 of the present invention;

fig. 5 is a schematic diagram of a PCB laminated structure provided in embodiment 2 of the present invention;

fig. 6 is a schematic diagram of a first-time lamination structure of a PCB lamination structure provided in embodiment 2 of the present invention.

Description of the main elements

First time lamination 100

Second sub-laminate structure 200

First core plate 110

Second core board 120

Third core board 130

L1 layer 10

L2 layer 20

L3 layer 30

L4 layer 40

L5 layer 50

L6 layer 60

L1L2 interlayer dielectric layer 12

First L1L2 interlayer dielectric layer 121

Second L1L2 interlayer dielectric layer 122

L2L3 interlayer dielectric layer 23

First L2L3 interlayer dielectric layer 231

Second L2L3 interlayer dielectric layer 232

Third L2L3 interlayer dielectric layer 233

L3L4 interlayer dielectric layer 34

L4L5 interlayer dielectric layer 45

First L4L5 interlayer dielectric layer 451

Second L4L5 interlayer dielectric layer 452

Third L4L5 interlevel dielectric layer 453

L5L6 interlayer dielectric layer 56

First L5L6 interlayer dielectric layer 561

A second L5L6 interlayer dielectric layer 562.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.

The terms "first," "second," and "third," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. To the extent that the term "includes" and any variations thereof are used in either the detailed description or the claims, as well as the appended drawings, this is intended to cover non-exclusive inclusions.

Referring to fig. 1, in the current design of a multi-layer PCB laminated structure, the laminated structure is often designed to be an asymmetric structure, for example, if the thicknesses of the L1 layer 10 and the L2 layer 20 are designed to be different, for example, the thickness of the L1 layer 10 is designed to be Hoz, and the thickness of the L2 layer 20 is designed to be 1oz, the copper thickness structure of the first core 110 is often asymmetric in the first core 110, where the first core 110 is composed of the L1 layer 10, the L1L2 interlayer dielectric layer 12, and the L2 layer 20; for another example, if the thicknesses of the L5 layer 50 and the L6 layer 60 of the third core board 130 composed of the L5 layer 50, the L5L6 interlayer dielectric layer 56, and the L6 layer 60 are designed to be different, for example, the thickness of the L5 layer 50 is designed to be Hoz, and the thickness of the L6 layer 60 is designed to be 1oz, the copper thickness structure of the third core board 130 may be asymmetric. When the PCB composed of the first core board 110, the third core board 130 and the second core board 120 having asymmetric copper thickness structures is laminated, the problem of asymmetric copper thickness of the core board in the laminated structure may occur.

Referring to fig. 2, in the current multi-layer PCB board lamination structure design, the lamination structure is often designed to be an asymmetrical structure, for example, if the thicknesses of the L1L2 interlayer dielectric layer 12, the L3L4 interlayer dielectric layer 34, and the L5L6 interlayer dielectric layer 56 are designed to be different, in the first core board 110 composed of the L1 layer 10, the L1L2 interlayer dielectric layer 12, and the L2 layer 20, the second core board 120 composed of the L3 layer 30, the L3L4 interlayer dielectric layer 34, and the L4 layer 40, and the third core board 130 composed of the L5 layer 50, the L5L6 interlayer dielectric layer 56, and the L6 layer 60, for example, the thickness of the L1L2 interlayer dielectric layer 12 is designed to be 0.12mm, the thickness of the L3L4 interlayer dielectric layer 34 is designed to be 0.85mm, the thickness of the L5L6 interlayer dielectric layer 56 is designed to be 0.12mm, when the PCB composed of the first core board 110, the second core board 120, and the third core board 130 is laminated, a problem of asymmetry of dielectric layers of the laminated structure may occur.

Example 1

Fig. 3 shows a PCB laminated structure provided by the present embodiment, and the PCB laminated structure of the present embodiment is mainly used for solving the problem of asymmetric copper thickness of a core board in the multi-layer PCB laminated structure shown in fig. 1.

As shown in fig. 3, in the present embodiment, the PCB laminated structure includes a first sub-laminated structure 100 and a second sub-laminated structure 200. In which the first-time laminated structure 100 is a structure in which lamination has been completed.

In the present embodiment, the second sub-laminated structure 200 includes the first sub-laminated structure 100 disposed at the center thereof, and the L1 layer 10 and the L6 layer 60 respectively disposed at both sides of the first sub-laminated structure 100, for example, the L1 layer may be disposed at the L2 layer 20 side of the first sub-laminated structure 100, and the L6 layer 60 may be disposed at the L5 layer 50 side of the first sub-laminated structure 100.

In this embodiment, an L1L2 interlayer dielectric layer 12 is disposed between the L1 layer 10 and the first-time laminated structure 100.

The L1L2 interlayer dielectric layer 12 may include a plurality of layers. For example, in the present embodiment, the L1L2 interlayer dielectric layer 12 may include two layers, namely, a first L1L2 interlayer dielectric layer 121 and a second L1L2 interlayer dielectric layer 122.

In this embodiment, an L5L6 interlevel dielectric layer 56 is disposed between the L6 layer 60 and the first-time laminated structure 100.

The L5L6 interlayer dielectric layer 56 may include multiple layers. For example, in the present embodiment, the L5L6 interlayer dielectric layer 56 may include two layers, i.e., a first L5L6 interlayer dielectric layer 561 and a second L5L6 interlayer dielectric layer 562.

As shown in fig. 4, in the present embodiment, the first-time laminated structure 100 includes an L2 layer 20, an L3 layer 30, an L4 layer 40, and an L5 layer 50, which are sequentially arranged. Wherein the first laminated structure 100 is laminated before the second laminated structure 200.

In this embodiment, an L3L4 interlayer dielectric layer 34 may be disposed between the L3 layer 30 and the L4 layer 40, and the L3L4 interlayer dielectric layer 34 is located at the center of the first lamination structure.

In this embodiment, an L2L3 interlayer dielectric layer 23 may be disposed between the L2 layer 20 and the L3 layer 30.

The L2L3 interlayer dielectric layer 23 may include a plurality of layers. For example, in the embodiment, the L2L3 interlayer dielectric layer 23 may include three layers, i.e., a first L2L3 interlayer dielectric layer 231, a second L2L3 interlayer dielectric layer 232, and a third L2L3 interlayer dielectric layer 233.

In this embodiment, an L4L5 interlayer dielectric layer 45 may be disposed between the L4 layer 40 and the L5 layer 50.

The L4L5 interlayer dielectric layer 45 may include a plurality of layers. For example, in the present embodiment, the L4L5 interlayer dielectric layer 45 may include three layers, i.e., a first L4L5 interlayer dielectric layer 451, a second L4L5 interlayer dielectric layer 452, and a third L4L5 interlayer dielectric layer 453.

In the present embodiment, the first-time lamination structure 100 may be equivalent to a structure for laminating the second core board 120 composed of the L3 layers 30, the L3L4 interlayer dielectric layers 34, and the L4 layers 40, and the L3 layers 30 and the L4 layers 40 in the second core board 120 have the same thickness, so that the core board copper thickness structure in the first-time lamination structure 100 is symmetrical. In the second sub-laminate structure 200, the first sub-laminate structure 100 may be equivalent to a composite core panel in which the L2 layers 20 are the same thickness as the L5 layers 50, and thus the core panel copper thickness structure in the second sub-laminate structure 200 is also symmetrical.

In summary, in the embodiment, the primary lamination asymmetric structure of the PCB is adjusted to the secondary lamination symmetric structure, so that the rejection caused by layer deviation and board warping of the PCB can be effectively avoided.

Example 2

Fig. 5 shows a PCB laminated structure provided by the present embodiment, which includes a first sub-laminated structure 100 and a second sub-laminated structure 200. In which the first-time laminated structure 100 is a structure in which lamination has been completed.

As shown in fig. 6, in the present embodiment, the first-time laminated structure 100 includes an L2 layer 20, an L3 layer 30, an L4 layer 40, and an L5 layer 50, which are sequentially arranged. Wherein the first laminated structure 100 is laminated before the second laminated structure 200.

In this embodiment, the first-time laminated structure 100 may be equivalent to a structure for laminating the second core board 120 composed of the L3 layers 30, the L3L4 interlayer dielectric layers 34, and the L4 layers 40, and there is no problem of asymmetry of the dielectric layers in the second core board 120, and thus, the structure of the dielectric layers in the first-time laminated structure 100 is symmetrical. In the second sub-laminate structure 200, the first sub-laminate structure 100 may be equivalent to a composite core board, and the first sub-laminate structure 100 is equivalent to a composite core board without the problem of asymmetry of the dielectric layers, so the structure of the dielectric layers in the second sub-laminate structure 200 is also symmetric.

Example 3

The present embodiment provides a PCB, wherein the PCB of the present embodiment is a PCB with different voltage endurance requirements of each layer, and the PCB of the present embodiment is a multilayer board with asymmetric Core thickness.

In this embodiment, the PCB may be formed by laminating the PCB laminated structures described in embodiment 1 or embodiment 2, and the double-lamination structure solves the problem of poor warpage caused by the deviation of the multilayer asymmetric PCB layer and the structural asymmetry.

The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A PCB laminated structure is characterized by comprising a first laminated structure and a second laminated structure, wherein the second laminated structure comprises the first laminated structure arranged at the center, an L1 layer and an interlayer dielectric layer arranged at one side of the first laminated structure, and an L6 layer and an interlayer dielectric layer arranged at the other side of the first laminated structure.

2. The PCB laminate structure of claim 1, wherein the number of dielectric layers between the L1 layer and the first secondary laminate structure is the same as the number of dielectric layers between the L6 layer and the first secondary laminate structure.

3. The PCB laminate structure of claim 2, wherein the number of dielectric layers between the L1 layer and the first secondary laminate structure and between the L6 layer and the first secondary laminate structure is at least 1.

4. The PCB laminate structure of claim 3, wherein a number of dielectric layers between the L1 layer and the first sub-laminate structure and between the L6 layer and the first sub-laminate structure is 2.

5. The PCB laminate structure of any one of claims 1-4, wherein the first laminate structure comprises sequentially disposed L2 layer, L3 layer, L4 layer, L5 layer, and interlayer dielectric layer disposed between adjacent two layers.

6. The PCB laminate structure of claim 5, wherein a number of dielectric layers between the L2 layer and the L3 layer is the same as a number of dielectric layers between the L4 layer and the L5 layer.

7. The PCB laminate structure of claim 6, wherein the number of dielectric layers between the L2 layer and the L3 layer and between the L4 layer and the L5 layer is 3.

8. A PCB board laminated with the PCB laminate structure of any one of claims 1 to 7.