CN211929503U

CN211929503U - Solar cell

Info

Publication number: CN211929503U
Application number: CN201922393630.0U
Authority: CN
Inventors: 姚骞; 常青; 马列; 张家峰; 王秀鹏
Original assignee: Tongwei Solar Meishan Co Ltd
Current assignee: Tongwei Solar Meishan Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-11-13
Anticipated expiration: 2029-12-26

Abstract

The utility model relates to a solar cell piece, it includes the base member piece and sets up the grid line on the base member piece, and the base member piece includes silicon chip and passivation layer. The passivation layer is arranged on the surface of the silicon chip, a plurality of accommodating holes penetrating along the height direction of the passivation layer are formed in the passivation layer, top openings are formed in the outer surface of the accommodating holes, and the bottoms of the accommodating holes are sealed by the silicon chip. The gate line includes two portions connected to each other, wherein the second portion is located on an outer surface of the passivation layer, and the first portion enters the receiving hole through the top opening to be fixed in the receiving hole and contacts the silicon wafer at the bottom of the receiving hole. The utility model discloses a passivation layer of solar wafer is provided with the accommodation hole, and the grid line is in the contact of accommodation hole bottom and silicon chip, and this area of contact is less, can effectively reduce grid line and silicon chip contact and the complex that leads to, can show promotion battery conversion efficiency.

Description

Solar cell

Technical Field

The utility model relates to an energy field especially relates to a solar wafer.

Background

With the increasing consumption of conventional fossil energy such as global coal, oil, natural gas and the like, the ecological environment is continuously deteriorated, and particularly, the sustainable development of the human society is seriously threatened due to the increasingly severe global climate change caused by the emission of greenhouse gases. Various countries in the world make respective energy development strategies to deal with the limitation of conventional fossil energy resources and the environmental problems caused by development and utilization. Solar energy has become one of the most important renewable energy sources by virtue of the characteristics of reliability, safety, universality, long service life, environmental protection and resource sufficiency, and is expected to become a main pillar of global power supply in the future.

In a new energy revolution process, the photovoltaic industry in China has grown into a strategic emerging industry with international competitive advantages. However, the development of the photovoltaic industry still faces many problems and challenges, and the conversion efficiency and reliability are the biggest technical obstacles restricting the development of the photovoltaic industry, while the cost control and the scale-up are economically restricted.

In recent years, various novel crystal silicon technologies have emerged. Currently, mainstream crystalline silicon cell technologies in the market, such as passivated back and emitter (PERC, PERL, PERT), passivated contacts (TOPCon, POLO), heterojunction (HJT, HIT, HDT) solar cells, etc., can reach a mainstream production efficiency of over 22%. At present, more than 98% of battery technologies in the market adopt a grid line screen printing mode to form a front metal electrode, silver paste is extruded to penetrate through meshes of a screen printing plate and penetrate to the surface of a silicon wafer to form a grid line with a certain height and width, and the grid line and the silicon wafer are in good contact through high-temperature sintering. The screen printing grid line is a necessary process for preparing the mainstream crystalline silicon cell at present, and has great influence on the conversion efficiency of the solar cell. However, the grid lines printed on the mainstream crystalline silicon solar cell at present burn through the passivation film on the surface of the cell and then are in full contact with the silicon wafer. Because the contact area of the grid line and the silicon wafer is large, a large number of carriers are compounded at a contact point, and therefore the open-circuit voltage and the conversion efficiency of the battery are low.

There is therefore a need to provide a novel solar cell to at least partially solve the above problems.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a solar wafer. The utility model discloses a grid line is less with the area of contact of silicon chip, can effectively reduce grid line and silicon chip contact and the complex that leads to, can show promotion battery conversion efficiency.

Specifically, the passivation layer of the solar cell is provided with an accommodating hole which penetrates through the passivation layer up and down, a first part of the grid line for guiding out the carrier is accommodated in the accommodating hole, and a second part of the grid line for transmitting the carrier to another grid line is positioned on the outer surface of the passivation layer. The second portion may be made of a conductive material having a relatively weak fire-through capability such that the second portion does not fire through the passivation layer and contacts the silicon wafer, and thus only the first portion within the receiving hole contacts the silicon wafer.

The utility model provides a solar wafer, solar wafer includes the base member piece and sets up grid line on the base member piece, the base member piece includes:

a silicon wafer;

a passivation layer disposed on the surface of the silicon wafer, the passivation layer having a plurality of receiving holes penetrating along a height direction thereof, the receiving holes having top openings on an outer surface of the passivation layer, and bottoms of the receiving holes reaching the silicon wafer,

the grid line comprises two parts which are connected with each other, wherein the second part is positioned on the outer surface of the passivation layer, the first part enters the accommodating hole through the top opening to be fixed in the accommodating hole, and is in contact with the silicon chip at the bottom of the accommodating hole.

In one embodiment, the first portion has a greater burn-through capability than the second portion; or

The second part and the first part are grid lines made of the same material.

In one embodiment, the grid lines are secondary grid lines, the solar cell further comprises a main grid line crossing each secondary grid line, and the burning-through capacity of the main grid line is stronger than that of the second part of the secondary grid line.

In one embodiment, the second portion and/or the first portion is a grid line made of one of silver, metal alloy, copper, conductive paste, and transparent conductive film.

In one embodiment, the projection of the receiving opening onto a plane parallel to the silicon wafer is circular, rectangular, triangular or irregular polygonal.

In one embodiment, the maximum radial dimension of the receiving hole is in the range of 0.00004mm²-1mm²。

In one embodiment, the passivation layer is at least one of a silicon nitride passivation film, a silicon oxide passivation film, an aluminum oxide passivation film, a silicon carbide passivation film, a polysilicon passivation film, an amorphous silicon passivation film, and a silicon oxynitride passivation film.

In one embodiment, the main grid line is a grid line made of silver, aluminum, silver aluminum, copper plating, conductive adhesive, graphene and a transparent conductive film.

In one embodiment, the accommodating holes are arranged at equal intervals on the passivation layer along the length direction or the width direction of the solar cell.

In one embodiment, the gate line is a main gate line.

According to the utility model discloses, be provided with the accommodation hole that runs through from top to bottom on the passivation layer of solar wafer, the first part that is used for deriving the carrier of vice grid line holds in the accommodation hole, and the second part that is used for of vice grid line is located the passivation layer with carrier transmission to main grid line is located on the surface. The second portion may be made of a conductive material having a relatively weak fire-through capability such that the second portion does not fire through the passivation layer and contacts the silicon wafer, and thus only the first portion within the receiving hole contacts the silicon wafer. And because the contact area of the first part and the silicon chip is smaller, the composition caused by the contact of the auxiliary grid line and the silicon chip can be effectively reduced, and the conversion efficiency of the battery can be obviously improved.

Drawings

For a better understanding of the above and other objects, features, advantages and functions of the present invention, reference should be made to the preferred embodiments illustrated in the accompanying drawings. Like reference numerals in the drawings refer to like parts. It will be appreciated by persons skilled in the art that the drawings are intended to illustrate preferred embodiments of the invention without any limiting effect on the scope of the invention, and that the various components in the drawings are not to scale.

Fig. 1 is a plan view of a solar cell sheet according to a preferred embodiment of the present invention;

3 FIG. 32 3 is 3 a 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 A 3- 3 A 3 of 3 FIG. 31 3; 3

3 fig. 3 3 3 is 3 another 3 possible 3 cross 3- 3 sectional 3 view 3 taken 3 along 3 line 3 a 3- 3 a 3 of 3 fig. 31 3. 3

Detailed Description

Referring now to the drawings, specific embodiments of the present invention will be described in detail. What has been described herein is merely a preferred embodiment in accordance with the present invention, and those skilled in the art will appreciate that other ways of implementing the present invention on the basis of the preferred embodiment will also fall within the scope of the present invention.

The utility model provides a solar cell. Fig. 1 to 3 show a preferred embodiment of a solar cell sheet according to the present invention.

The solar cell 10 may be an aluminum back surface field crystalline silicon solar cell, a PERC cell, a TOPCon cell, a PERT cell, an HJT cell, a crystalline silicon stacked cell, or the like. The solar cell comprises a substrate sheet and main grid lines 4 and auxiliary grid lines 3 arranged on the surface of the substrate sheet, wherein the substrate sheet further comprises a silicon wafer 1 and a passivation layer 2, and the main grid lines 4 can cross over the auxiliary grid lines 3 to connect the auxiliary grid lines 3.

In the embodiment shown in fig. 1 and 2, the passivation layer 2 is disposed on the top surface of the silicon wafer 1, and the passivation layer 2 is provided with a plurality of receiving holes 21 penetrating in the height direction thereof (i.e., the direction D1 shown in fig. 2), the receiving holes 21 being provided with top openings 23 on the outer surface of the passivation layer 2, and the bottoms 22 of the receiving holes 21 opening into the silicon wafer 1. The receiving hole 21 is for receiving a portion of the finger 3. The receiving holes 21 may be arranged at equal intervals along the length direction or the width direction (e.g., the direction D2 shown in fig. 2) of the solar cell sheet 10 on the passivation layer 2 to uniformly receive the conductive material for forming the sub-grid lines 3.

It should be noted that the references herein to "outside" and "inside" of a feature refer to the side of the feature farther from the silicon wafer 1 and the side closer to the silicon wafer 1 in the first direction D1. In particular, the passivation layer 2 shown in fig. 2 has an outer surface which is a surface of the passivation layer 2 far from the silicon wafer 1, and a bottom which is a portion of the passivation layer 2 close to the silicon wafer 1.

The finger 3 further includes a first portion 32 and a second portion 31 connected to each other, the first portion 32 enters the receiving hole 21 through the top opening 23 to be fixed in the receiving hole 21, and contacts the silicon wafer 1 at the bottom 22 of the receiving hole 21 for discharging the current carriers of the battery; the second portion 31 is located on an outer surface of the passivation layer 2 for transporting carriers to the bus bars. And because the contact area of the secondary grid line 3 and the silicon chip 1 is only the area of the bottom surface of the accommodating hole 21, the area is small, the recombination caused by the contact of the secondary grid line 3 and the silicon chip 1 can be reduced, and the battery conversion efficiency can be obviously improved.

Preferably, the first portion 32 and the second portion 31 of the finger 3 may be made of different materials, and the burning-through capability of the first portion 32 is higher than that of the second portion 31. Specifically, the first portion 32 may be made of a conductive material with a strong burn-through capability, and the second portion 31 may be made of a conductive material with a weak burn-through capability. Since the second portion 31 is made of a conductive material with a weak burn-through capability, the second portion 31 does not burn through the passivation layer 2 at the top side of the passivation layer 2 either. More preferably, the burn-through capability of the second portion 31 is also simultaneously weaker than the burn-through capability of the bus bars. Alternatively, in other embodiments, the first portion 32 and the second portion 31 may be made of the same conductive material.

In this embodiment, the first portion 32, the second portion 31 and the main gate line of the sub-gate line 3 may be made of conductive materials such as silver paste, metal alloy, copper electrode, conductive adhesive, transparent conductive film, and the like.

In other embodiments, not shown, it may be that the bus bar is configured to have two portions, a first portion of which is received in the receiving hole and a second portion of which is located on the surface of the passivation layer. In addition, unless otherwise specified, the term "gate line" may refer to both the main gate line and the sub-gate line, and may also refer to both the main gate line and the sub-gate line.

The shape of the receiving opening 21 of the passivation layer 2 can also be chosen in many ways. For example, the projection of the receiving hole 21 on a plane parallel to the silicon wafer 1 is a circle, a rectangle, a triangle, or an irregular polygon, and the maximum radial dimension of the receiving hole 21 ranges from 0.00004mm²-1mm²。

In the present embodiment, the passivation layer 2 may have a single-layer structure or a stacked-layer structure of one or more of a silicon nitride passivation film, a silicon oxide passivation film, an aluminum oxide passivation film, a silicon carbide passivation film, a polysilicon passivation film, an amorphous silicon passivation film, and a silicon oxynitride passivation film. In the present embodiment, only the passivation layer 2 disposed on the top side of the silicon wafer 1 is provided with the receiving holes 21, and the passivation layer 2 may be disposed on the bottom side of the silicon wafer 1, but the passivation layer 2 disposed on the bottom side of the silicon wafer 1 may have another structure, for example, the receiving holes 21 are not provided.

Fig. 3 shows a portion of a cross-sectional view of another alternative embodiment of the present invention. In fig. 3, both the top and bottom surfaces of a silicon wafer 1 are provided with a passivation layer 2 having an accommodation hole 21. The receiving opening 21 of the top passivation layer 24 has a top opening 23 and a bottom 22 sealed by the silicon wafer 1, and the receiving opening 21 of the bottom passivation layer 25 likewise has a top opening 23 and a bottom 22 sealed by the silicon wafer 1. It will be understood that the directional terms "top" and "bottom" as used herein refer to the portions thereof away from the silicon die 1 and the portions thereof near the silicon die 1 for a particular receiving hole 21, respectively.

As shown in fig. 3, the first portions 32 of the finger lines 3 on the top and bottom sides of the silicon chip 1 can be accommodated in the corresponding accommodating holes 21, so that the contact areas between the finger lines 3 on the top and bottom sides of the silicon chip 1 and the silicon chip 1 are smaller, recombination caused by contact between the finger lines 3 and the silicon chip 1 can be reduced, and the battery conversion efficiency can be significantly improved.

The preferred embodiment of the present invention also provides a method for manufacturing the solar cell as above, which includes a step of manufacturing a solar cell piece integral piece and a step of splitting, wherein the step of manufacturing the solar cell piece integral piece includes a step of providing a base sheet and a step of applying a gate line on the base sheet.

Wherein, the step of arranging the base sheet sequentially comprises the following steps: arranging a silicon wafer; a passivation layer is arranged on the surface of the silicon wafer, and a plurality of accommodating holes penetrating along the height of the passivation layer are processed on the passivation layer, so that the accommodating holes are provided with top openings on the outer surface of the passivation layer, and the bottoms of the accommodating holes are sealed by the silicon wafer. Of course, the step of providing the base sheet preferably includes other steps, and the base sheet preferably includes other structures in addition to the silicon wafer and passivation layer shown in fig. 2 and 3.

The step of applying the gate lines to set the gate lines includes applying secondary gate lines, the step of applying the secondary gate lines including: and applying a conductive material on the outer surface of the passivation layer, so that one part of the conductive material enters the accommodating hole through the top opening and is fixed in the accommodating hole after sintering to form a first part of the secondary grid line, the other part of the conductive material is fixed on the outer surface of the passivation layer after sintering to form a second part of the secondary grid line, and the first part is in contact with the silicon wafer at the bottom of the accommodating hole.

Preferably, if the first and second portions of the finger are made of different conductive materials, the step of applying the finger may further comprise the steps of, in order: injecting a first conductive material into the accommodating hole through the top opening of the accommodating hole and sintering the first conductive material to form a first part of the secondary grid line; a second conductive material is applied to the outer surface of the passivation layer and sintered to form a second portion of the subgrid, the second portion connecting the respective first portions together at the top thereof. That is, the first portion and the second portion may be separately processed, and a first conductive material may be applied on the surface of the silicon wafer to form the first portion, and then a second conductive material may be applied to form the second portion. Preferably, the burn-through capability of the first conductive material is greater than the burn-through capability of the second conductive material.

Preferably, the step of providing the gate lines further comprises applying the main gate lines using a third conductive material after applying the sub-gate lines, the second conductive material preferably having a burn-through capability less than the third conductive material.

If the first and second portions of the finger are made of the same conductive material, the first and second portions of the finger can be processed in a single process, for example, the process can be: and continuously applying the same conductive material on the outer surface of the passivation layer, so that part of the conductive material enters the accommodating hole and the other part of the conductive material is positioned on the outer surface of the passivation layer, and then sintering and fixing the conductive material.

The first conductive material and the second conductive material can be silver paste, metal alloy, copper electrodes, conductive adhesive and transparent conductive films. The third conductive material can be silver paste, aluminum paste, silver-aluminum paste, copper plating, conductive adhesive, graphene, transparent conductive film and metal alloy.

The grid lines are preferably applied by means of a screen-infiltration process.

Preferably, the receiving hole is machined by laser drilling. And a plurality of receiving holes may be formed in the passivation layer at regular intervals in the length direction or the width direction of the solar cell sheet.

Also preferably, the receiving hole may be processed such that a projection of the receiving hole on a plane parallel to the silicon wafer is a circle, a rectangle, a triangle, or an irregular polygon, and such that a maximum radial dimension of the receiving hole ranges from 0.00004mm²-1mm²。

Preferably, the passivation layer may be provided using at least one of silicon nitride, silicon oxide, aluminum oxide, silicon carbide, polysilicon, amorphous silicon, and silicon oxynitride.

In this embodiment, the passivation layer is provided with an accommodation hole in which a first portion of the sub-gate line for guiding out carriers is accommodated, and a second portion of the sub-gate line for transmitting the carriers to the main gate line is located on an outer surface of the passivation layer. The second portion may be made of a conductive material with a relatively weak fire-through capability so that the portion does not fire through the passivation layer and contact the silicon wafer. The first part of the secondary grid line is in direct contact with the silicon wafer, the area is small (similar to point contact), the composition caused by contact of the secondary grid line and the silicon wafer can be effectively reduced, and the conversion efficiency of the battery can be remarkably improved.

The foregoing description of various embodiments of the invention is provided to one of ordinary skill in the relevant art for the purpose of illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. As noted above, various alternatives and modifications of the present invention will be apparent to those skilled in the art of the above teachings. Thus, while some alternative embodiments are specifically described, other embodiments will be apparent to, or relatively easily developed by, those of ordinary skill in the art. The present invention is intended to embrace all such alternatives, modifications and variances of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention as described above.

Reference numerals:

solar cell piece 10

Silicon wafer 1

Passivation layer 2

Secondary grid line 3

Receiving hole 21

Bottom 22 of the receiving hole

Top passivation layer 24

Bottom passivation layer 25

Top opening 23 of the receiving hole

The first portion 32 of the finger line

Second portion 31 of the secondary grid line

Claims

1. A solar cell sheet, comprising a substrate sheet and a grid line disposed on the substrate sheet, wherein the substrate sheet comprises:

a silicon wafer;

wherein the gate line includes a first portion and a second portion connected to each other, the first portion entering the receiving hole through the top opening to be fixed in the receiving hole and contacting the silicon wafer at the bottom of the receiving hole, the second portion being on an outer surface of the passivation layer.

2. Solar cell sheet according to claim 1,

the first portion has a burn-through capability greater than the second portion; or

The second part and the first part are grid lines made of the same material.

3. The solar cell sheet according to claim 1, wherein the grid lines are secondary grid lines, and the solar cell sheet further comprises a main grid line crossing each of the secondary grid lines, and wherein the burn-through capability of the main grid line is stronger than the burn-through capability of the second portion of the secondary grid line.

4. The solar cell sheet according to claim 1, wherein the second portion and/or the first portion is a grid line made of one of silver, metal alloy, copper, conductive paste, and transparent conductive film.

5. The solar cell piece according to claim 1, wherein the projection of the accommodating hole on a plane parallel to the silicon wafer is circular, rectangular, triangular or polygonal.

6. The solar cell piece of claim 1, wherein the maximum radial dimension of the receiving hole is in the range of 0.00004mm²-1mm²。

7. The solar cell of claim 1, wherein the passivation layer is at least one of a silicon nitride passivation film, a silicon oxide passivation film, an aluminum oxide passivation film, a silicon carbide passivation film, a polysilicon passivation film, an amorphous silicon passivation film, and a silicon oxynitride passivation film.

8. The solar cell sheet according to claim 3, wherein the main grid line is a grid line made of one of silver, aluminum, silver aluminum, copper plating, conductive adhesive, graphene, and transparent conductive film.

9. The solar cell sheet according to claim 1, wherein the accommodating holes are arranged at equal intervals on the passivation layer along a length direction or a width direction of the solar cell sheet.

10. The solar cell of claim 1, wherein the grid lines are bus bars.