CN110890433A - Grid line structure, solar cell, laminated tile assembly, printing method and manufacturing method - Google Patents
Grid line structure, solar cell, laminated tile assembly, printing method and manufacturing method Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Sustainable Energy (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention relates to a grid line structure, a solar cell, a laminated tile assembly, a printing method and a manufacturing method. The grid line structure is located the top surface and/or the bottom surface of base member piece and includes first layer grid line and second layer grid line, first layer grid line and the silicon chip direct contact of base member piece, the second layer grid line setting is in the one side relative with the base member piece of first layer grid line and with the membrane contact on the silicon chip, the first layer grid line of each two-layer formula grid line includes a plurality of punctiform structures, the punctiform structure is arranged at interval in the extending direction of two-layer formula grid line, and the width of punctiform structure is greater than the width of second layer grid line. According to the invention, the first layer of grid lines are in a dot structure, and the width of the first layer of grid lines is larger than that of the second layer of grid lines, so that the second layer of grid lines can be conveniently aligned to the first layer of grid lines in production and manufacturing on the basis of reducing the composition caused by contact between the grid lines and a silicon wafer, and the processing precision and the processing efficiency are improved.
Description
Technical Field
The invention relates to the field of energy, in particular to a grid line structure of a crystalline silicon solar cell, a printing method, a solar cell, a laminated tile assembly and a manufacturing method.
Background
With the increasing consumption of conventional fossil energy such as global coal, oil, natural gas and the like, the ecological environment is continuously deteriorated, and particularly, the sustainable development of the human society is seriously threatened due to the increasingly severe global climate change caused by the emission of greenhouse gases. Various countries in the world make respective energy development strategies to deal with the limitation of conventional fossil energy resources and the environmental problems caused by development and utilization. Solar energy has become one of the most important renewable energy sources by virtue of the characteristics of reliability, safety, universality, long service life, environmental protection and resource sufficiency, and is expected to become a main pillar of global power supply in the future.
In a new energy revolution process, the photovoltaic industry in China has grown into a strategic emerging industry with international competitive advantages. Currently, mainstream crystalline silicon cell technologies in the photovoltaic industry on the market, such as passivated back and emitter (PERC, PERL, PERT), passivated contacts (TOPCon, POLO), heterojunction (HJT, HIT, HDT) solar cells, etc., have a mainstream production efficiency of over 22%. However, the development of the photovoltaic industry still faces many problems and challenges, and the conversion efficiency and reliability are the biggest technical obstacles restricting the development of the photovoltaic industry, while the cost control and the scale-up are economically restricted. The photovoltaic module is taken as a core component of photovoltaic power generation, and the development of high-efficiency modules by improving the conversion efficiency of the photovoltaic module is a necessary trend. Various high efficiency modules, such as shingles, half-sheets, multi-master grids, double-sided modules, etc., are currently emerging on the market. With the application places and application areas of the photovoltaic module becoming more and more extensive, the reliability requirement of the photovoltaic module becomes higher and higher, and particularly, the photovoltaic module with high efficiency and high reliability needs to be adopted in some severe or extreme weather frequent areas.
Under the background of vigorous popularization and use of green solar energy, the shingled assembly utilizes the electrical principle of low current and low loss (the power loss of the photovoltaic assembly is in direct proportion to the square of working current) so as to greatly reduce the power loss of the assembly. And secondly, the inter-cell distance region in the cell module is fully utilized to generate electricity, so that the energy density in unit area is high. In addition, the conventional photovoltaic metal welding strip for the assembly is replaced by the conductive adhesive with the elastomer characteristic at present, the photovoltaic metal welding strip shows higher series resistance in the whole battery, and the stroke of a current loop of the conductive adhesive is far smaller than that of a welding strip, so that the laminated assembly becomes a high-efficiency assembly, and meanwhile, the outdoor application reliability is more excellent than that of the conventional photovoltaic assembly, and the laminated assembly avoids stress damage of the metal welding strip to the interconnection position of the battery and other confluence areas. Especially, under the dynamic (load action of natural world such as wind, snow and the like) environment with alternating high and low temperatures, the failure probability of the conventional assembly which is interconnected and packaged by adopting the metal welding strips is far higher than that of the laminated assembly which is interconnected and cut by adopting the conductive adhesive of the elastomer and packaged by the crystalline silicon battery small pieces.
The mainstream technology of the current tile stack assembly is to use a conductive adhesive to interconnect the cut battery pieces, wherein the conductive adhesive mainly comprises a conductive phase and a bonding phase. The conductive phase mainly comprises precious metals, such as pure silver particles or particles of silver-coated copper, silver-coated nickel, silver-coated glass and the like, and is used for conducting electricity among solar cells, the particle shape and distribution of the precious metals are based on the requirement of optimal electricity conduction, and at present, more flake-shaped or sphere-like combined silver powder with the D50 being less than 10 mu m is adopted. The adhesive phase is mainly composed of a high molecular resin polymer having weather resistance, and acrylic resin, silicone resin, epoxy resin, polyurethane, and the like are usually selected in accordance with the adhesive strength and weather resistance. In order to enable the conductive adhesive to achieve low contact resistance, low volume resistivity and high adhesion and maintain long-term excellent weather resistance, a conductive adhesive manufacturer can generally complete the design of a conductive phase and an adhesive phase formula, so that the performance stability of the laminated tile assembly under an initial stage environment corrosion test and long-term outdoor practical application is ensured.
Electrodes are typically applied to the solar cell sheets. At present, more than 98% of battery technologies in the market adopt a screen printing silver grid line mode to form grid lines, silver paste is extruded to penetrate through meshes of a screen printing plate and penetrate to the surface of a silicon wafer to form the silver grid lines with certain height and width, and the silver grid lines are in good contact with the silicon wafer through high-temperature sintering. The screen printing of silver electrodes is a necessary process for the preparation of the current mainstream crystalline silicon cell, and has a great influence on the conversion efficiency of the solar cell. However, all the existing front silver electrode screen printing graphic designs adopt straight lines, the formed grid line is in a linear structure in full contact with the silicon wafer, and the current carriers caused by the contact of the grid line and the silicon wafer are compounded, so that the improvement of the conversion efficiency of the battery is limited.
In order to solve the problem, a layer of dotted line type gate line can be arranged firstly when the gate line is arranged, and then a second layer of gate line is arranged on the dotted line type gate line, but the process still has a problem: when the second layer of gate lines is provided, it is difficult to align the second layer of gate lines with the dashed-line gate lines, which may result in a case where the extending direction of the second layer of gate lines and the extending direction of the dashed-line gate lines are deviated from each other.
It is therefore desirable to provide a grid line structure, a solar cell sheet, a shingle assembly, a printing method, and a manufacturing method that at least partially address the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a grid line structure, a solar cell, a laminated tile assembly, a printing method and a manufacturing method.
In addition, the invention also provides the preferable arrangement of the materials, shapes, sizes and the like of the first layer of grid lines, the second layer of grid lines and other structures of the solar cell, so that the base sheet, the secondary grid lines, the main grid lines and other parts can be well adapted, and the solar cell can have stable characteristics and excellent performance.
According to one aspect of the present invention, there is provided a gate line structure for a crystalline silicon solar cell, the crystalline silicon solar cell comprising a substrate sheet comprising a silicon wafer and films disposed on top and bottom surfaces of the silicon wafer,
the grid line structure is located the top surface and/or the bottom surface of base member piece, and the grid line structure is two-layer formula grid line, and it includes:
the first layer of grid lines are in direct contact with the silicon wafer, the first layer of grid lines of each two-layer type grid line are of a plurality of point-shaped structures, and the point-shaped structures are arranged at intervals in the extending direction of the two-layer type grid lines; and
a second layer of gate lines disposed on a side of the first layer of gate lines opposite the base sheet, and a portion of a surface of the second layer of gate lines facing the base sheet is in contact with the first layer of gate lines, and another portion is in contact with the film,
and the width of the dot structure is greater than that of the grid line of the second layer.
In one embodiment, the two-layer gate lines extend along a first direction, and for any two adjacent two of the two-layer gate lines, the dot structures of the two first-layer gate lines are staggered in a direction perpendicular to the first direction and parallel to the substrate sheet.
In one embodiment, the dot-like structure is a dot structure, an elliptical dot structure, a ring-like dot structure, a square dot structure, or a polygonal dot structure.
In one embodiment, the second layer of gate lines is continuously disposed in an extending direction thereof.
In one embodiment, the first layer of grid lines has a burn-through capability that is greater than a burn-through capability of the second layer of grid lines.
In one embodiment, the width of the dot structure is 5 μm to 500 μm, and the width of the grid line of the second layer is 5 μm to 150 μm.
In one embodiment, the distance between two adjacent dot structures is 0.3mm to 4 mm.
In one embodiment, the first layer of gate lines is gate lines made of silver paste or silver-aluminum paste, and the second layer of gate lines is gate lines made of one of silver paste, metal alloy, copper electrodes, conductive adhesive and transparent conductive film.
In one embodiment, the film is intermittently disposed on the silicon wafer to reserve a space for the first layer of gate lines.
In one embodiment, the grid line structure is a main grid line or a secondary grid line of the crystalline silicon solar cell.
According to another aspect of the present invention, there is provided a solar cell sheet including:
a substrate sheet comprising a silicon wafer and films disposed on top and bottom surfaces of the silicon wafer;
main grid lines and auxiliary grid lines, wherein the main grid lines and the auxiliary grid lines are arranged on the top surface and the bottom surface of the base piece, the auxiliary grid lines are arranged at intervals, the main grid lines cross each auxiliary grid line,
at least one of the main gate line on the top surface, the sub-gate line on the top surface, the main gate line on the bottom surface, and the sub-gate line on the bottom surface is the gate line structure according to any one of the above aspects.
In one embodiment, only the secondary gate lines are the gate line structure, and the burn-through capability of the main gate line is stronger than that of the first layer of gate lines of the gate line structure.
In one embodiment, the main grid line is fixed on the substrate sheet through a main grid welding point, wherein the projection of the main grid welding point on the substrate sheet is formed into a rectangle, and the length dimension and the width dimension of the rectangle are 0.1mm-2.0 mm.
In one embodiment, for one main gate line, the distance between two adjacent main gate pads for fixing the main gate line is 6mm to 40 mm.
In one embodiment, the extending direction of the main gate line is perpendicular to the extending direction of the sub gate line.
In one embodiment, the bus bars of the top surface and/or the bottom surface are intermittently arranged in the extending direction thereof, and the solar cell sheets are configured such that the bus bars on the surfaces of any two adjacent solar cell sheets facing each other are at least partially aligned with each other in a direction perpendicular to the base sheet.
In one embodiment, the bus bars of the top and bottom surfaces are formed in a zigzag structure, and the facing bus bars of two solar cells are in contact with each other in a rack-and-pinion manner when the two solar cells are connected in a shingled manner.
In one embodiment, the film is a passivation film or an antireflective film.
According to another aspect of the present invention, a laminated assembly is provided, wherein the laminated assembly is formed by arranging the solar cells according to any one of the above aspects in a laminated manner.
In one embodiment, the minor grid lines of the solar cell pieces extend along a first direction, a plurality of the solar cell pieces are sequentially arranged along a third direction in a tiling mode, the major grid lines of the solar cell pieces extend along a second direction, the first direction is consistent with the third direction, and the second direction is perpendicular to the third direction.
According to a fourth aspect of the present invention, there is provided a printing method for printing a gate line structure according to any one of the above aspects on a top surface and/or a bottom surface of a base sheet, the base sheet comprising a silicon wafer and a film on a surface of the silicon wafer, the method comprising:
applying a first layer of grid lines on the substrate sheet so that the first layer of grid lines directly contacts the silicon wafer;
applying a second layer of gate lines on the second layer of gate lines such that the second layer of gate lines contacts the film.
In one embodiment, the step of applying a first layer of grid lines comprises: a first conductive material is applied to the substrate sheet to form a first layer of gate lines,
the step of applying a second layer of grid lines comprises: applying a second conductive material on the first layer of gate lines to form a second layer of gate lines,
the burning-through capability of the first conductive material is stronger than that of the second conductive material.
According to a fifth aspect of the present invention, there is provided a manufacturing method of a solar cell sheet, the manufacturing method including the steps of:
pretreating a large crystal silicon cell, wherein the pretreatment step comprises the following steps:
preparing a large substrate sheet;
applying secondary grid lines on the top and bottom surfaces of the large substrate sheet;
applying a main grid line on the top surface and the bottom surface of the large substrate sheet;
cutting the silicon crystal battery after the pretreatment into small pieces to form a plurality of solar battery pieces,
wherein at least one of the main gate line on the top surface, the sub-gate line on the top surface, the main gate line on the bottom surface, and the sub-gate line on the bottom surface is a two-layer gate line, and the step of applying the two-layer gate line is implemented based on a printing method according to one of the two schemes.
According to the invention, the solar cell is provided with two layers of grid lines, and the first layer of grid lines is in a dotted structure and is wider than the second layer of grid lines, so that the second layer of grid lines can be conveniently aligned to the first layer of grid lines in production and manufacturing on the basis of reducing the composition caused by contact between the grid lines and a silicon wafer, and the processing precision and the processing efficiency are improved. In addition, the invention also provides the preferable arrangement of the materials, shapes, sizes and the like of the first layer of grid lines, the second layer of grid lines and other structures of the solar cell, so that the base sheet, the secondary grid lines, the main grid lines and other parts can be well adapted, and the solar cell can have stable characteristics and excellent performance.
Drawings
For a better understanding of the above and other objects, features, advantages and functions of the present invention, reference should be made to the preferred embodiments illustrated in the accompanying drawings. Like reference numerals in the drawings refer to like parts. It will be appreciated by persons skilled in the art that the drawings are intended to illustrate preferred embodiments of the invention without any limiting effect on the scope of the invention, and that the various components in the drawings are not drawn to scale.
FIG. 1 is a schematic top view of a crystalline silicon cell wafer according to a preferred embodiment of the invention;
fig. 2 is an enlarged view of a portion a of fig. 1 showing a first layer of gate lines and a second layer of gate lines positioned above the first layer of gate lines;
FIG. 3 is a partial schematic view taken along line B-B of FIG. 2, wherein only the finger lines are shown and the finger lines are omitted, wherein the finger line structure according to the present invention is disposed on both the top and bottom surfaces of the substrate sheet;
fig. 4 is another alternative schematic view of fig. 3, wherein only the top surface of the substrate sheet is provided with a grid line structure according to the present invention;
figure 5 is a schematic view of a shingle assembly according to this embodiment.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. What has been described herein is merely a preferred embodiment in accordance with the present invention and other ways of practicing the invention will occur to those skilled in the art and are within the scope of the invention.
The fabrication of crystalline silicon cells requires multiple steps. For a single-crystal silicon cell piece, it can be obtained as follows. For example, a Czochralski method is used to grow a wafer rod as a raw material. And cutting and slicing by using a cutting machine, cutting and polishing the wafer rod to obtain a square rod, and cutting the square rod obtained after cutting and polishing to obtain the monocrystalline silicon piece. And then, carrying out steps such as surface texturing, cleaning, diffusion junction making, phosphorosilicate glass removal, antireflection film deposition and the like on the monocrystalline silicon wafer. And then screen printing a grid line of the solar cell, and finishing the manufacturing process of the large single crystal cell by a sintering process. According to the large single crystal battery, the front surfaces of the large single crystal batteries are provided with the front main grid lines, the back surfaces of the large single crystal batteries are provided with the back main grid lines, the auxiliary grid lines intersected with the main grid lines are arranged between the main grid lines, and the large single crystal batteries can be divided into small single crystal batteries to form the laminated assembly. The invention improves the grid line structure of the crystalline silicon solar cell.
The invention provides a grid line structure, a printing method, a solar cell, a laminated tile assembly and a manufacturing method, and particularly relates to a grid line structure, a printing method, a solar cell, a laminated tile assembly and a manufacturing method, wherein a preferred embodiment of the invention is shown in figures 1 to 5.
Fig. 1 shows a large crystalline silicon cell 7 according to a preferred embodiment of the present invention, the large crystalline silicon cell 7 can be split into a plurality of solar cells, which can be arranged in a tiling manner to form a tiled assembly. It should be noted that the "first direction" to be mentioned later may be understood as an extending direction of one of the sub-grid lines 2 on the solar cell sheet; the "second direction" can be understood as the extending direction of the bus bars 3 of the solar cell sheet 6; the "third direction" can be understood as the arrangement direction of each solar cell 6 in the laminated tile assembly 5; as used herein, the "width" of a grid line refers to the dimension of the grid line in a direction perpendicular to its direction of extension and parallel to the substrate sheet.
Referring to fig. 2 and 3, the solar cell sheet 6 divided by the large crystalline silicon cell sheet 7 includes a base sheet 1, and the base sheet 1 includes a silicon wafer and films disposed on top and bottom surfaces of the silicon wafer, which may preferably be passivation or antireflective films 12. The top surface and the bottom surface of the substrate sheet 1 of each solar cell sheet 6 are printed with a plurality of secondary grid lines 2 and a plurality of main grid lines 3, the secondary grid lines 2 are arranged at intervals, the main grid lines 3 cross over the secondary grid lines 2 so as to collect current from the secondary grid lines 2, generally, the main grid lines 3 on the top surface of the substrate sheet 1 can also be called as positive electrodes, and the main grid lines 3 on the bottom surface of the substrate sheet 1 can also be called as back electrodes. For any two adjacent solar cells 6, the bus bars 3 on the faces facing each other can contact each other to realize the conductive connection of the two solar cells 6. It should be noted that, unless otherwise specified, the term "contacting" as used herein includes both direct contact and indirect contact via a conductive adhesive or conductive adhesive.
In this embodiment, the extending direction of the main gate line 3 (i.e., the second direction D2) and the extending direction of the sub gate line 2 (i.e., the first direction D1) are both substantially straight lines, and the first direction D1 is perpendicular to the second direction D2. Also, the first direction D1 is also coincident with the third direction D3, that is, the second direction D2 is also perpendicular to the third direction D3. In other embodiments, which are not shown, the extending directions of the main and sub gate lines may have other options, for example, the main and sub gate lines may extend along a curved line, or the angle between the main and sub gate lines may be acute, or the extending directions of the sub gate lines may be offset from the third direction D3.
The invention provides a novel grid line structure of a crystalline silicon battery, namely a two-layer grid line. Specifically, referring to fig. 2 and 3, the solar cell sheet 6 includes such two-layer grid lines, and specifically at least one of the main grid lines 3 on the top surface, the main grid lines 3 on the bottom surface, the sub-grid lines 2 on the top surface, and the sub-grid lines 2 on the bottom surface of the base sheet 1 may be a two-layer grid line. In the present embodiment, the finger lines 2 on the top and bottom surfaces of the base sheet 1 shown in fig. 3 are two-layer finger lines.
With continued reference to fig. 3, it can be seen that the two-layer grid lines of the solar cell 6 include a first layer of grid lines 21 and a second layer of grid lines 22, the first layer of grid lines 21 is in direct contact with the silicon wafer, and the second layer of grid lines 22 is disposed on the side of the first layer of grid lines 21 opposite to the base sheet 1 and above the passivation or antireflective film 12 for contacting the main grid lines 3. The first layer of gate lines 21 of each two-layer gate line includes a plurality of dot-shaped structures arranged at intervals in the extending direction (in this embodiment, the first direction D1), and the second layer of gate lines 22 are continuously arranged in the extending direction (in this embodiment, the first direction D1), so that the sub-gate lines 2 are not in complete contact with the silicon wafer 11 but in intermittent contact with the silicon wafer 11, and thus the contact area between the sub-gate lines 2 and the silicon wafer 11 is greatly reduced, and the purpose of improving the open-circuit voltage and the conversion efficiency of the solar cell 6 is achieved.
Specifically, for the secondary grid lines 2 on the top surface of the base sheet 1 of the solar cell sheet 6, a first layer of grid lines 21 is directly applied on the top surface of the base sheet 1, and a second layer of grid lines 22 is applied on the top side of the first layer of grid lines 21 and is used for contacting with the positive electrode of the solar cell sheet 6; for the sub-grid lines 2 on the bottom surface of the base sheet 1, a first layer of grid lines 21 is directly applied on the bottom surface of the base sheet 1, and a second layer of grid lines 22 is applied on the bottom side of the first layer of grid lines 21 and is used for contacting with the back electrode of the solar cell sheet 6.
In order to align the second layer of gate lines 22 with the first layer of gate lines 21 in the manufacturing process, the width of the dot structure of the first layer of gate lines 21 needs to be larger than the width of the second layer of gate lines 22. In this way, when a two-layer gate line is applied on the top surface, for example, the gate line 21 on the bottom side can be clearly seen during the application of the gate line 22 on the second layer, thereby ensuring that the extending direction of the gate line 22 on the second layer coincides with the extending direction of the gate line 21 on the first layer (i.e., the arrangement direction of the dot-like structures of the gate line 21 on the first layer).
Further, the width of the dot structure and the width setting of the second layer gate line 22 may have a more specific choice. For example, with reference to the dimensions indicated in fig. 2, the width X2 of the dot-shaped structures may satisfy: x2 is more than or equal to 5 mu m and less than or equal to 500 mu m; the width X1 of the second layer of grid lines 22 can satisfy 5 μm & lt X1 & lt 150 μm. On the other hand, for each two-layer gate line, the distance X3 between two adjacent dot structures may satisfy: x3 is not less than 0.3mm and not more than 4 mm. The above sizes are arranged on the basis of ensuring that the current can be efficiently transmitted, the contact area between the secondary grid line 2 and the base piece is prevented from being too large, and meanwhile, the material can be saved and the cost can be reduced.
Preferably, for any two adjacent two-layer gate lines, the dot structures of the two groups of first-layer gate lines 21 are staggered in a direction perpendicular to the first direction D1 and parallel to the base sheet, and in this embodiment, the direction perpendicular to the first direction D1 and parallel to the base sheet may be understood as the third direction D3. The arrangement can improve the efficiency of collecting the surface carriers of the battery, thereby further improving the battery conversion efficiency.
Preferably, the dot structures of the first layer of gate lines 21 may be dot structures of different shapes. In fig. 2 the individual dot-like structures are shown as dots or oval dot-like structures, but in other embodiments not shown, the dot-like structures may be ring-like dot-like structures, square dot-like structures or other polygonal dot-like structures, which include both regular and irregular polygonal structures.
Alternatively, the two-layer gate line may be only a sub-gate line on the top surface of the base sheet 1. For example, referring to fig. 4, the bottom of the substrate sheet 1 may be provided with an aluminum oxide layer 82 and a silicon nitride layer 83, and the sub-grid lines at the bottom of the substrate sheet 1 are aluminum electrodes 84 having a back electric field 81.
Turning back to fig. 3. In other embodiments, not shown, the second layer of grid lines 22 may also be provided intermittently in its extension direction, preferably also with the following dimensioning: each section is 10-4000 μm in length; and/or the distance between any two adjacent sections is 10-4000 μm. The arrangement avoids overlarge contact area between the secondary grid line 2 and the base sheet 1 on the basis of ensuring high-efficiency transmission of current, and meanwhile, the material can be saved and the cost can be reduced.
Preferably, the first layer of gate lines 21 and the second layer of gate lines 22 may also be made of different conductive materials, and the fire-through capability of the first layer of gate lines 21 is stronger than that of the second layer of gate lines 22. The first layer of gate lines 21 may be made of a conductive material with strong fire-through capability, such as silver paste, silver-aluminum paste, etc.; the second gate line 22 may be made of a conductive material with weak fire-through capability, such as silver paste, silver-aluminum paste, copper electrode, other metal alloy, conductive adhesive or transparent conductive film with weak fire-through capability. The first layer of grid lines 21 can burn through the passivation or antireflection film 12 (such as silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide) on the surface of the substrate 1 and directly contact with the silicon substrate, while the second layer of grid lines 22, which have a weaker burn-through capability, do not burn through the passivation or antireflection film 12 on the surface of the substrate 1 and only serve to connect the strong burn-through silver electrode and transmit carriers.
In this embodiment, the first layer of grid lines 21 is in direct contact with the silicon wafer 11 by burning through the passivation or antireflective film 12 of the base wafer 1 due to its relatively high burn-through capability. However, in other embodiments, not shown, the base sheet 1 may be prefabricated as: the passivation or antireflective film 12 is intermittently disposed over the silicon wafer 11 to provide space for the first layer of gridlines 21 so that the first layer of gridlines 21 are in direct contact with the silicon wafer 11 when the first layer of gridlines 21 is applied to the base sheet 1.
The two-layer gate line may also be applied to the main gate line 3, and in this embodiment, the main gate line 3 is not a two-layer gate line. In the present embodiment, the material, shape, fixing method and the like of the bus bar 3 may be selected in various ways. In terms of material, the main grid lines 3 can also be made of a material with strong burning-through capability; in terms of shape, the bus bars 3 on the top surface and/or the bottom surface of the base sheet 1 may also be continuously or intermittently arranged in the extending direction thereof (in the second direction D2 in the present embodiment), and when intermittently arranged, the bus bars 3 on the surfaces of any two adjacent solar cell sheets 6 facing each other can at least partially face each other in the direction perpendicular to the base sheet 1, thereby ensuring that the conductive connection between the two adjacent solar cell sheets 6 can be achieved, or the bus bars 3 of the base sheet 1 are each formed in a zigzag structure such that the bus bars 3 of the facing surfaces of the two solar cell sheets 6 contact each other in a rack-and-pinion manner; in terms of fixing, the bus bar 3 may be fixed to the base sheet 1 by soldering.
In addition, it can be understood by the present invention that the grid line printing method provided by the present invention can be combined with other methods such as electroplating, conductive adhesive, etc.
The present embodiment also provides a printing method for printing the gate line structure of the present embodiment on a top surface and/or a bottom surface of a base sheet, the base sheet including a silicon wafer and a film on a surface of the silicon wafer, the method including:
applying a first layer of grid lines on the substrate sheet so that the first layer of grid lines directly contacts the silicon wafer;
and applying a second layer of grid lines on the second layer of grid lines so that the second layer of grid lines contacts the film.
Preferably, the step of applying a first layer of grid lines comprises: a first conductive material is applied to the substrate sheet to form a first layer of gate lines,
the step of applying a second layer of grid lines comprises: a second conductive material is applied to the first layer of gate lines to form a second layer of gate lines,
the burn-through capability of the first conductive material is stronger than that of the second conductive material.
The embodiment also provides a manufacturing method of the solar cell, which comprises the following steps:
pretreating a large crystal silicon cell, wherein the pretreatment step comprises the following steps:
preparing a large substrate sheet;
respectively applying secondary grid lines and main grid lines on the top surface and the bottom surface of the large substrate sheet; and cutting the pretreated crystal silicon cell into small pieces so as to form a plurality of solar cell pieces.
And one of the main grid lines on the top surface, the auxiliary grid lines on the top surface, the main grid lines on the bottom surface and the auxiliary grid lines on the bottom surface of the substrate sheet is a two-layer grid line, and the step of applying the two-layer grid line is realized based on the printing method.
Of course, the step of pretreating the large piece of the crystalline silicon battery further comprises the following steps:
texturing on the surface of a total substrate sheet of a large crystal silicon cell;
growing and depositing an inner passivation layer on the front surface and the back surface of the total substrate sheet;
growing and depositing a middle passivation layer on the inner passivation layer;
and growing and depositing an outer passivation layer on the middle passivation layer.
More specifically, the inner passivation layer is deposited by a thermal oxidation method or a laughing gas oxidation method or an ozonization method or a nitric acid solution chemical method, and the inner passivation layer is arranged as a silicon dioxide film layer; and/or
The middle passivation layer is deposited by a PECVD or ALD layer or a PVD layer method by using a solid target material, and is set to be an aluminum oxide film layer or a film layer containing aluminum oxide; and/or
The outer passivation layer is deposited using PVD, CVD or ALD methods.
The above-described steps can be further specified and optimized. For example, in the texturing step, a single crystal silicon wafer is subjected to surface texturing to obtain a good textured structure, so that the specific surface area is increased, more photons (energy) can be received, meanwhile, the reflection of incident light is reduced, and the subsequent step can comprise a step of cleaning liquid remained in texturing so as to reduce the influence of acidic and alkaline substances on cell junction making. The method also comprises a step of manufacturing a PN junction after the texturing, which comprises the following steps: reacting phosphorus oxychloride with a silicon wafer to obtain phosphorus atoms; after a certain time, phosphorus atoms enter the surface layer of the silicon wafer and permeate and diffuse into the silicon wafer through gaps among the silicon atoms to form an interface of the N-type semiconductor and the P-type semiconductor. And finishing the diffusion and junction making process and realizing the conversion from light energy to electric energy. Because the diffusion junction forms a short circuit channel at the edge of the silicon wafer, photo-generated electrons collected by the front surface of the PN junction flow to the back surface of the PN junction along the region with phosphorus diffused at the edge to cause short circuit, and the PN junction at the edge is removed by etching through plasma, so that the short circuit caused by the edge can be avoided, and in addition, the SE process step can be added. Moreover, a layer of phosphorosilicate glass is formed on the surface of the silicon wafer in the diffusion junction making process, and the influence on the efficiency of the laminated cell is reduced through the phosphorosilicate glass removing process.
Further, laser grooving can be carried out on the silicon wafer after the passivation layer is formed; and sintering after printing the electrodes, reducing the light attenuation of the battery by passing through a light attenuation furnace or an electric injection furnace, and finally testing and grading the battery.
The step of breaking the silicon wafer into a plurality of solar cells is preferably accomplished using a laser cutter. The on-line laser cutting scribing process is added for the sintered large crystal silicon cell, the sintered large crystal silicon cell enters a scribing detection position to perform appearance inspection and visually locate the OK plate (poor appearance detection can automatically shunt to the NG position), and a multi-track scribing machine or a preset cache stack area can be freely arranged according to the on-line production beat so as to realize on-line continuous feeding operation. And setting relevant parameters of the laser according to the optimal effect of cutting and scribing so as to realize higher cutting speed, narrower cutting heat affected zone and cutting line width, better uniformity, preset cutting depth and the like. And after the automatic cutting is finished, the automatic sheet breaking mechanism of the online laser scribing machine is used for breaking the solar cell sheets at the cutting position to realize the natural separation of the solar cell sheets. It should be noted that the laser cutting surface is far away from the side of the PN junction, so that leakage current caused by damage of the PN junction is avoided, the front and back directions of the battery piece need to be confirmed before the material is cut and fed, and if the front and back directions are opposite, a separate 180-degree reversing device needs to be added.
And finally, after all the solar cells are connected in series to form the laminated assembly, the packaging of the laminated assembly is completed through the links of automatic typesetting and converging, glue film and back plate laying, intermediate inspection, laminating, trimming, framing, intermediate junction box curing, cleaning, testing and the like.
The solar cell, the laminated tile assembly and the manufacturing method can be widely applied to traditional aluminum back surface field crystal silicon cells (BSF), PERC cells, TOPCon cells, PERT cells, HJT cells, crystal silicon laminated cells and the like. The solar cell piece is provided with the two layers of secondary grid lines, wherein the secondary grid lines in contact with the base piece are discontinuously arranged in the extending direction of the secondary grid lines, so that the composition caused by the contact of the secondary grid lines and the base piece can be effectively reduced, and the open-circuit voltage and the conversion efficiency of the solar cell piece can be remarkably improved. In addition, the invention also provides the optimal arrangement of the shapes, the sizes and the like of the first layer of grid lines, the second layer of grid lines and other structures of the cell, so that the base sheet, the secondary grid lines, other structures of the cell and other parts can be well adapted, and the solar cell can have stable characteristics and excellent performance.
The foregoing description of various embodiments of the invention is provided for the purpose of illustration to one of ordinary skill in the relevant art. It is not intended that the invention be limited to a single disclosed embodiment. As mentioned above, many alternatives and modifications of the present invention will be apparent to those skilled in the art of the above teachings. Thus, while some alternative embodiments are specifically described, other embodiments will be apparent to, or relatively easily developed by, those of ordinary skill in the art. The present invention is intended to embrace all such alternatives, modifications and variances of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention as described above.
Reference numerals:
crystal silicon battery large sheet 7
Passivation or antireflective film 12
First layer of grid lines 21
A second layer of grid lines 22
Recess 221
Main grid welding point 4
Back electric field 81
First direction D1
Second direction D2
A third direction D3.
Claims (23)
1. A grid line structure for a crystalline silicon solar cell comprising a substrate sheet (1) comprising a silicon wafer (11) and films (12) disposed on top and bottom surfaces of the silicon wafer,
the grid line structure is located on the top surface and/or the bottom surface of the base piece, and the grid line structure is a two-layer grid line, and comprises:
the first layer of grid lines (21) are in direct contact with the silicon wafer, each first layer of grid line of the two layers of grid lines is of a plurality of point-shaped structures, and the point-shaped structures are arranged at intervals in the extending direction of the two layers of grid lines; and
a second layer of grid lines (22) disposed on the opposite side of the first layer of grid lines from the base sheet, with a portion of the surface of the second layer of grid lines facing the base sheet in contact with the first layer of grid lines and another portion in contact with the film,
wherein the width (X2) of the dot structure is larger than the width (X1) of the grid line of the second layer.
2. The gate line structure of claim 1, wherein said two-layer gate line extends along a first direction (D1), and for any two adjacent of said two-layer gate lines, each of said dot structures of two sets of said first layer gate lines is staggered in a direction perpendicular to said first direction and parallel to said substrate sheet.
3. The gate line structure of claim 1, wherein the dot structure is a dot structure, an elliptical dot structure, a circular dot structure, a square dot structure, or a polygonal dot structure.
4. The gate line structure of claim 1, wherein the second layer of gate lines is continuously disposed in an extending direction thereof.
5. The gate line structure of claim 1, wherein the first layer of gate lines has a burn-through capability that is greater than a burn-through capability of the second layer of gate lines.
6. The gate line structure of claim 1, wherein the dot structures have a width of 5 μm to 500 μm, and the second layer of gate lines have a width of 5 μm to 150 μm.
7. The gate line structure of claim 1, wherein the distance (X3) between two adjacent dot structures is 0.3mm to 4 mm.
8. The gate line structure of claim 1, wherein the first layer of gate lines is a gate line made of silver paste or silver-aluminum paste, and the second layer of gate lines is a gate line made of one of silver paste, metal alloy, copper electrode, conductive paste, and transparent conductive film.
9. The gate line structure of claim 1, wherein the film is intermittently disposed on the silicon wafer to leave spaces for the first layer of gate lines.
10. The grid line structure of claim 1, wherein the grid line structure is a primary grid line or a secondary grid line of the crystalline silicon solar cell.
11. A solar cell sheet comprising:
a substrate sheet comprising a silicon wafer and films disposed on top and bottom surfaces of the silicon wafer;
main grid lines and auxiliary grid lines, wherein the main grid lines and the auxiliary grid lines are arranged on the top surface and the bottom surface of the base piece, the auxiliary grid lines are arranged at intervals, the main grid lines cross each auxiliary grid line,
wherein at least one of a bus bar located on the top surface, a finger located on the top surface, a bus bar located on the bottom surface, and a finger located on the bottom surface is the gate line structure of any of claims 1-9.
12. The solar cell of claim 11, wherein only the secondary grid lines are of the grid line structure, and the burn-through capability of the primary grid lines is stronger than that of the first layer of grid lines of the grid line structure.
13. The solar cell sheet of claim 11, wherein the main grid lines are fixed on the substrate sheet by main grid welding points, wherein the projections of the main grid welding points on the substrate sheet are formed into rectangles, and the length dimension and the width dimension of the rectangles are 0.1mm-2.0 mm.
14. The solar cell sheet according to claim 13, wherein for one of the main grid lines, the distance between two adjacent main grid bonding pads for fixing the main grid line is 6mm to 40 mm.
15. The solar cell sheet according to claim 11, wherein the extending direction of the main grid line is perpendicular to the extending direction of the sub grid line.
16. The solar cell sheet according to claim 12, wherein the bus bars of the top surface and/or the bottom surface are intermittently arranged in the extending direction thereof, and the solar cell sheet is configured such that the bus bars on the surfaces of any two adjacent solar cell sheets facing each other are at least partially aligned with each other in a direction perpendicular to the base sheet.
17. The solar cell sheet according to claim 12, wherein the bus bars of the top and bottom surfaces are formed in a zigzag structure, and when two solar cell sheets are connected in a shingled manner, the facing bus bars of the two solar cell sheets contact each other in a rack-and-pinion manner.
18. The solar cell sheet according to claim 11, wherein the film is a passivation film or an antireflective film.
19. A stack of tiles, characterized in that the stack of tiles is arranged in a stack of solar cells according to any one of claims 11-18.
20. The shingle assembly of claim 19, wherein the minor grid lines of the solar cells extend in a first direction (D1), a plurality of the solar cells are arranged in a shingle manner in a sequence in a third direction (D3), and the major grid lines of the solar cells extend in a second direction (D2), the first direction being coincident with the third direction, and the second direction being perpendicular to the third direction.
21. A printing method for printing a gate line structure according to any one of claims 1 to 10 on a top and/or bottom surface of a substrate sheet, the substrate sheet comprising a silicon wafer and a film on a surface of the silicon wafer, the method comprising:
applying a first layer of grid lines on the substrate sheet so that the first layer of grid lines directly contacts the silicon wafer;
applying a second layer of gate lines on the second layer of gate lines such that the second layer of gate lines contacts the film.
22. The printing method according to claim 21,
the step of applying a first layer of grid lines comprises: a first conductive material is applied to the substrate sheet to form a first layer of gate lines,
the step of applying a second layer of grid lines comprises: applying a second conductive material on the first layer of gate lines to form a second layer of gate lines,
the burning-through capability of the first conductive material is stronger than that of the second conductive material.
23. A manufacturing method of a solar cell is characterized by comprising the following steps:
pretreating a large crystal silicon cell, wherein the pretreatment step comprises the following steps:
preparing a large substrate sheet;
applying secondary grid lines on the top and bottom surfaces of the large substrate sheet;
applying a main grid line on the top surface and the bottom surface of the large substrate sheet;
cutting the silicon crystal battery after the pretreatment into small pieces to form a plurality of solar battery pieces,
wherein at least one of the bus bar lines on the top surface, the sub-bus bar lines on the top surface, the bus bar lines on the bottom surface, and the sub-bus bar lines on the bottom surface is a two-layer bus bar, and the step of applying the two-layer bus bar is performed based on the printing method according to claim 21 or 22.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471336A (en) * | 2021-07-23 | 2021-10-01 | 常州时创能源股份有限公司 | Local back field passivation contact battery and preparation method thereof |
| CN113921630A (en) * | 2021-12-07 | 2022-01-11 | 中国华能集团清洁能源技术研究院有限公司 | Device structure and preparation method thereof |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471336A (en) * | 2021-07-23 | 2021-10-01 | 常州时创能源股份有限公司 | Local back field passivation contact battery and preparation method thereof |
| CN113921630A (en) * | 2021-12-07 | 2022-01-11 | 中国华能集团清洁能源技术研究院有限公司 | Device structure and preparation method thereof |
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