CN210640259U

CN210640259U - Grid line structure, solar cell piece and stack tile subassembly

Info

Publication number: CN210640259U
Application number: CN201922164383.7U
Authority: CN
Inventors: 常青; 姚骞; 张家峰; 马列; 王秀鹏
Original assignee: Tongwei Solar Meishan Co Ltd
Current assignee: Tongwei Solar Meishan Co Ltd
Priority date: 2019-12-05
Filing date: 2019-12-05
Publication date: 2020-05-29
Anticipated expiration: 2029-12-05

Abstract

The utility model relates to a grid line structure, solar wafer and stack tile subassembly. The grid line structure is located on the top surface and/or the bottom surface of the base piece and comprises a first layer of grid lines and a second layer of grid lines, the first layer of grid lines is in direct contact with a silicon wafer of the base piece, the second layer of grid lines is arranged on one side, opposite to the base piece, of the first layer of grid lines and is in film contact with the silicon wafer, and the first layer of grid lines of each two-layer type grid line is arranged discontinuously in the extending direction of the first layer of grid lines. According to the utility model discloses, in the grid line with the silicon chip one deck grid line of contact be interrupted the setting on its extending direction, can effectively reduce grid line and base member piece contact and the complex that leads to can show open circuit voltage and the conversion efficiency that promotes solar wafer.

Description

Grid line structure, solar cell piece and stack tile subassembly

Technical Field

The utility model relates to an energy field especially relates to a grid line structure, solar wafer and the subassembly of folding tiles of crystalline silicon solar cell.

Background

With the increasing consumption of conventional fossil energy such as global coal, oil, natural gas and the like, the ecological environment is continuously deteriorated, and particularly, the sustainable development of the human society is seriously threatened due to the increasingly severe global climate change caused by the emission of greenhouse gases. Various countries in the world make respective energy development strategies to deal with the limitation of conventional fossil energy resources and the environmental problems caused by development and utilization. Solar energy has become one of the most important renewable energy sources by virtue of the characteristics of reliability, safety, universality, long service life, environmental protection and resource sufficiency, and is expected to become a main pillar of global power supply in the future.

In a new energy revolution process, the photovoltaic industry in China has grown into a strategic emerging industry with international competitive advantages. Currently, mainstream crystalline silicon cell technologies in the photovoltaic industry on the market, such as passivated back and emitter (PERC, PERL, PERT), passivated contacts (TOPCon, POLO), heterojunction (HJT, HIT, HDT) solar cells, etc., have a mainstream production efficiency of over 22%. However, the development of the photovoltaic industry still faces many problems and challenges, and the conversion efficiency and reliability are the biggest technical obstacles restricting the development of the photovoltaic industry, while the cost control and the scale-up are economically restricted. The photovoltaic module is taken as a core component of photovoltaic power generation, and the development of high-efficiency modules by improving the conversion efficiency of the photovoltaic module is a necessary trend. Various high efficiency modules, such as shingles, half-sheets, multi-master grids, double-sided modules, etc., are currently emerging on the market. With the application places and application areas of the photovoltaic module becoming more and more extensive, the reliability requirement of the photovoltaic module becomes higher and higher, and particularly, the photovoltaic module with high efficiency and high reliability needs to be adopted in some severe or extreme weather frequent areas.

Under the background of vigorous popularization and use of green solar energy, the shingled assembly utilizes the electrical principle of low current and low loss (the power loss of the photovoltaic assembly is in direct proportion to the square of working current) so as to greatly reduce the power loss of the assembly. And secondly, the inter-cell distance region in the cell module is fully utilized to generate electricity, so that the energy density in unit area is high. In addition, the conventional photovoltaic metal welding strip for the assembly is replaced by the conductive adhesive with the elastomer characteristic at present, the photovoltaic metal welding strip shows higher series resistance in the whole battery, and the stroke of a current loop of the conductive adhesive is far smaller than that of a welding strip, so that the laminated assembly becomes a high-efficiency assembly, and meanwhile, the outdoor application reliability is more excellent than that of the conventional photovoltaic assembly, and the laminated assembly avoids stress damage of the metal welding strip to the interconnection position of the battery and other confluence areas. Especially, under the dynamic (load action of natural world such as wind, snow and the like) environment with alternating high and low temperatures, the failure probability of the conventional assembly which is interconnected and packaged by adopting the metal welding strips is far higher than that of the laminated assembly which is interconnected and cut by adopting the conductive adhesive of the elastomer and packaged by the crystalline silicon battery small pieces.

The mainstream technology of the current tile stack assembly is to use a conductive adhesive to interconnect the cut battery pieces, wherein the conductive adhesive mainly comprises a conductive phase and a bonding phase. The conductive phase mainly comprises precious metals, such as pure silver particles or particles of silver-coated copper, silver-coated nickel, silver-coated glass and the like, and is used for conducting electricity among solar cells, the particle shape and distribution of the precious metals are based on the requirement of optimal electricity conduction, and at present, more flake-shaped or sphere-like combined silver powder with the D50 being less than 10 mu m is adopted. The adhesive phase is mainly composed of a high molecular resin polymer having weather resistance, and acrylic resin, silicone resin, epoxy resin, polyurethane, and the like are usually selected in accordance with the adhesive strength and weather resistance. In order to enable the conductive adhesive to achieve low contact resistance, low volume resistivity and high adhesion and maintain long-term excellent weather resistance, a conductive adhesive manufacturer can generally complete the design of a conductive phase and an adhesive phase formula, so that the performance stability of the laminated tile assembly under an initial stage environment corrosion test and long-term outdoor practical application is ensured.

Electrodes are typically applied to the solar cell sheets. At present, more than 98% of battery technologies in the market adopt a screen printing silver grid line mode to form grid lines, silver paste is extruded to penetrate through meshes of a screen printing plate and penetrate to the surface of a silicon wafer to form the silver grid lines with certain height and width, and the silver grid lines are in good contact with the silicon wafer through high-temperature sintering. The screen printing of silver electrodes is a necessary process for the preparation of the current mainstream crystalline silicon cell, and has a great influence on the conversion efficiency of the solar cell. However, all the existing front silver electrode screen printing graphic designs adopt straight lines, the formed grid line is in a linear structure in full contact with the silicon wafer, and the current carriers caused by the contact of the grid line and the silicon wafer are compounded, so that the improvement of the conversion efficiency of the battery is limited.

It is therefore desirable to provide a grid line structure, a solar cell sheet and a shingle assembly that at least partially address the above problems.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a grid line structure, solar wafer, stack subassembly, the utility model discloses a solar wafer is provided with two-layer grid line, wherein is interrupted the setting on its extending direction with the one deck grid line of silicon chip contact, effectively reduces grid line and silicon chip contact and the complex that leads to can show open circuit voltage and the conversion efficiency who promotes solar wafer.

And, the utility model discloses still provide the preferred setting of the shape of other structures of first layer grid line, second floor grid line and battery piece, size etc for each part such as base member piece, vice grid line and main grid line can the adaptation betterly, thereby makes solar wafer can have stable characteristic and better performance.

According to an aspect of the present invention, there is provided a gate line structure for a crystalline silicon solar cell, the crystalline silicon solar cell including a substrate sheet including a silicon wafer and films disposed on top and bottom surfaces of the silicon wafer,

the grid line structure is located the top surface and/or the bottom surface of base member piece, and the grid line structure is two-layer formula grid line, and it includes:

the first layer of grid lines are in direct contact with the silicon wafer, and the first layer of grid lines of each two-layer type grid line are discontinuously arranged in the extending direction of the first layer of grid lines; and

and the second layer of grid lines is arranged on one side of the first layer of grid lines opposite to the base sheet, and one part of the surface of the second layer of grid lines facing the base sheet is in contact with the first layer of grid lines, and the other part of the surface of the second layer of grid lines is in contact with the film.

In one embodiment, the second layer of gate lines is continuously disposed in an extending direction thereof.

In one embodiment, the first layer of grid lines has a burn-through capability that is greater than a burn-through capability of the second layer of grid lines.

In one embodiment, each of the two-layer gate lines extends along a straight line, and for each of the first layer gate lines:

each section is 10-4000 μm in length; and/or

The distance between any two adjacent sections is 10-3000 μm; and/or a width of 5 μm to 200 μm.

In one embodiment, each of the two-layer gate lines extends along a straight line, and each of the second-layer gate lines has a width of 5 μm to 200 μm.

In one embodiment, each of the two-layer gate lines extends along a straight line, and the second layer of gate lines is intermittently arranged in the extending direction thereof, wherein,

each section is 10-4000 μm in length; and/or

The distance between any two adjacent sections is 10-3000 μm.

In one embodiment, the first layer of gate lines is gate lines made of silver paste or silver-aluminum paste, and the second layer of gate lines is gate lines made of one of silver paste, metal alloy, copper electrodes, conductive adhesive and transparent conductive film.

In one embodiment, the width of the first layer of gate lines is less than or equal to the width of the second layer of gate lines.

In one embodiment, each segment of the first layer of grid lines is a long strip or one of a circle, a ring and a polygon.

In one embodiment, the film is intermittently disposed on the silicon wafer to reserve a space for the first layer of gate lines.

In one embodiment, the grid line structure is a main grid line or a secondary grid line of the crystalline silicon solar cell.

According to the utility model discloses another aspect provides a solar wafer, solar wafer includes:

a substrate sheet comprising a silicon wafer and films disposed on top and bottom surfaces of the silicon wafer;

main grid lines and auxiliary grid lines, wherein the main grid lines and the auxiliary grid lines are arranged on the top surface and the bottom surface of the base piece, the auxiliary grid lines are arranged at intervals, the main grid lines cross each auxiliary grid line,

at least one of the main gate line on the top surface, the sub-gate line on the top surface, the main gate line on the bottom surface, and the sub-gate line on the bottom surface is the gate line structure according to any one of the above aspects.

In one embodiment, only the secondary grid lines are of the grid line structure, and the burn-through capability of the main grid lines is higher than that of the first layer of grid lines.

In one embodiment, the main grid line is fixed on the substrate sheet through a main grid welding point, wherein the projection of the main grid welding point on the substrate sheet is formed into a rectangle, and the length dimension and the width dimension of the rectangle are 0.1mm-2.0 mm.

In one embodiment, for one main grid line, the distance between two adjacent main grid welding points for fixing the main grid line is 6mm-40 mm.

In one embodiment, the extending direction of the main gate line is perpendicular to the extending direction of the sub gate line.

In one embodiment, the bus bars of the top surface and/or the bottom surface are intermittently arranged in the extending direction thereof, and the solar cell sheets are configured such that the bus bars on the surfaces of any two adjacent solar cell sheets facing each other are at least partially aligned with each other in a direction perpendicular to the base sheet.

In one embodiment, the bus bars of the top and bottom surfaces are formed in a zigzag structure, and the facing bus bars of two solar cells are in contact with each other in a rack-and-pinion manner when the two solar cells are connected in a shingled manner.

In one embodiment, the film is a passivation film or an antireflective film.

According to the utility model discloses still another aspect provides a stack assembly, stack assembly is formed by arranging the solar wafer according to any one of above-mentioned scheme with the stack mode.

In one embodiment, the minor grid lines of the solar cell pieces extend along a first direction, a plurality of the solar cell pieces are sequentially arranged along a third direction in a tiling mode, the major grid lines of the solar cell pieces extend along a second direction, the first direction is consistent with the third direction, and the second direction is perpendicular to the third direction.

According to the utility model discloses, solar wafer is provided with two-layer formula grid line, wherein is interrupted the setting on its extending direction with the one deck grid line of silicon chip contact, can effectively reduce grid line and silicon chip contact and the complex that leads to can show open circuit voltage and the conversion efficiency who promotes solar wafer. And, the utility model discloses still provide the preferred setting of the shape of other structures of first layer grid line, second floor grid line and battery piece, size etc for each part such as base member piece, vice grid line and main grid line can the adaptation betterly, thereby makes solar wafer can have stable characteristic and better performance.

Drawings

For a better understanding of the above and other objects, features, advantages and functions of the present invention, reference should be made to the preferred embodiments illustrated in the accompanying drawings. Like reference numerals in the drawings refer to like parts. It will be appreciated by persons skilled in the art that the drawings are intended to illustrate preferred embodiments of the invention without any limiting effect on the scope of the invention, and that the various components in the drawings are not to scale.

Fig. 1 is a schematic top view of a crystalline silicon battery wafer according to a preferred embodiment of the present invention;

fig. 2 is an enlarged view of a portion a of fig. 1, showing a first layer of gate lines underlying a second layer of gate lines, where the first layer of gate lines would actually be hidden by the second layer of gate lines;

FIG. 3 is a partial schematic view taken along line B-B of FIG. 2, wherein only the secondary grid lines are shown and the primary grid lines are omitted, wherein both the top and bottom surfaces of the substrate sheet are provided with grid line structures in accordance with the present invention;

fig. 4 is another alternative schematic view of fig. 3, wherein only the top surface of the substrate sheet is provided with a grid line structure according to the present invention;

fig. 5 is a partially enlarged view of a portion C in fig. 1;

figure 6 is a schematic view of a shingle assembly according to this embodiment.

Detailed Description

Referring now to the drawings, specific embodiments of the present invention will be described in detail. What has been described herein is merely a preferred embodiment in accordance with the present invention, and those skilled in the art will appreciate that other ways of implementing the present invention on the basis of the preferred embodiment will also fall within the scope of the present invention.

The fabrication of crystalline silicon cells requires multiple steps. For a single-crystal silicon cell piece, it can be obtained as follows. For example, a Czochralski method is used to grow a wafer rod as a raw material. And cutting and slicing by using a cutting machine, cutting and polishing the wafer rod to obtain a square rod, and cutting the square rod obtained after cutting and polishing to obtain the monocrystalline silicon piece. And then, carrying out steps such as surface texturing, cleaning, diffusion junction making, phosphorosilicate glass removal, antireflection film deposition and the like on the monocrystalline silicon wafer. And then screen printing a grid line of the solar cell, and finishing the manufacturing process of the large single crystal cell by a sintering process. According to the large single crystal battery, the front surfaces of the large single crystal batteries are provided with the front main grid lines, the back surfaces of the large single crystal batteries are provided with the back main grid lines, the auxiliary grid lines intersected with the main grid lines are arranged between the main grid lines, and the large single crystal batteries can be divided into small single crystal batteries to form the laminated assembly. The utility model discloses the modified is crystalline silicon solar cell's grid line structure.

The utility model provides a grid line structure, solar wafer, shingle assembly, fig. 1 to fig. 6 show the utility model discloses a preferred embodiment.

Fig. 1 shows a large crystalline silicon cell 7 according to a preferred embodiment of the present invention, the large crystalline silicon cell 7 can be split into a plurality of solar cells, and the plurality of solar cells can be arranged in a tile-stacking manner to form a tile-stacking assembly. It should be noted that the "first direction" to be mentioned later may be understood as an extending direction of one of the sub-grid lines 2 on the solar cell sheet; the "second direction" can be understood as the extending direction of the bus bars 3 of the solar cell sheet 6; the "third direction" can be understood as the arrangement direction of each solar cell 6 in the laminated tile assembly 5, which is approximately consistent with the width direction of each rectangular solar cell 6; as used herein, the term "one grid line" refers to the entirety of the grid line extending in a certain direction on one surface of a certain solar cell sheet 6, and "one segment of the grid line" refers to the smallest unit spaced apart from each other among the grid lines provided intermittently.

Referring to fig. 2 and 3, the solar cell sheet 6 divided by the large crystalline silicon cell sheet 7 includes a base sheet 1, and the base sheet 1 includes a silicon wafer and films disposed on top and bottom surfaces of the silicon wafer, which may preferably be passivation or antireflective films 12. The top surface and the bottom surface of the substrate sheet 1 of each solar cell sheet 6 are printed with a plurality of secondary grid lines 2 and a plurality of main grid lines 3, the secondary grid lines 2 are arranged at intervals, the main grid lines 3 cross over the secondary grid lines 2 so as to collect current from the secondary grid lines 2, generally, the main grid lines 3 on the top surface of the substrate sheet 1 can also be called as positive electrodes, and the main grid lines 3 on the bottom surface of the substrate sheet 1 can also be called as back electrodes. For any two adjacent solar cells 6, the bus bars 3 on the faces facing each other can contact each other to realize the conductive connection of the two solar cells 6. It should be noted that, unless otherwise specified, the term "contacting" as used herein includes both direct contact and indirect contact via a conductive adhesive or conductive adhesive.

In this embodiment, the extending direction of the main gate line 3 (i.e., the second direction D2) and the extending direction of the sub gate line 2 (i.e., the first direction D1) are both substantially straight lines, and the first direction D1 is perpendicular to the second direction D2. Also, the first direction D1 is also coincident with the third direction D3, that is, the second direction D2 is also perpendicular to the third direction D3. In other embodiments, which are not shown, the extending directions of the main and sub gate lines may have other options, for example, the main and sub gate lines may extend along a curved line, or the angle between the main and sub gate lines may be acute, or the extending directions of the sub gate lines may be offset from the third direction D3.

The utility model provides a novel grid line structure of crystal silicon battery, two-layer type grid line promptly. Specifically, referring to fig. 2 and 3, the solar cell sheet 6 includes such two-layer gate lines, that is, at least one of the main gate lines 3 on the top surface, the sub-gate lines 2 on the bottom surface, and the main gate lines 3 on the bottom surface of the base sheet 1 may be such two-layer gate lines. In the present embodiment, only the finger lines 2 on the top and bottom surfaces of the base sheet 1 shown in fig. 3 are two-layer finger lines.

With continued reference to fig. 3, it can be seen that the two-layer grid lines of the solar cell 6 include a first layer of grid lines 21 and a second layer of grid lines 22, the first layer of grid lines 21 is in direct contact with the silicon wafer, and the second layer of grid lines 22 is disposed on the side of the first layer of grid lines 21 opposite to the base sheet 1 and above the passivation or antireflective film 12 for contacting the main grid lines 3. The first layer of gate lines 21 of each two-layer gate line are intermittently arranged in the extending direction (in the embodiment, the first direction D1), and the second layer of gate lines 22 are continuously arranged in the extending direction (in the embodiment, the first direction D1), so that the sub-gate lines 2 are not in complete contact with the silicon wafer 11 but in intermittent contact with the silicon wafer 11, and therefore the contact area between the sub-gate lines 2 and the silicon wafer 11 is greatly reduced, and the purpose of improving the open-circuit voltage and the conversion efficiency of the solar cell 6 is achieved.

Specifically, for the secondary grid lines 2 on the top surface of the base sheet 1 of the solar cell sheet 6, a first layer of grid lines 21 is directly applied on the top surface of the base sheet 1, and a second layer of grid lines 22 is applied on the top side of the first layer of grid lines 21 and is used for contacting with the positive electrode of the solar cell sheet 6; for the sub-grid lines 2 on the bottom surface of the base sheet 1, a first layer of grid lines 21 is directly applied on the bottom surface of the base sheet 1, and a second layer of grid lines 22 is applied on the bottom side of the first layer of grid lines 21 and is used for contacting with the back electrode of the solar cell sheet 6.

Alternatively, the two-layer gate line may be only a sub-gate line on the top surface of the base sheet 1. For example, referring to fig. 4, the bottom of the substrate sheet 1 may be provided with an aluminum oxide layer 82 and a silicon nitride layer 83, and the sub-grid lines at the bottom of the substrate sheet 1 are aluminum electrodes 84 having a back electric field 81.

Turning back to fig. 3. In this embodiment, the sizes of the first layer gate line 21 and the second layer gate line 22 may further have a preferable setting. For example, for each first layer gate line 21, the length X1 of each segment preferably satisfies: x1 is more than or equal to 10 mu m and less than or equal to 4000 mu m; the distance X2 between any adjacent two segments preferably satisfies 10 μm. ltoreq. X2. ltoreq.4000 μm; the width (i.e. the dimension along the second direction D2 shown in fig. 5) is preferably 5 μm-200 μm. The width of each second layer gate line 22 is also preferably 5 μm to 200 μm. In other embodiments, not shown, the second layer of grid lines 22 may also be provided intermittently in its extension direction, preferably also with the following dimensioning: each section is 10-4000 μm in length; and/or the distance between any two adjacent sections is 10-3000 μm. The arrangement avoids overlarge contact area between the secondary grid line 2 and the base sheet 1 on the basis of ensuring high-efficiency transmission of current, and meanwhile, the material can be saved and the cost can be reduced.

Preferably, the first layer of gate lines 21 and the second layer of gate lines 22 may also be made of different conductive materials, and the fire-through capability of the first layer of gate lines 21 is stronger than that of the second layer of gate lines 22. The first layer of gate lines 21 may be made of a conductive material with strong fire-through capability, such as silver paste, silver-aluminum paste, etc.; the second gate line 22 may be made of a conductive material with weak fire-through capability, such as silver paste, silver-aluminum paste, copper electrode, other metal alloy, conductive adhesive or transparent conductive film with weak fire-through capability. The first layer of grid lines 21 can burn through the passivation or antireflection film 12 (such as silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide) on the surface of the substrate 1 and directly contact with the silicon substrate, while the second layer of grid lines 22, which have a weaker burn-through capability, do not burn through the passivation or antireflection film 12 on the surface of the substrate 1 and only serve to connect the strong burn-through silver electrode and transmit carriers.

In this embodiment, the first layer of grid lines 21 is in direct contact with the silicon wafer 11 by burning through the passivation or antireflective film 12 of the base wafer 1 due to its relatively high burn-through capability. However, in other embodiments, not shown, the base sheet 1 may be prefabricated as: the passivation or antireflective film 12 is intermittently disposed over the silicon wafer 11 to provide space for the first layer of gridlines 21 so that the first layer of gridlines 21 are in direct contact with the silicon wafer 11 when the first layer of gridlines 21 is applied to the base sheet 1.

The two-layer gate line may also be applied to the main gate line 3, and in this embodiment, the main gate line 3 is not a two-layer gate line. In the present embodiment, the material, shape, fixing method and the like of the bus bar 3 may be selected in various ways. In terms of material, the main grid lines 3 can also be made of a material with strong burning-through capability; in terms of shape, the bus bars 3 on the top surface and/or the bottom surface of the base sheet 1 may also be continuously or intermittently arranged in the extending direction thereof (in the second direction D2 in the present embodiment), and when intermittently arranged, the bus bars 3 on the surfaces of any two adjacent solar cell sheets 6 facing each other can at least partially face each other in the direction perpendicular to the base sheet 1, thereby ensuring that the conductive connection between the two adjacent solar cell sheets 6 can be achieved, or the bus bars 3 of the base sheet 1 are each formed in a zigzag structure such that the bus bars 3 of the facing surfaces of the two solar cell sheets 6 contact each other in a rack-and-pinion manner; in terms of fixing manner, the main gate lines 3 may be fixed to the base sheet 1 by soldering, and referring to fig. 5, the main gate pads 4 formed by soldering may preferably be formed in a rectangular shape, and the length (i.e., the dimension in the first direction D1) and the width (i.e., the dimension in the second direction D2) thereof may be approximately 0.1mm to 2.0mm, and the distance between two adjacent main gate pads 4 for fixing one main gate line 3 may be approximately 6mm to 40 mm.

In addition, through the utility model discloses can also understand, the utility model provides a printing mode of grid line can combine together with other modes such as electroplating, conducting resin.

The present embodiment also provides a printing method for printing the gate line structure of the present embodiment on a top surface and/or a bottom surface of a base sheet, the base sheet including a silicon wafer and a film on a surface of the silicon wafer, the method including:

applying a first layer of grid lines on the substrate sheet so that the first layer of grid lines directly contacts the silicon wafer;

and applying a second layer of grid lines on the second layer of grid lines so that the second layer of grid lines contacts the film.

Preferably, the step of applying a first layer of grid lines comprises: a first conductive material is applied to the substrate sheet to form a first layer of gate lines,

the step of applying a second layer of grid lines comprises: a second conductive material is applied to the first layer of gate lines to form a second layer of gate lines,

the burn-through capability of the first conductive material is stronger than that of the second conductive material.

The embodiment also provides a manufacturing method of the solar cell, which comprises the following steps:

pretreating a large crystal silicon cell, wherein the pretreatment step comprises the following steps:

preparing a large substrate sheet;

respectively applying secondary grid lines and main grid lines on the top surface and the bottom surface of the large substrate sheet;

cutting the pretreated crystal silicon battery into small pieces so as to form a plurality of solar battery pieces,

and one of the main grid lines on the top surface, the auxiliary grid lines on the top surface, the main grid lines on the bottom surface and the auxiliary grid lines on the bottom surface of the substrate sheet is a two-layer grid line, and the step of applying the two-layer grid line is realized based on the printing method.

Of course, the step of pretreating the large piece of the crystalline silicon battery further comprises the following steps:

texturing on the surface of a total substrate sheet of a large crystal silicon cell;

growing and depositing an inner passivation layer on the front surface and the back surface of the total substrate sheet;

growing and depositing a middle passivation layer on the inner passivation layer;

and growing and depositing an outer passivation layer on the middle passivation layer.

More specifically, the inner passivation layer is deposited by a thermal oxidation method or a laughing gas oxidation method or an ozonization method or a nitric acid solution chemical method, and the inner passivation layer is arranged as a silicon dioxide film layer; and/or

The middle passivation layer is deposited by a PECVD or ALD layer or a PVD layer method by using a solid target material, and is set to be an aluminum oxide film layer or a film layer containing aluminum oxide; and/or

The outer passivation layer is deposited using PVD, CVD or ALD methods.

The above-described steps can be further specified and optimized. For example, in the texturing step, a single crystal silicon wafer is subjected to surface texturing to obtain a good textured structure, so that the specific surface area is increased, more photons (energy) can be received, meanwhile, the reflection of incident light is reduced, and the subsequent step can comprise a step of cleaning liquid remained in texturing so as to reduce the influence of acidic and alkaline substances on cell junction making. The method also comprises a step of manufacturing a PN junction after the texturing, which comprises the following steps: reacting phosphorus oxychloride with a silicon wafer to obtain phosphorus atoms; after a certain time, phosphorus atoms enter the surface layer of the silicon wafer and permeate and diffuse into the silicon wafer through gaps among the silicon atoms to form an interface of the N-type semiconductor and the P-type semiconductor. And finishing the diffusion and junction making process and realizing the conversion from light energy to electric energy. Because the diffusion junction forms a short circuit channel at the edge of the silicon wafer, photo-generated electrons collected by the front surface of the PN junction flow to the back surface of the PN junction along the region with phosphorus diffused at the edge to cause short circuit, and the PN junction at the edge is removed by etching through plasma, so that the short circuit caused by the edge can be avoided, and in addition, the SE process step can be added. Moreover, a layer of phosphorosilicate glass is formed on the surface of the silicon wafer in the diffusion junction making process, and the influence on the efficiency of the laminated cell is reduced through the phosphorosilicate glass removing process.

Further, laser grooving can be carried out on the silicon wafer after the passivation layer is formed; and sintering after printing the electrodes, reducing the light attenuation of the battery by passing through a light attenuation furnace or an electric injection furnace, and finally testing and grading the battery.

The step of breaking the silicon wafer into a plurality of solar cells is preferably accomplished using a laser cutter. The on-line laser cutting scribing process is added for the sintered large crystal silicon cell, the sintered large crystal silicon cell enters a scribing detection position to perform appearance inspection and visually locate the OK plate (poor appearance detection can automatically shunt to the NG position), and a multi-track scribing machine or a preset cache stack area can be freely arranged according to the on-line production beat so as to realize on-line continuous feeding operation. And setting relevant parameters of the laser according to the optimal effect of cutting and scribing so as to realize higher cutting speed, narrower cutting heat affected zone and cutting line width, better uniformity, preset cutting depth and the like. And after the automatic cutting is finished, the automatic sheet breaking mechanism of the online laser scribing machine is used for breaking the solar cell sheets at the cutting position to realize the natural separation of the solar cell sheets. It should be noted that the laser cutting surface is far away from the side of the PN junction, so that leakage current caused by damage of the PN junction is avoided, the front and back directions of the battery piece need to be confirmed before the material is cut and fed, and if the front and back directions are opposite, a separate 180-degree reversing device needs to be added.

And finally, after all the solar cells are connected in series to form the laminated assembly, the packaging of the laminated assembly is completed through the links of automatic typesetting and converging, glue film and back plate laying, intermediate inspection, laminating, trimming, framing, intermediate junction box curing, cleaning, testing and the like.

The utility model discloses a solar wafer, fold tile subassembly and manufacturing approach, but wide application in traditional aluminium back of body field crystal silicon Battery (BSF), PERC battery, TOPCon battery, PERT battery, HJT battery to and crystal silicon tandem cell etc.. The utility model discloses a solar wafer has two-layer vice grid line, wherein is interrupted the setting in its extending direction with the vice grid line of base member piece contact, can effectively reduce vice grid line and base member piece contact and the complex that leads to can show open a way voltage and the conversion efficiency that promotes solar wafer. And, the utility model discloses still provide the preferred setting of the shape of other structures of first layer grid line, second floor grid line and battery piece, size etc for each part such as base member piece, vice grid line and main grid line can the adaptation betterly, thereby makes solar wafer can have stable characteristic and better performance.

The foregoing description of various embodiments of the invention is provided to one of ordinary skill in the relevant art for the purpose of illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. As noted above, various alternatives and modifications of the present invention will be apparent to those skilled in the art of the above teachings. Thus, while some alternative embodiments are specifically described, other embodiments will be apparent to, or relatively easily developed by, those of ordinary skill in the art. The present invention is intended to embrace all such alternatives, modifications and variances of the present invention described herein, as well as other embodiments that fall within the spirit and scope of the present invention as described above.

Reference numerals:

crystal silicon battery large sheet 7

Shingle assembly 5

Solar cell sheet 6

Base sheet 1

Silicon wafer 11

Passivation or antireflective film 12

Secondary grid line 2

First layer of grid lines 21

A second layer of grid lines 22

Recess 221

Main grid line 3

Main grid welding point 4

Back electric field 81

Alumina layer 82

Silicon nitride layer 83

Aluminum electrode 84

First direction D1

Second direction D2

Third direction D3

Claims

1. A grid line structure for a crystalline silicon solar cell comprising a substrate sheet (1) comprising a silicon wafer (11) and films (12) disposed on top and bottom surfaces of the silicon wafer,

the grid line structure is located on the top surface and/or the bottom surface of the base piece, and the grid line structure is a two-layer grid line, and comprises:

the first layer of grid lines (21) are in direct contact with the silicon wafer, and the first layer of grid lines of each two-layer type grid line are discontinuously arranged in the extending direction of the first layer of grid lines; and

and a second layer of grid lines (22) which are arranged on one side of the first layer of grid lines opposite to the base sheet, wherein one part of the surface of the second layer of grid lines facing the base sheet is in contact with the first layer of grid lines, and the other part of the surface of the second layer of grid lines is in contact with the film.

2. The gate line structure of claim 1, wherein the second layer of gate lines is continuously disposed in an extending direction thereof.

3. The gate line structure of claim 1, wherein the first layer of gate lines has a burn-through capability that is greater than a burn-through capability of the second layer of gate lines.

4. The gate line structure of claim 1, wherein each of the two-layer gate lines extends along a straight line, and for each of the first layer gate lines:

each section is 10-4000 μm in length; and/or

The distance between any two adjacent sections is 10-3000 μm; and/or

The width is 5 μm-200 μm.

5. The gate line structure of claim 1, wherein each of the two-layer gate lines extends along a straight line, and each of the second layer gate lines has a width of 5 μm to 200 μm.

6. The gate line structure of claim 1, wherein each of said two-layer gate lines extends along a straight line, and said second layer of gate lines is intermittently arranged in a direction in which it extends, wherein,

each section is 10-4000 μm in length; and/or

The distance between any two adjacent sections is 10-3000 μm.

7. The gate line structure of claim 1, wherein the first layer of gate lines is a gate line made of silver paste or silver-aluminum paste, and the second layer of gate lines is a gate line made of one of silver paste, metal alloy, copper electrode, conductive paste, and transparent conductive film.

8. The gate line structure of claim 1, wherein the width of the first layer of gate lines is less than or equal to the width of the second layer of gate lines.

9. The gate line structure of claim 1, wherein each segment of the first gate line is one of a strip, a circle, and a polygon.

10. The gate line structure of claim 1, wherein the film is intermittently disposed on the silicon wafer to leave spaces for the first layer of gate lines.

11. The grid line structure of claim 1, wherein the grid line structure is a primary grid line or a secondary grid line of the crystalline silicon solar cell.

12. A solar cell sheet comprising:

wherein at least one of a bus bar located on the top surface, a finger located on the top surface, a bus bar located on the bottom surface, and a finger located on the bottom surface is the gate line structure of any of claims 1-11.

13. The solar cell of claim 12, wherein only the secondary grid lines are of the grid line structure, and the main grid lines have a burn-through capability higher than that of the first layer of grid lines.

14. The solar cell sheet of claim 13, wherein the main grid lines are fixed on the substrate sheet by main grid welding points, wherein the projections of the main grid welding points on the substrate sheet are formed into rectangles, and the length dimension and the width dimension of the rectangles are 0.1mm-2.0 mm.

15. The solar cell sheet according to claim 14, wherein for one of the main grid lines, the distance between two adjacent main grid bonding pads for fixing the main grid line is 6mm to 40 mm.

16. The solar cell sheet according to claim 12, wherein the extending direction of the main grid line is perpendicular to the extending direction of the sub grid line.

17. The solar cell sheet according to claim 13, wherein the bus bars of the top surface and/or the bottom surface are intermittently arranged in the extending direction thereof, and the solar cell sheet is configured such that the bus bars on the surfaces of any two adjacent solar cell sheets facing each other are at least partially aligned with each other in a direction perpendicular to the base sheet.

18. The solar cell sheet according to claim 13, wherein the bus bars of the top and bottom surfaces are formed in a zigzag structure, and when two solar cell sheets are connected in a shingled manner, the facing bus bars of the two solar cell sheets contact each other in a rack-and-pinion manner.

19. The solar cell sheet according to claim 12, wherein the film is a passivation film or an antireflective film.

20. A shingled assembly comprising solar cells according to any of claims 12-19 arranged in a shingled manner.

21. The shingle assembly of claim 20, wherein the minor grid lines of the solar cells extend in a first direction (D1), a plurality of the solar cells are arranged in a shingle manner in a sequence in a third direction (D3), and the major grid lines of the solar cells extend in a second direction (D2), the first direction being coincident with the third direction, and the second direction being perpendicular to the third direction.