CN211827126U - Feiteng mainboard with many PCIE interfaces - Google Patents

Abstract

The utility model relates to a computer technology field, concretely relates to Feiteng mainboard with many PCIE interfaces, including Feiteng CPU, PCIe Switch chip, graphics image processor and DDR, through first PCIe 8 interface connection between the ascending interface of PCIe Switch chip and the Feiteng CPU, down the interface includes six PCIe1 interfaces, six PCIe1 interfaces insert two PCIe commentaries on classics USB controllers, two PCIe SATA commentaries on classics controllers, a PCIe commentaries on classics UART controller and a network controller altogether. The Feiteng CPU is connected with the graphic image processor through a second PCIe (peripheral component interface express) multiplied by 8 interface, the graphic image processor is connected with two DVI multiplied by 1 slots, and the Feiteng CPU is connected with a PCIE2 multiplied by 8 slot through a third PCIe multiplied by 8 interface. Peripheral interface expansion is performed by adopting a PCIe Switch chip, and the peripheral interface expansion has enough PCIE interfaces and effectively controls the cost.

Description

Feiteng mainboard with many PCIE interfaces

Technical Field

The utility model relates to a computer technology field, concretely relates to mainboard of soaring with many PCIE interfaces.

Background

The existing computer motherboard is usually designed by adopting an X86 architecture, PCIE interfaces of the motherboard with the X86 architecture are usually led out from north and south bridges, PCIE interface resources of bridge chips are limited, and the expandability is poor. The chipset with more PCIE interfaces is expensive, for example, the H67 chip with 8 PCIE1X signals has only 2 more PCIE1X than the H61 chip, but the price is twice of the latter, and the cost is high. In addition, the existing main board usually adopts a combination of 12V, 5V and 3.3V power supplies, and has different power-on sequence requirements for different bridge chips, so that the universality is not strong and the stability is poor. The CPU usually adopts a fan for heat dissipation, and the fan has a large volume, needs to occupy more space of the chassis, and is not favorable for the miniaturization development of the equipment.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a mainboard of soaring with many PCIE interfaces to prior art's defect, it has abundant PCIE interface, has higher commonality, and need not external radiator fan.

The technical scheme of the utility model is that: the Feiteng mainboard comprises a Feiteng CPU, a PCIe Switch chip, a graphic image processor and a DDR, the upstream interface of the PCIe Switch chip is connected with the Feiteng CPU through a first PCIe x8 interface, the PCIe Switch chip downlink interface comprises at least six PCIe x 1 interfaces, the six PCIe x 1 interfaces are accessed into two PCIe-to-USB controllers, two PCIe-to-SATA controllers, a PCIe-to-UART controller and a network controller, the two PCIe-to-USB controllers are respectively connected with a USB x 2 slot and a USB x4 slot, the two PCIe-to-SATA controllers are respectively connected with a SATA x4 slot and a mSATA electronic disk, the PCIe-to-UART controller is connected with a UART x4 slot, the network controller is connected with a gigabit Ethernet x4 slot, the Feiteng CPU is connected with a graphic image processor through a second PCIe (peripheral component interface express) x8 interface, the graphic image processor is connected with two DVI x 1 slots, the Feiteng CPU is connected with the PCIE2 multiplied by 8 slot through a third PCIe multiplied by 8 interface.

Preferably, the main board is powered by a +12VDC power supply, the +12VDC power supply is connected with the power input ends of the Feiteng CPU, the network controller and the DDR through a switch power supply, and the +12VDC power supply is connected with the power input ends of the PLL chip and the IO chip through a low dropout regulator LDO.

Preferably, the DDR is formed by combining DDR3 memory particles attached to the DDR interface.

Preferably, the main board is arranged in a totally enclosed heat dissipation shell, the inner wall of the heat dissipation shell and the corresponding position of each chip on the main board are provided with protruding parts, and heat conduction layers are filled between the protruding parts and the chips of the main board.

Preferably, the heat conducting layer is heat-dissipating silicone grease or heat-conducting rubber.

Preferably, the top of the heat dissipation shell is provided with heat dissipation fins.

Preferably, the heat conducting layer is made of heat-dissipating silicone grease and heat-conducting rubber.

Preferably, the Feiteng CPU is an FT1500A-4 processor.

Preferably, the PCIe Switch chip is a PCIe Switch PEX8648 chip.

The utility model has the advantages that: peripheral interface expansion is performed by adopting a PCIe Switch chip, and the peripheral interface expansion has enough PCIE interfaces and effectively controls the cost. The power supply of each chip of the main board is realized by adopting a +12VDC power supply to match with a switching power supply and a low dropout regulator (LDO), the requirement of a computer board on a power-on time sequence is reduced, and the stability of the power-on time sequence is ensured. The traditional fan heat dissipation mode is replaced by the contact type heat dissipation mode of the heat dissipation cover plate and the case, so that the heat of each chip in the mainboard can be quickly conducted, and the internal space of the case is saved. Through the design of the lug boss and the filling heat conduction material, a heat conduction flow exchange channel is realized between a heat source and the radiator, and the heat radiation efficiency is improved.

Drawings

FIG. 1 is a schematic view of the present invention;

fig. 2 is a schematic view of the present invention.

Detailed Description

The invention will be further described in detail with reference to the drawings and the following detailed description, which are provided for the purpose of clearly understanding the invention and are not intended to limit the invention.

As shown in fig. 1, the flyover motherboard includes a flyover CPU, a PCIe Switch chip, a graphics image processor and a DDR, an upstream interface of the PCIe Switch chip is connected to the flyover CPU via a first PCIe × 8 interface, a downstream interface of the PCIe Switch chip includes at least six PCIe × 1 interfaces, the six PCIe × 1 interfaces are commonly connected to two PCIe-to-USB controllers, two PCIe-to-SATA controllers, a PCIe-to-UART controller and a network controller, the two PCIe-to-USB controllers are respectively connected to USB × 2 and USB × 4 slots, the two PCIe-to-USB controllers are respectively connected to SATA × 4 slots and SATA mseds, the PCIe-to-UART controller is connected to a UART × 4 slot, the network controller is connected to a gigabit ethernet × 4 slot, the flyover CPU is connected to the graphics image processor via a second PCIe × 8 interface, and the graphics image processor is connected to the two DVI × 1 slots, the Feiteng CPU is connected with the PCIE2 multiplied by 8 slot through a third PCIe multiplied by 8 interface.

Preferably, the Feiteng mainboard supplies power through a +12VDC power supply, the +12VDC power supply is connected with the Feiteng CPU, the network controller and the DDR power supply input end through a switching power supply, and the conversion efficiency can be greatly improved by means of the switching power supply and can reach over 90%, so that the power consumption of the whole board is reduced. And the +12VDC power supply is connected with the power supply input ends of the PLL chip and the IO chip through the low dropout regulator LDO. Other power supply requirements are obtained by conversion in the board, so that conversion efficiency is improved, and stable power sequence on the whole board is ensured.

Preferably, the DDR is formed by combining DDR3 memory particles attached to the DDR interface.

It is comparatively preferred, the mainboard setting is in a totally enclosed heat dissipation casing 1, each chip corresponds position department on heat dissipation casing 1 inner wall and the mainboard 2 and is equipped with the protruding portion 3, it has heat-conducting layer 4 to fill between protruding portion 3 and the mainboard chip, and heat-conducting layer 4 is heat dissipation silicone grease or heat conduction rubber, and heat dissipation casing 1 top is equipped with radiating fin 5.

In this embodiment, the FT CPU adopts an FT1500A-4 processor, and the PCIe Switch chip is a PCIe Switch PEX8648 chip. A DDR3 memory controller provided by a Feiteng CPU supports two bit-wide particle types of x8 and x4, and is realized by adopting a domestic DDR particle of HXI15H4G800AF manufactured by the Ministry of Violet.

Details not described in this specification are within the skill of the art that are well known to those skilled in the art.

Claims (8)

1. The utility model provides a Feiteng mainboard with many PCIE interfaces which characterized in that: the Feiteng mainboard comprises a Feiteng CPU, a PCIeSwitch chip, a graphic image processor and a DDR, the upstream interface of the PCIe Switch chip is connected with the Feiteng CPU through a first PCIe x8 interface, the PCIe Switch chip downlink interface comprises at least six PCIe x 1 interfaces, the six PCIe x 1 interfaces are accessed into two PCIe-to-USB controllers, two PCIe-to-SATA controllers, a PCIe-to-UART controller and a network controller, the two PCIe-to-USB controllers are respectively connected with a USB x 2 slot and a USB x4 slot, the two PCIe-to-SATA controllers are respectively connected with a SATA x4 slot and a mSATA electronic disk, the PCIe-to-UART controller is connected with a UART x4 slot, the network controller is connected with a gigabit Ethernet x4 slot, the Feiteng CPU is connected with a graphic image processor through a second PCIe (peripheral component interface express) x8 interface, the graphic image processor is connected with two DVI x 1 slots, the Feiteng CPU is connected with the PCIE2 multiplied by 8 slot through a third PCIe multiplied by 8 interface.

2. The Feiteng motherboard with multiple PCIE interfaces of claim 1, wherein: the power supply system is characterized in that the Feiteng mainboard is powered by a +12VDC power supply, the +12VDC power supply is connected with the power input ends of the Feiteng CPU, the network controller and the DDR through a switch power supply, and the +12VDC power supply is connected with the power input ends of the PLL chip and the IO chip through a low dropout regulator (LDO).

3. The Feiteng motherboard with multiple PCIE interfaces of claim 1, wherein: the DDR is formed by combining DDR3 memory particles attached to a DDR interface.

4. The Feiteng motherboard with multiple PCIE interfaces of claim 1, wherein: the mainboard sets up in a totally enclosed heat dissipation casing (1), each chip corresponds position department on heat dissipation casing (1) inner wall and mainboard (2) and is equipped with protruding portion (3), it has heat-conducting layer (4) to fill between protruding portion (3) and the mainboard chip.

5. The Feiteng motherboard with multiple PCIE interfaces of claim 4, wherein: the heat conducting layer (4) is made of heat-dissipating silicone grease or heat-conducting rubber.

6. The Feiteng motherboard with multiple PCIE interfaces of claim 4, wherein: and the top of the heat dissipation shell (1) is provided with heat dissipation fins (5).

7. The Feiteng motherboard with multiple PCIE interfaces of claim 1, wherein: the Feiteng CPU is an FT1500A-4 processor.

8. The Feiteng motherboard with multiple PCIE interfaces of claim 1, wherein: the PCIe Switch chip is a PCIe Switch PEX8648 chip.

Images