CN211789074U - Light-emitting diode chip - Google Patents
Light-emitting diode chip Download PDFInfo
- Publication number
- CN211789074U CN211789074U CN201922493632.7U CN201922493632U CN211789074U CN 211789074 U CN211789074 U CN 211789074U CN 201922493632 U CN201922493632 U CN 201922493632U CN 211789074 U CN211789074 U CN 211789074U
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- emitting diode
- diode chip
- ohmic contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
- Led Devices (AREA)
Abstract
The application discloses light emitting diode chip. The light emitting diode chip includes: the transfer substrate comprises a transfer substrate, and a bonding layer, a dielectric film layer, a P-type ohmic contact layer, a P-type current expansion layer, a P-type limiting layer, an active layer, an N-type limiting layer, an N-type coarsening layer and an N-type ohmic contact layer which are sequentially stacked on the upper part of the transfer substrate; the upper electrode is positioned on the N-type ohmic contact layer; a lower electrode positioned under the transfer substrate; the radius of the upper electrode is larger than 30 microns, so that the pressure intensity during welding can be reduced, and the possibility of electrode digging is reduced. The light-emitting diode can effectively avoid the problems of electrode digging and electrode failure in the wire welding process, and improves the reliability and brightness of products.
Description
Technical Field
The utility model relates to a semiconductor technology field, more specifically relates to a light emitting diode chip.
Background
The Light Emitting Diode (LED) emits Light in the form of Light by utilizing the energy difference between the N-type semiconductor and the P-type semiconductor caused by electrons moving therebetween. With its good color rendering capability, it has been widely used in public fields such as display indication, traffic sign, urban lightening, etc. Meanwhile, as an excellent semiconductor lighting source, the LED has the advantages of low energy consumption, long service life, no maintenance, environmental protection and the like. The LED backlight source can be widely applied to the fields of various indications, displays, decorations, backlight sources, general illumination and the like.
The epitaxial wafer of the quaternary system aluminum gallium indium phosphide light-emitting diode (AlGaInP LED) chip of the traditional transfer substrate is a combination of a plurality of layers, and stress can be generated due to lattice difference between the layers, so that the problem that the light-emitting diode chip is dug and broken is solved, and the product reliability risk and the customer maintenance cost are increased.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, an object of the present invention is to provide a light emitting diode chip and a method for manufacturing the same, which can prevent the problem of electrode digging and electrode falling during wire bonding.
According to the utility model discloses a first aspect provides a light emitting diode chip, include:
the transfer substrate comprises a transfer substrate, and a bonding layer, a dielectric film layer, a P-type ohmic contact layer, a P-type current expansion layer, a P-type limiting layer, an active layer, an N-type limiting layer, an N-type coarsening layer and an N-type ohmic contact layer which are sequentially stacked on the transfer substrate; and the number of the first and second groups,
the upper electrode is positioned on the N-type ohmic contact layer;
a lower electrode positioned under the transfer substrate;
wherein the upper electrode comprises a plurality of metal layers, and the radius of the upper electrode is greater than 30 microns.
Preferably, the buffer layer further comprises a stress gradient layer, wherein the component of the aluminum element is smaller than that of the aluminum element in the N-type coarse layer, and the stress gradient layer is arranged between the N-type coarse layer and the N-type limiting layer.
Preferably, the N-type roughened layer is an aluminum gallium indium phosphide (Al)xGa(1-x))0.5In0.5P；
The N-type limiting layer is an aluminum indium phosphide (AlInP) compound;
the stress gradient layer is an aluminum gallium indium phosphide (Al) compoundyGa(1-y))0.5In0.5P。
Preferably, the multi-metal layer includes: the metal-clad multilayer metal capacitor comprises a first gold layer, a gold-germanium-nickel alloy layer, a second gold layer, a platinum layer and an aluminum layer which are sequentially stacked, wherein the first gold layer is in contact with the N-type ohmic contact layer.
Preferably, the light emitting diode chip is an aluminum gallium indium phosphide light emitting diode chip.
According to the utility model discloses LED chip includes: the transfer substrate comprises a transfer substrate, and a bonding layer, a dielectric film layer, a P-type ohmic contact layer, a P-type current expansion layer, a P-type limiting layer, an active layer, an N-type limiting layer, an N-type coarsening layer and an N-type ohmic contact layer which are sequentially stacked on the transfer substrate; and the upper electrode is positioned on the N-type ohmic contact layer, and the lower electrode is positioned below the transfer substrate, wherein the radius of the upper electrode is more than 30 micrometers. The utility model discloses a light emitting diode chip adopts the radius to be greater than the last electrode of 30 microns, possesses sufficient power supply area, and the power supply is sufficient, and luminous respond well has reduced the pressure of bonding wire in-process, reduces the possibility that the electrode appears digging.
Meanwhile, a stress gradient layer, the component of which is less than that of the aluminum element in the N-type coarsened layer, is arranged between the N-type coarsened layer and the N-type limiting layer, and can solve the problems that the LED chip digs and falls electrodes in the wire welding process, and the reliability of the chip is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic diagram of a conventional led chip structure.
Fig. 2 shows a schematic diagram of a light emitting diode chip structure according to an embodiment of the present invention.
Fig. 3 shows a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present invention.
Fig. 4a to 4f are schematic structural diagrams illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus.
Fig. 1 is a schematic diagram illustrating a conventional vertical led chip structure. As shown in fig. 1, the conventional vertical type light emitting diode chip structure includes: the semiconductor device comprises a transfer substrate 111, an adhesive layer 110, a dielectric film layer 109, a P-type ohmic contact layer 108, a P-type current spreading layer 107, a P-type limiting layer 106, an active layer 105, an N-type limiting layer 104, an N-type coarsening layer 103, an N-type ohmic contact layer 102, an upper electrode 101 positioned on the N-type ohmic contact layer 102, and a lower electrode 112 positioned under the transfer substrate 111, which are sequentially laminated on the transfer substrate 111.
The transfer substrate 111 may be a silicon substrate, or may be another substrate (e.g., silicon carbide, zinc oxide, etc.), the adhesive layer 110 is made of Au, for example, and the dielectric film layer 109 is made of silicon dioxide or magnesium fluoride, for example; the P-type ohmic contact layer 108 is GaP, for example; the P-type current spreading layer 107 is made of GaP, for example; the P-type confinement layer 106 is made of, for example, AlInP; the N-type confinement layer 104 is made of, for example, AlInP; the N-type roughened layer 103 is made of (Al)xGa(1-x))0.5In0.5P) and doped with silicon ions or tellurium ions, wherein the composition of aluminum satisfies 0.4<x<0.9; the N-type ohmic contact layer 102 is made of GaAs, for example.
The upper electrode 101 includes: a gold layer 11, a gold-germanium-nickel alloy layer 12, a gold layer 13, a platinum layer 14, and an aluminum layer 15 are sequentially stacked on the N-type ohmic contact layer 102.
Alternatively, the gold-germanium-nickel alloy layer 12 in the upper electrode may also be made of a gold-germanium alloy material; the platinum layer 14 may be made of titanium; the aluminum layer 15 may be made of gold.
The P-type ohmic contact 108, the P-type current spreading layer 107, the P-type confinement layer 106, the active layer 105, the N-type confinement layer 104, the N-type roughening layer 103 and the N-type ohmic contact layer 102 are structures in an epitaxial wafer. Because the epitaxial wafer is a combination of a plurality of layers, stress can be generated due to the lattice difference between the layers, the stress can change along with the external condition, and the larger the stress is, the larger the risk of digging an electrode and breaking the electrode is.
Fig. 2 shows a schematic structural diagram of a vertical light emitting diode chip according to an embodiment of the present invention. This chip structure will be used to illustrate the light emitting diode chip according to the embodiment of the present invention, and is not to be taken as a limitation to the light emitting diode of the present invention.
As shown in fig. 2, the vertical led chip 100 of the present invention includes: a transfer substrate 111, and an adhesive layer 110, a dielectric film layer 109, a P-type ohmic contact layer 108, a P-type current spreading layer 107, a P-type confinement layer 106, an active layer 105, an N-type confinement layer 104, a stress gradient layer S0, an N-type coarsening layer 103, and an N-type ohmic contact layer 102 which are sequentially laminated on the transfer substrate; and an upper electrode 101 on the N-type ohmic contact layer 102; and a lower electrode 112 positioned under the transfer substrate 111.
The transfer substrate 111 may be a silicon substrate, or may be another substrate (e.g., silicon carbide, zinc oxide, etc.), the adhesive layer 110 is made of Au, for example, and the dielectric film layer 109 is made of silicon dioxide or magnesium fluoride, for example; the P-type ohmic contact layer 108 is GaP, for example; the P-type current spreading layer 107 is made of GaP, for example; the P-type confinement layer 106 is made of, for example, AlInP; the N-type ohmic contact layer 102 is made of GaAs, for example.
A stress gradual change layer S0 is arranged between the N-type rough layer 103 and the N-type limiting layer 104, the components of aluminum elements in the stress gradual change layer are smaller than those of the aluminum elements in the N-type rough layer, and the gradual change of the materials from the N-type rough layer to the N-type limiting layer is realized, so that the lattice mismatch degree is reduced, and the stress is further reduced. Specifically, the material of the N-type roughened layer 103 is (Al)xGa(1-x))0.5In0.5P) and doped with silicon ions or tellurium ions, wherein the composition of aluminum satisfies 0.4<x<0.9, the stress gradient layer S0 is made of (Al)yGa(1-y))0.5In0.5P wherein the composition of aluminum satisfies 0.4<y<The material of the x, N type confinement layer 104 is AlInP.
It should be noted that the above descriptions of the N-type rough layer 103, the stress gradient S0, the N-type confinement layer 104, and the components are only for illustrative purposes, and are not intended to limit the scope of the present invention, and modifications and substitutions that can be made by those skilled in the art are intended to fall within the scope of the present invention.
The upper electrode 101 includes: a gold layer 11, a gold-germanium-nickel alloy layer 12, a gold layer 13, a platinum layer 14, and an aluminum layer 15 are sequentially stacked on the N-type ohmic contact layer 102.
Alternatively, the gold-germanium-nickel alloy layer 12 in the upper electrode 101 may also be made of a gold-germanium alloy material; the platinum layer 14 may be made of titanium; the aluminum layer 15 may be made of gold.
The radius of the upper electrode 101 is larger than 30 microns, so that the pressure in the wire welding process is reduced, and the possibility of electrode digging is reduced.
The utility model discloses a product suitable for vertical electrode and horizontal electrode structure.
Fig. 3 shows a flowchart of a method for manufacturing a light emitting diode chip according to an embodiment of the present invention.
Fig. 4a to 4f are schematic structural diagrams illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the present invention. The following describes a method for manufacturing a light emitting diode chip according to an embodiment of the present invention with reference to fig. 3 to 4 f.
According to a second aspect of the present invention, a method for manufacturing a light emitting diode chip is provided, which is used for manufacturing the light emitting diode chip 100 shown in fig. 2.
In step S301, an etch stop layer S2, an N-type ohmic contact layer 102, an N-type roughened layer 103, a stress gradient layer S0, an N-type confinement layer 104, an active layer 105, a P-type confinement layer 106, a P-type current spreading layer 107, and a P-type ohmic contact layer 108 are sequentially grown on a substrate S1 by an organometallic vapor phase epitaxy method, and as shown in fig. 4a, step S301 is also referred to as preparation of an epitaxial wafer.
Specifically, the substrate S1 in the present embodiment may be GaAs (gallium arsenide) -basedThe plate and the etch stop layer S2 are made of GaInP or AlxGa(1-x)InP; the N-type ohmic contact layer 102 is made of GaAs; the N-type roughened layer 103 is made of (Al)xGa(1-x))0.5In0.5P), wherein the composition of aluminum satisfies 0.4<x<0.9; the stress gradient layer S0 is made of (Al)yGa(1-y))0.5In0.5P, wherein the composition of aluminum satisfies 0.4<y<x; the N-type confinement layer 104 is made of AlInP; the P-type confinement layer 106 is made of AlInP; the P-type current spreading layer 107 is made of GaP; the P-type ohmic contact layer 108 is GaP.
In step S302, the dielectric film layer 109 and the first metal layer S3 are formed on the P-type ohmic contact layer 108 and are sequentially annealed. Specifically, the P-type ohmic contact layer 108 on the upper surface of the epitaxial wafer is cleaned by an organic or acid-base solution, a silicon dioxide or magnesium fluoride dielectric film layer 202 is formed on the P-type ohmic contact layer 108, the dielectric film layer 202 is annealed by a tube furnace at a temperature of 400-480 ℃, the surface of the dielectric film layer 202 is cleaned by the organic or acid-base solution to form a first metal layer S3, the first metal layer S3 is annealed by the tube furnace at a temperature of 400-480 ℃, and the annealing temperature is shown in fig. 4 b.
Wherein, the annealing temperature to the dielectric film layer 202 and the first metal layer S3 is 400-480 ℃, which can achieve the best effect of the utility model. And cleaning the P-type ohmic contact layer 108 by using an organic or acid-base solution to remove impurities on the P-type ohmic contact layer 108, so that the formed dielectric film layer 109 is more uniform and firmer. The dielectric film layer 109 is cleaned by organic or acid-base solution to remove impurities on the dielectric film layer 109, so that the formed first metal layer S3 is more uniform and firmer.
In step S303, a transfer substrate 111 is provided, and the front surface of the transfer substrate 111 is cleaned with an organic or acid-base solution to form a second metal layer S4, as shown in fig. 4 c.
Wherein, the front surface of the transfer substrate 111 is cleaned by organic or acid-base solution to remove impurities on the front surface of the transfer substrate 111, so that the formed second metal layer S4 is uniform and stable.
In step S304, the transfer substrate 111 is bonded to the structure shown in fig. 4b, specifically, the second metal layer S4 and the first metal layer S3 are bonded by a bonding apparatus, and the bonding layer 110 is formed after bonding. As shown in fig. 4 d.
In step S305, the substrate S1 and the etch stop layer S2 are removed, and the upper electrode 101 is fabricated and annealed, as shown in FIG. 4 e.
Specifically, ammonium hydroxide and hydrogen peroxide are used in a volume ratio of 1: 5, the substrate S1 is removed, and the etching stopper S2 is removed with a mixed solution of hydrochloric acid and phosphoric acid.
The substrate S1 and the corrosion stop layer S2 are removed respectively more thoroughly by the two mixed solutions, and the effect is better.
Coating a positive photoresist on the N-type ohmic contact layer 102, exposing for 5-15 seconds, developing for 1min, drying, baking at 100 ℃ for 30 min, corroding part of the N-type ohmic contact layer 102 by using a mixed solution of phosphoric acid and hydrogen peroxide in a volume ratio of 1:30 to expose part of the region of the N-type roughened layer 103, removing the photoresist by using a degumming solution, coating a negative photoresist on the surfaces of the N-type roughened layer 103 and the N-type ohmic contact layer 102, exposing for 5-15 seconds, baking at 120 ℃ for 30 min, developing for 1min, drying, and manufacturing the upper electrode 101 by using electron beams in an evaporation or ion sputtering mode.
The upper electrode 101 is annealed by adopting a tube furnace or a rapid annealing furnace, the annealing temperature is 290-330 ℃, and compared with the traditional electrode annealing condition of 380 ℃, the annealing temperature is obviously reduced, so that the phenomenon that crystal lattices are damaged due to serious diffusion between metal and an epitaxial wafer is avoided, and the bearing capacity of the bonding wire and the reliability of products are improved.
The radius of the upper electrode 101 is larger than 30 microns, so that the pressure in the wire welding process is reduced, and the possibility of electrode digging is reduced.
In step S306, the N-type roughened layer is etched to form an etching track, the N-type roughened layer is roughened, a passivation layer is formed on the side wall of the cutting track, the transfer substrate is processed, then a lower electrode is formed under the transfer substrate, the lower electrode is annealed, and cutting is performed along the etching track, as shown in fig. 4 f.
Specifically, coating photoresist on the surface of the N-type rough layer 103 (the photoresist is used for protection of subsequent dry etching), exposing for 5-15 seconds, baking for 30 minutes at 120 ℃, developing for 1 minute, cleaning and blow-drying, etching a cutting channel (a separating device) by using dry etching equipment, wherein the etching depth is 3-9 microns, and immersing into photoresist removing liquid to remove the photoresist; after the steps are completed, coating positive photoresist on the surface of the N-type roughened layer 103, exposing for 5-15 seconds, baking at 120 ℃ for 30 minutes, developing for 1 minute, cleaning and blow-drying, immersing in RH07 roughening solution, roughening the surface, and immersing in photoresist removing solution to remove the positive photoresist. And forming a passivation layer on the side wall of the cutting channel by using a vapor deposition method (PECVD).
The transfer substrate 111 is processed to form the lower electrode 112. Specifically, the thickness of the transfer substrate 111 is reduced to 100-200 microns by treatment with a grinding wheel or large-disc grinding equipment or corrosion treatment with a chemical solution; the lower electrode 112 is manufactured by immersing the substrate in an organic solution for cleaning, and performing electron beam evaporation or ion sputtering. The lower electrode 112 is annealed by a tube furnace or a Rapid Thermal Processing (RTP), and the annealing temperature is between 180 and 250 ℃.
Wherein, the annealing temperature of the lower electrode is 180-250 ℃, which can achieve the best effect of the utility model.
The light emitting diode chip is formed by laser cutting, testing, splitting and visual inspection.
Therefore, the preparation of the light emitting diode chip 100 is completed, the prepared light emitting diode chip 100 can effectively prevent the problems of electrode digging and electrode failure, and the reliability is enhanced.
According to the utility model discloses LED chip and preparation method thereof is provided with the stress gradual change layer between N type coarsening layer and N type restriction layer, and the component of aluminium element is less than in the stress gradual change layer the component of aluminium element in the N type coarsening layer has realized the gradual change of N type coarsening layer to N type restriction layer material, reduces lattice mismatch degree in the epitaxial wafer in order to reduce stress. The problems of electrode digging and electrode falling in the wire welding process are prevented, and the reliability of the chip is enhanced.
In the above description, the details of the patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present invention, and these alternatives and modifications are intended to fall within the scope of the present invention.
Claims (5)
1. A light emitting diode chip comprising:
the transfer substrate comprises a transfer substrate, and a bonding layer, a dielectric film layer, a P-type ohmic contact layer, a P-type current expansion layer, a P-type limiting layer, an active layer, an N-type limiting layer, an N-type coarsening layer and an N-type ohmic contact layer which are sequentially stacked on the transfer substrate; and the number of the first and second groups,
the upper electrode is positioned on the N-type ohmic contact layer;
a lower electrode positioned under the transfer substrate;
wherein the upper electrode comprises a plurality of metal layers, and the radius of the upper electrode is greater than 30 microns.
2. The light emitting diode chip of claim 1, further comprising a stress-graded layer having a composition of aluminum element smaller than a composition of aluminum element in the N-type roughened layer, the stress-graded layer being disposed between the N-type roughened layer and the N-type confinement layer.
3. The light-emitting diode chip of claim 2,
the N-type coarsened layer is aluminum galliumIndium phosphorus Compound (Al)xGa(1-x))0.5In0.5P；
The N-type limiting layer is an aluminum indium phosphide (AlInP) compound;
the stress gradient layer is an aluminum gallium indium phosphide (Al) compoundyGa(1-y))0.5In0.5P。
4. The light-emitting diode chip of claim 1,
the multi-layer metal layer includes: the metal-clad multilayer metal capacitor comprises a first gold layer, a gold-germanium-nickel alloy layer, a second gold layer, a platinum layer and an aluminum layer which are sequentially stacked, wherein the first gold layer is in contact with the N-type ohmic contact layer.
5. The light-emitting diode chip of claim 1,
the light emitting diode chip is an aluminum gallium indium phosphide light emitting diode chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922493632.7U CN211789074U (en) | 2019-12-31 | 2019-12-31 | Light-emitting diode chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922493632.7U CN211789074U (en) | 2019-12-31 | 2019-12-31 | Light-emitting diode chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211789074U true CN211789074U (en) | 2020-10-27 |
Family
ID=72890769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922493632.7U Active CN211789074U (en) | 2019-12-31 | 2019-12-31 | Light-emitting diode chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211789074U (en) |
-
2019
- 2019-12-31 CN CN201922493632.7U patent/CN211789074U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6917417B2 (en) | Photoelectric device and its manufacturing method | |
| US8143148B1 (en) | Self-aligned multi-dielectric-layer lift off process for laser diode stripes | |
| US8383438B2 (en) | Method for fabricating InGaAIN light-emitting diodes with a metal substrate | |
| US9070839B2 (en) | Method of manufacturing a light emitting diode | |
| US10840419B2 (en) | Nitride semiconductor light-emitting device and manufacture method therefore | |
| KR20080043648A (en) | Method of manufacturing vertical light emitting device | |
| TW200849355A (en) | Method for roughening an object surface | |
| CN111106214A (en) | Light emitting diode chip and preparation method thereof | |
| US10008634B2 (en) | Thin-film flip-chip light emitting diode having roughening surface and method for manufacturing the same | |
| TWI430475B (en) | Method of manufacturing light emitting diode | |
| KR20110049799A (en) | Method for fabricating semiconductor light-emitting device with double-sided passivation | |
| KR100648136B1 (en) | Light Emitting Diode and manufacturing method of the same | |
| CN211929520U (en) | Light-emitting diode chip | |
| TWI412157B (en) | Method for forming a light emitting device | |
| CN211789074U (en) | Light-emitting diode chip | |
| KR101018280B1 (en) | Vertical Light Emitting Diode and manufacturing method of the same | |
| CN112885936B (en) | Micro-LED array with transparent electrode structure and preparation method | |
| US20130292692A1 (en) | Light emitting diode | |
| KR101868232B1 (en) | Light emitting diode comprising hybrid transparent electrode | |
| JP5897365B2 (en) | Semiconductor light emitting device and manufacturing method thereof | |
| KR101140138B1 (en) | Method for manufacturing vertical light emitting diode | |
| JP2007189060A (en) | Semiconductor light-emitting element, junction substrate therefor, and manufacturing method thereof | |
| CN114388675A (en) | GaN-based micro LED chip and preparation method thereof | |
| KR20090103217A (en) | Fabrication of vertical structured light emitting diodes using group 3 nitride-based semiconductors and its related methods | |
| TW201344967A (en) | LED electrode contact structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |