CN211720466U - Synchronous rectification MOS tube driving circuit - Google Patents
Synchronous rectification MOS tube driving circuit Download PDFInfo
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- CN211720466U CN211720466U CN201922470820.8U CN201922470820U CN211720466U CN 211720466 U CN211720466 U CN 211720466U CN 201922470820 U CN201922470820 U CN 201922470820U CN 211720466 U CN211720466 U CN 211720466U
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- resistor
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- mos tube
- comparator cmp
- synchronous rectification
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Abstract
The utility model provides a synchronous rectification MOS pipe drive circuit, including comparator CMP, diode D1, diode D2, resistance R1, resistance R2, wherein, a termination power VCC1 of resistance R1, another termination of resistance R1 diode D1 'S positive pole, diode D1' S negative pole connects MOS pipe SF 'S source S, a termination power VCC1 of resistance R2, another termination of resistance R2 diode D2' S positive pole, diode D2 'S negative pole connects MOS pipe SF' S drain electrode D, and MOS pipe SF 'S grid G connects power VCC2 respectively with comparator CMP' S output. The utility model has the advantages that: the driving function same as that of the synchronous rectification chip is realized by using a comparator (or an operational amplifier), a diode, a resistor and the like with low cost, and the cost is low.
Description
Technical Field
The utility model relates to a synchronous rectification drive circuit especially relates to a synchronous rectification MOS manages drive circuit.
Background
The driving signal of the synchronous rectification MOS tube is usually generated by a synchronous rectification driving chip, and the use of the synchronous rectification driving chip has the disadvantage of higher cost.
Disclosure of Invention
In order to solve the problems in the prior art, the utility model provides a synchronous rectification MOS manages drive circuit.
The utility model provides a synchronous rectification MOS pipe drive circuit, including comparator CMP, diode D1, diode D2, resistance R1, resistance R2, wherein, a termination power VCC1 of resistance R1, another termination of resistance R1 diode D1 'S positive pole, diode D1' S negative pole connects the source S of MOS pipe SF, a termination power VCC1 of resistance R2, another termination of resistance R2 the positive pole of diode D2, the negative pole of diode D2 connects the drain-source resistance D of MOS pipe SF, the grid G of MOS pipe SF with the output of comparator CMP connects power VCC2 respectively, the homophase input of comparator CMP connect in between the positive poles of resistance R1, diode D1, the reverse phase input of comparator CMP connect in between the positive pole of resistance R2, diode D2, when the body diode of MOS pipe SF is flowed through to the electric current, its drain-source D voltage is less than the source S voltage, correspondingly, the voltage of the inverting input terminal of the comparator CMP is lower than that of the non-inverting input terminal, the comparator CMP outputs a high level to be applied to the gate G of the MOS transistor SF, the MOS transistor SF is completely turned on, when no current flows through the MOS transistor SF, the power supply VCC1 is applied to two ends of the drain D and the source S of the MOS transistor SF through the resistor R2 and the diode D2, the body diode of the MOS transistor SF is turned off in the reverse direction, the voltage of the inverting input terminal of the comparator CMP is close to the power supply VCC1 and is much higher than that of the non-inverting input terminal, the comparator CMP outputs a low level, the voltage of the gate G of the MOS transistor SF is pulled down, the MOS transistor SF is completely turned off, and when the output voltage is higher, the diode D2 is turned.
As a further improvement of the present invention, the power source VCC1 and the power source VCC2 are shared all the way, and the comparator CMP is replaced by an operational amplifier.
As a further improvement of the present invention, the non-inverting input terminal of the comparator CMP is connected to a resistor R +, and the inverting input terminal of the comparator CMP is connected to a resistor R-.
As a further improvement of the present invention, the output terminal of the comparator CMP is connected with a pull-up resistor R3, and the pull-up resistor R3 is connected to the power supply VCC 2.
As a further improvement of the present invention, the gate G of the MOS transistor SF is connected to a driving resistor Rg, which is respectively connected to the output end of the comparator CMP and the pull-up resistor R3.
As a further improvement, the output of the comparator CMP is connected with an one-level amplifying circuit, which is connected with the driving resistor Rg in series and then connected with the gate G of the MOS transistor SF.
As a further improvement of the utility model, the one-level amplifying circuit is a one-level push-pull circuit.
As a further improvement of the present invention, the diode D1 is replaced by a resistor R4, and the diode D2 is replaced by a resistor R5.
As a further improvement of the present invention, a resistor R4 is connected in series between the anode of the diode D1 and the resistor R1, the non-inverting input terminal of the comparator CMP is connected between the resistor R1 and the resistor R4, a resistor R5 is connected in series between the anode of the diode D2 and the resistor R2, and the inverting input terminal of the comparator CMP is connected between the resistor R1 and the resistor R5.
As a further improvement of the present invention, a feedback resistor Rf is connected between the non-inverting input terminal and the output terminal of the comparator CMP.
As a further improvement of the present invention, the diodes D1 and D2 are omitted.
The utility model has the advantages that: through the scheme, the driving function same as that of the synchronous rectification chip is realized by using the comparator (or the operational amplifier), the diode, the resistor and the like with low cost, and the cost is low.
Drawings
Fig. 1 is a schematic diagram of a first embodiment of a synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 2 is a schematic diagram of a second embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 3 is a schematic diagram of a second embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 4 is a schematic diagram of a third embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 5 is a schematic diagram of a third embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 6 is a schematic diagram of a third embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 7 is a schematic diagram of a third embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 8 is a schematic diagram of a fourth embodiment of the synchronous rectification MOS transistor driving circuit of the present invention.
Fig. 9 is a schematic diagram of a fourth embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Fig. 10 is a schematic diagram of a fourth embodiment of the synchronous rectification MOS transistor driving circuit according to the present invention.
Detailed Description
The present invention will be further described with reference to the following description and embodiments.
Example one
As shown in fig. 1, a synchronous rectification MOS transistor driving circuit includes a comparator CMP, a diode D1, a diode D2, a resistor R1, and a resistor R2, wherein one end of the resistor R1 is connected to a power VCC1, the other end of the resistor R1 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the source S of the MOS transistor SF, one end of the resistor R2 is connected to the power VCC1, the other end of the resistor R2 is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the drain D of the MOS transistor SF, the gate G of the MOS transistor SF and the output end of the comparator CMP are respectively connected to the power VCC2, the non-inverting input end of the comparator CMP is connected between the anodes of the resistors R1 and the diode D1, the inverting input end of the comparator CMP is connected between the anodes of the resistors R2 and the anode of the diode D2, when a current flows through the body diode of the MOS transistor SF, the drain D has a voltage, correspondingly, the voltage of the inverting input terminal of the comparator CMP is lower than that of the non-inverting input terminal, the comparator CMP outputs a high level to be applied to the gate G of the MOS transistor SF, the MOS transistor SF is completely turned on, when no current flows through the MOS transistor SF, the power supply VCC1 is applied to two ends of the drain D and the source S of the MOS transistor SF through the resistor R2 and the diode D2, the body diode of the MOS transistor SF is turned off in the reverse direction, the voltage of the inverting input terminal of the comparator CMP is close to the power supply VCC1 and is much higher than that of the non-inverting input terminal, the comparator CMP outputs a low level, the voltage of the gate G of the MOS transistor SF is pulled down, the MOS transistor SF is completely turned off, and when the output voltage is higher, the diode D2 is turned.
The comparator CMP may be replaced with an operational amplifier.
The non-inverting input terminal of the comparator CMP is connected with a resistor R +, and the inverting input terminal of the comparator CMP is connected with a resistor R-.
The output end of the comparator CMP is connected with a pull-up resistor R3, and the pull-up resistor R3 is connected with a power supply VCC 2.
The gate G of the MOS transistor SF is connected with a driving resistor Rg, and the driving resistor Rg is respectively connected with the output end of the comparator CMP and the pull-up resistor R3.
The MOS transistor SF is a driven synchronous rectification MOS, and the current direction is from the source S to the drain D. The input end of the comparator CMP (which can be replaced by an operational amplifier) is respectively connected with the source S and the drain D of the MOS transistor through a resistor R + (can be omitted), a diode D1 and a resistor R- (can be omitted), and a diode D2 is connected with the source S and the drain D of the MOS transistor, and the resistor R1 and the resistor R2 ensure that the diode D1 and the diode D2 can be reliably conducted. R3 is the output pull-up resistor of the comparator, and R3 can be omitted if an operational amplifier or totem-pole output comparator is used. Rg is MOS pipe drive resistance, can replace with diode resistance combination, or save.
The MOS tube works in a synchronous rectification state to replace the original diode rectification, so that the conduction loss can be reduced, and the electric energy conversion efficiency is improved.
The shortcoming of using the synchronous rectification driving chip is that the cost is higher, the utility model discloses the driving function that realizes the same with synchronous rectification chip such as using low cost's comparator (or operational amplifier), diode, resistance.
Example two
As shown in fig. 2 to fig. 3, in order to increase the speed of turning on and off the MOS transistor, a first stage of amplifying circuit may be added at the output end of the comparator, and typically a first stage of push-pull circuit is added to drive the MOS transistor SF.
The power supplies VCC1 and VCC2 may share one path.
EXAMPLE III
As shown in fig. 4 to 7, the diode D1 and the diode D2 are not essential, and may be replaced by resistors or series-parallel resistors, and the diode D1 and the diode D2 may be omitted when the output voltage is relatively low.
Example four
As shown in fig. 8 to 10, a feedback resistor Rf is added between the non-inverting input terminal and the output terminal of the comparator CMP, so that the comparator CMP can operate in a hysteresis comparison state, thereby reducing unnecessary false switching.
The utility model provides a pair of synchronous rectification MOS manages drive circuit has avoided the use of synchronous rectification chip, the cost is reduced.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.
Claims (10)
1. The utility model provides a synchronous rectification MOS manages drive circuit which characterized in that: the circuit comprises a comparator CMP, a diode D1, a diode D2, a resistor R1 and a resistor R2, wherein one end of the resistor R1 is connected with a power VCC1, the other end of the resistor R1 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the source S of an MOS tube SF, one end of the resistor R2 is connected with the power VCC1, the other end of the resistor R2 is connected with the anode of the diode D2, the cathode of the diode D2 is connected with the drain D of the MOS tube SF, the grid G of the MOS tube SF and the output end of the comparator CMP are respectively connected with the power VCC2, the non-inverting input end of the comparator CMP is connected between the anodes of the resistors R1 and the diode D1, the inverting input end of the comparator CMP is connected between the anodes of the resistors R2 and the diode D2, when current flows through the body diode of the MOS tube SF, the drain D voltage is lower than the source S voltage, and correspondingly, and the inverting input end voltage of the non, the comparator CMP outputs high level to be applied to a grid G of the MOS tube SF, the MOS tube SF is completely conducted, when no current flows through the MOS tube SF, a power supply VCC1 is applied to two ends of a drain electrode D and a source electrode S of the MOS tube SF through a resistor R2 and a diode D2, a body diode of the MOS tube SF is reversely cut off, the voltage of an inverting input end of the comparator CMP is close to the voltage VCC1 and is far higher than that of a non-inverting input end, the comparator CMP outputs low level, the voltage of the grid G of the MOS tube SF is pulled down, the MOS tube SF is completely closed, and when the output voltage is higher, the diode D2 is reversely cut off to play a role in protecting a driving circuit.
2. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: power VCC1, power VCC2 share one way, comparator CMP adopts operational amplifier to replace.
3. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: the non-inverting input terminal of the comparator CMP is connected with a resistor R +, and the inverting input terminal of the comparator CMP is connected with a resistor R-.
4. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: the output end of the comparator CMP is connected with a pull-up resistor R3, and the pull-up resistor R3 is connected with a power supply VCC 2.
5. The synchronous rectification MOS tube driving circuit as claimed in claim 4, wherein: the gate G of the MOS transistor SF is connected with a driving resistor Rg, and the driving resistor Rg is respectively connected with the output end of the comparator CMP and the pull-up resistor R3.
6. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: the output end of the comparator CMP is connected with a first-stage amplifying circuit, and the first-stage amplifying circuit is connected with a driving resistor Rg in series and then connected with a grid G of the MOS tube SF.
7. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: the diode D1 and the diode D2 are omitted.
8. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: the diode D1 is replaced by a resistor R4, and the diode D2 is replaced by a resistor R5.
9. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: a resistor R4 is connected in series between the anode of the diode D1 and the resistor R1, the non-inverting input end of the comparator CMP is connected between the resistor R1 and the resistor R4, a resistor R5 is connected in series between the anode of the diode D2 and the resistor R2, and the inverting input end of the comparator CMP is connected between the resistor R1 and the resistor R5.
10. The synchronous rectification MOS tube driving circuit as claimed in claim 1, wherein: a feedback resistor Rf is connected between the non-inverting input end and the output end of the comparator CMP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922470820.8U CN211720466U (en) | 2019-12-31 | 2019-12-31 | Synchronous rectification MOS tube driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922470820.8U CN211720466U (en) | 2019-12-31 | 2019-12-31 | Synchronous rectification MOS tube driving circuit |
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| Publication Number | Publication Date |
|---|---|
| CN211720466U true CN211720466U (en) | 2020-10-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922470820.8U Expired - Fee Related CN211720466U (en) | 2019-12-31 | 2019-12-31 | Synchronous rectification MOS tube driving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113472206A (en) * | 2021-05-25 | 2021-10-01 | 中国电子科技集团公司第四十一研究所 | Self-driven synchronous rectification circuit |
-
2019
- 2019-12-31 CN CN201922470820.8U patent/CN211720466U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113472206A (en) * | 2021-05-25 | 2021-10-01 | 中国电子科技集团公司第四十一研究所 | Self-driven synchronous rectification circuit |
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| GR01 | Patent grant | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20201020 Termination date: 20201231 |