CN211700244U - DFN power integrated semiconductor device - Google Patents
DFN power integrated semiconductor device Download PDFInfo
- Publication number
- CN211700244U CN211700244U CN202020444913.3U CN202020444913U CN211700244U CN 211700244 U CN211700244 U CN 211700244U CN 202020444913 U CN202020444913 U CN 202020444913U CN 211700244 U CN211700244 U CN 211700244U
- Authority
- CN
- China
- Prior art keywords
- chip
- pin
- dfn
- semiconductor device
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses a DFN power integrated semiconductor device, wherein the front and back end faces of a chip are respectively bonded with a metal radiating fin through a heat conducting adhesive layer, the left and right end faces of the chip are respectively bonded with a left metal radiating fin and a right metal radiating fin through a heat conducting adhesive layer, the left metal radiating fin and the right metal radiating fin are respectively provided with a plurality of left through holes and right through holes for embedding a left pin and a right pin, and the left through holes and the right through holes are respectively insulated and isolated from the left pin and the right pin through epoxy packaging bodies; the upper surface of chip has a soaking plate through the laminating of heat-conducting adhesive layer, and the surface that this soaking plate and chip carried on the back mutually has the bellying of a plurality of interval setting, and this bellying embedding is in the epoxy encapsulation body. The utility model discloses DFN power integrated semiconductor device has increased effective heat radiating area, improves the radiating effect for radiating speed has also prevented epoxy packaging body and chip layering, thereby prevents during steam gets into the device.
Description
Technical Field
The utility model relates to a semiconductor device technical field especially relates to a DFN power integrated semiconductor device.
Background
DFN is a recent electronic packaging technology that uses advanced double-sided flat lead-free packaging. DFN platforms are the latest surface mount packaging technology. The mounting pads, solder mask and stencil pattern design and assembly process of the printed circuit board all follow the corresponding principles. The DFN platform has versatility to allow one or more semiconductor devices to be connected within a lead-free package.
In the existing DFN packaging structure of the chip, heat on the chip is conducted out and dissipated through the heat dissipation region by setting the heat dissipation region. However, in the prior art, the heat dissipation area mainly dissipates heat through contact with the external environment, but the contact area between the heat dissipation area and the external environment is limited, so the heat dissipation performance is relatively general. How to overcome the above technical problems has been the direction of efforts of those skilled in the art.
Disclosure of Invention
The utility model aims at providing a DFN power integrated semiconductor device, this DFN power integrated semiconductor device have increased effective heat radiating area, improve the radiating effect for radiating speed also prevents epoxy packaging body and chip layering, thereby in the prevention steam gets into the device.
In order to achieve the above purpose, the utility model adopts the technical scheme that: a DFN power integrated semiconductor device comprises a chip, a plurality of left pins and right pins, wherein the left pins and the right pins are positioned in an epoxy packaging body, one ends of the left pins and the right pins are electrically connected with the chip and are respectively positioned on the left side and the right side of the chip, the other ends of the left pins and the right pins extend out of the epoxy packaging body, metal radiating fins are bonded on the front end surface and the rear end surface of the chip through heat conducting adhesive layers, left metal radiating fins and right metal radiating fins are bonded on the left end surface and the right end surface of the chip through heat conducting adhesive layers, a plurality of left through holes and right through holes for embedding the left pins and the right pins are formed in the left metal radiating fins and the right metal radiating fins respectively, and the left through holes and the right; the upper surface of chip has a soaking plate through the laminating of heat-conducting adhesive layer, and the surface that this soaking plate and chip carried on the back mutually has the bellying of a plurality of interval setting, and this bellying embedding is in the epoxy encapsulation body.
The further improved scheme in the technical scheme is as follows:
1. in the above scheme, the metal radiating fins are aluminum radiating fins, copper radiating fins or aluminum alloy radiating fins.
2. In the above scheme, the left metal radiating fin and the right metal radiating fin are both aluminum radiating fins, copper radiating fins or aluminum alloy radiating fins.
3. In the above scheme, the lower end surfaces of the left pin and the right pin are slightly lower than the lower surface of the epoxy packaging body.
Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:
1. the utility model discloses DFN power integrated semiconductor device, the terminal surface all bonds through heat-conducting adhesive layer around its chip has metal fin, the terminal surface all bonds through heat-conducting adhesive layer has left metal fin and right metal fin about the chip, and left through-hole and right through-hole that a plurality of supplied left pin, right pin embedding are opened respectively to this left metal fin and right metal fin, left side through-hole, right through-hole respectively with left pin, right pin between through the epoxy packaging body insulation isolation, increased effective heat radiating area, improve the radiating effect for radiating speed, also improved the intensity and the reliability of device and prolonged the life of chip.
2. The utility model discloses DFN power integrated semiconductor device, the upper surface of its chip has a soaking plate through the laminating of heat-conducting glue layer, and the surface that this soaking plate and chip carried on the back mutually has the bellying of a plurality of interval settings, and this bellying imbeds in the epoxy packaging body, has both strengthened device bulk strength, also prevents epoxy packaging body and chip layering to prevent steam from getting into the device; in addition, the lower end surfaces of the left pin and the right pin are slightly lower than the lower surface of the epoxy packaging body, so that a gap for air flow to flow is formed between the semiconductor device and the PCB, and heat can be taken away quickly.
Drawings
Fig. 1 is a schematic structural diagram of a DFN power integrated semiconductor device according to the present invention;
fig. 2 is a schematic top sectional view of fig. 1.
In the above drawings: 1. an epoxy package; 2. a chip; 3. a left pin; 4. a right pin; 5. a heat-conducting adhesive layer; 6. a metal heat sink; 7. a left metal heat sink; 8. a right metal heat sink; 9. a left through hole; 10. a right through hole; 13. a vapor chamber; 14. a raised portion.
Detailed Description
Example 1: a DFN power integrated semiconductor device comprises a chip 2 positioned in an epoxy packaging body 1, and a plurality of left pins 3 and right pins 4, wherein one ends of the left pins 3 and the right pins 4 are electrically connected with the chip 2 and respectively positioned at the left side and the right side of the chip 2, the other ends of the left pins 3 and the right pins 4 extend out of the epoxy packaging body 1, metal radiating fins 6 are bonded on the front end face and the rear end face of the chip 2 through heat conducting glue layers 5, left metal radiating fins 7 and right metal radiating fins 8 are bonded on the left end face and the right end face of the chip 2 through the heat conducting glue layers 5, a plurality of left through holes 9 and right through holes 10 for embedding the left pins 3 and the right pins 4 are respectively formed in the left metal radiating fins 7 and the right metal radiating fins 8, and the left through holes 9 and the right through holes 10 are respectively insulated and isolated from; the upper surface of chip 2 has a soaking plate 13 through the laminating of thermal conductive adhesive layer 5, and this soaking plate 13 has the bellying 14 that a plurality of interval set up with the surface that chip 2 carried on the back mutually, and this bellying 14 imbeds in the epoxy packaging body 1.
The metal heat sink 6 is an aluminum heat sink, and the left metal heat sink 7 and the right metal heat sink 8 are both aluminum heat sinks.
The lower end surfaces of the left pin 3 and the right pin 4 are slightly lower than the lower surface of the epoxy package 1.
Example 2: a DFN power integrated semiconductor device comprises a chip 2 positioned in an epoxy packaging body 1, and a plurality of left pins 3 and right pins 4, wherein one ends of the left pins 3 and the right pins 4 are electrically connected with the chip 2 and respectively positioned at the left side and the right side of the chip 2, the other ends of the left pins 3 and the right pins 4 extend out of the epoxy packaging body 1, metal radiating fins 6 are bonded on the front end face and the rear end face of the chip 2 through heat conducting glue layers 5, left metal radiating fins 7 and right metal radiating fins 8 are bonded on the left end face and the right end face of the chip 2 through the heat conducting glue layers 5, a plurality of left through holes 9 and right through holes 10 for embedding the left pins 3 and the right pins 4 are respectively formed in the left metal radiating fins 7 and the right metal radiating fins 8, and the left through holes 9 and the right through holes 10 are respectively insulated and isolated from; the upper surface of chip 2 has a soaking plate 13 through the laminating of thermal conductive adhesive layer 5, and this soaking plate 13 has the bellying 14 that a plurality of interval set up with the surface that chip 2 carried on the back mutually, and this bellying 14 imbeds in the epoxy packaging body 1.
The metal heat sink 6 is a copper heat sink,
the left metal heat sink 7 and the right metal heat sink 8 are both copper heat sinks.
The lower end surfaces of the left pin 3 and the right pin 4 are slightly lower than the lower surface of the epoxy package 1.
When the DFN power integrated semiconductor device is adopted, the effective heat dissipation area is effectively increased, the heat dissipation effect is improved, the heat dissipation speed is accelerated, the strength and the reliability of the device are improved, and the service life of a chip is prolonged; in addition, the integral strength of the device is enhanced, and the epoxy packaging body and the chip are prevented from being layered, so that water vapor is prevented from entering the device; in addition, the lower end surfaces of the left pin and the right pin are slightly lower than the lower surface of the epoxy packaging body, so that a gap for air flow to flow is formed between the semiconductor device and the PCB, and heat can be taken away quickly.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
Claims (4)
1. A DFN power integrated semiconductor device, characterized by: including chip (2), one end that are located epoxy packaging body (1) and be connected with chip (2) electricity and be located a plurality of left pin (3), right pin (4) of chip (2) left and right sides respectively, left side pin (3), right pin (4) respective other end extend from epoxy packaging body (1), the terminal surface all bonds through heat-conducting adhesive layer (5) around chip (2) has metal fin (6), the terminal surface all bonds through heat-conducting adhesive layer (5) has left metal fin (7) and right metal fin (8) about chip (2), and left through-hole (9) and right through-hole (10) that this left metal fin (7) and right metal fin (8) were opened respectively that a plurality of supplied left pin (3), right pin (4) to imbed, left through-hole (9), right through-hole (10) respectively with left pin (3), The right pins (4) are insulated and isolated through the epoxy packaging body (1); the upper surface of chip (2) has a soaking plate (13) through heat-conducting adhesive layer (5) laminating, and this soaking plate (13) has bellying (14) that a plurality of interval set up with the surface that chip (2) carried on the back mutually, and this bellying (14) imbed in epoxy packaging body (1).
2. The DFN power integrated semiconductor device of claim 1, wherein: the metal radiating fins (6) are aluminum radiating fins, copper radiating fins or aluminum alloy radiating fins.
3. The DFN power integrated semiconductor device of claim 1, wherein: the left metal radiating fin (7) and the right metal radiating fin (8) are both aluminum radiating fins, copper radiating fins or aluminum alloy radiating fins.
4. The DFN power integrated semiconductor device of claim 1, wherein: the lower end surfaces of the left pin (3) and the right pin (4) are slightly lower than the lower surface of the epoxy packaging body (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020444913.3U CN211700244U (en) | 2020-03-31 | 2020-03-31 | DFN power integrated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020444913.3U CN211700244U (en) | 2020-03-31 | 2020-03-31 | DFN power integrated semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211700244U true CN211700244U (en) | 2020-10-16 |
Family
ID=72782029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020444913.3U Active CN211700244U (en) | 2020-03-31 | 2020-03-31 | DFN power integrated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211700244U (en) |
-
2020
- 2020-03-31 CN CN202020444913.3U patent/CN211700244U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3346263B2 (en) | Printed wiring board and manufacturing method thereof | |
| JPH0917919A (en) | Semiconductor device | |
| US9269685B2 (en) | Integrated circuit package and packaging methods | |
| EP1571706B1 (en) | Electronic device | |
| CN109616452B (en) | Heat radiation assembly, corresponding heat radiation device and corresponding circuit board | |
| JP2013077691A (en) | Component built-in substrate package, manufacturing method thereof and component built-in substrate | |
| US20020189853A1 (en) | BGA substrate with direct heat dissipating structure | |
| CN114792680A (en) | Power management chip packaging structure and manufacturing method thereof | |
| CN211700253U (en) | DFN device packaging structure for surface mounting | |
| CN111312670B (en) | Heat dissipation packaging method | |
| JP2002171050A (en) | Printed wiring board | |
| CN211700244U (en) | DFN power integrated semiconductor device | |
| JPH05275580A (en) | Semiconductor device | |
| CN211700255U (en) | DFN packaged semiconductor device | |
| JP3931696B2 (en) | Electronic equipment | |
| JP2002151634A (en) | Board radiator | |
| CN201066696Y (en) | Encapsulation structure for high-power LED chip and high-power LED lighting part | |
| CN200990387Y (en) | Large power LED chip package structure and large power LED illuminating device | |
| JP2001168226A (en) | Semiconductor package and semiconductor device | |
| CN211929475U (en) | Heat dissipation packaging device | |
| KR20000031820A (en) | Printed circuit board, method for producing printed circuit board and semiconductor package using thereof | |
| CN214228544U (en) | Copper-based heat dissipation circuit board | |
| CN220106505U (en) | DFN packaged semiconductor device | |
| CN212587482U (en) | Semiconductor product with top heat dissipation function and electronic product | |
| CN210984717U (en) | Heat dissipation packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |