CN211656003U - Adapter pulse width modulation drive circuit - Google Patents

Adapter pulse width modulation drive circuit Download PDF

Info

Publication number
CN211656003U
CN211656003U CN202020412253.0U CN202020412253U CN211656003U CN 211656003 U CN211656003 U CN 211656003U CN 202020412253 U CN202020412253 U CN 202020412253U CN 211656003 U CN211656003 U CN 211656003U
Authority
CN
China
Prior art keywords
resistor
pulse width
adapter
mos
drive circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202020412253.0U
Other languages
Chinese (zh)
Inventor
叶庆兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Haiyingte Power Technology Co ltd
Original Assignee
Suzhou Jiande Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Jiande Electronic Technology Co ltd filed Critical Suzhou Jiande Electronic Technology Co ltd
Priority to CN202020412253.0U priority Critical patent/CN211656003U/en
Application granted granted Critical
Publication of CN211656003U publication Critical patent/CN211656003U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Electronic Switches (AREA)
  • Amplifiers (AREA)

Abstract

The utility model provides an adapter pulse width modulation drive circuit, it includes: the pulse width modulator U1, a mos tube Q1, a release unit, a resistor R1 and a resistor R3; the pulse width modulator U1 has a first pin1 and a second pin2, the first pin1 is connected to the gate of the mos transistor Q1 through a resistor R1, and the release unit includes: the first pin1 is further connected with the source of the mos tube Q1 through a resistor R2, a transistor Q2 and a resistor R3 in sequence, the base of the transistor Q2 is connected with the resistor R2, the collector is connected between the resistor R1 and the mos tube Q1, and the emitter is connected with the source of the mos tube Q1 through the resistor R3. The utility model discloses an adapter pulse width modulation drive circuit is through providing the route of bleeding when mos pipe turn-offs, and when mos pipe turn-offs, triode Q2 switches on to the earthing terminal is released through triode Q2 to the voltage on the mos pipe drive signal, has reduced the electromagnetic energy, thereby can improve electromagnetic interference.

Description

Adapter pulse width modulation drive circuit
Technical Field
The utility model relates to a drive circuit especially relates to an adapter pulse width modulation drive circuit.
Background
The primary side of the adapter usually adopts Pulse Width Modulation (PWM), and the pulse width modulation drives a field effect semiconductor (MOSFET) through a PWM signal, wherein the PWM signal is a high-frequency (65K-100 KHz) signal. However, the high frequency drive signal will generate an electromagnetic signal that can interfere with and affect the peripheral electronics, thereby affecting the proper operation and longevity of the adapter and peripheral electronics. Therefore, it is necessary to provide a further solution for how to release the electromagnetic interference signals.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an adapter pulse width modulation drive circuit to overcome the not enough that exists among the prior art.
In order to achieve the above object, the present invention provides an adapter pulse width modulation driving circuit, which includes: the pulse width modulator U1, a mos tube Q1, a release unit, a resistor R1 and a resistor R3;
the pulse width modulator U1 has a first pin1 and a second pin2, the first pin1 is connected to the gate of the mos transistor Q1 through a resistor R1, and the release unit includes: the first pin1 is further connected with the source of the mos tube Q1 through a resistor R2, a transistor Q2 and a resistor R3 in sequence, the base of the transistor Q2 is connected with the resistor R2, the collector is connected between the resistor R1 and the mos tube Q1, and the emitter is connected with the source of the mos tube Q1 through the resistor R3.
As the utility model discloses an improvement of adapter pulse width modulation drive circuit, second pin2 ground connection sets up.
As the utility model discloses an improvement of adapter pulse width modulation drive circuit, first pin1 output fixed frequency's pulse square wave signal.
As an improvement of the pulse width modulation driving circuit of the adapter of the present invention, when the pulse square wave signal is at a high level, the mos tube Q1 is driven by the resistor R1; when the pulse square wave signal is at a low level, the charges accumulated between the gate and the source of the mos transistor are discharged by the discharging unit.
As the utility model discloses an improvement of adapter pulse width modulation drive circuit, adapter pulse width modulation drive circuit still includes electric capacity C1, electric capacity C1 one end is connected to between resistance R1 and the mos pipe, the other end is connected to between triode Q2 and the resistance R3.
Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses an adapter pulse width modulation drive circuit is through providing the route of bleeding when mos pipe turn-offs, and when mos pipe turn-offs, triode Q2 switches on to the earthing terminal is released through triode Q2 to the voltage on the mos pipe drive signal, has reduced the electromagnetic energy, thereby can improve electromagnetic interference.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a circuit diagram of an embodiment of the present invention.
Detailed Description
The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that the functions, methods, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.
The utility model provides an adapter pulse width modulation drive circuit, it includes: the pulse width modulator U1, a mos tube Q1, a release unit, a resistor R1 and a resistor R3;
the pulse width modulator U1 has a first pin1 and a second pin2, the first pin1 is connected to the gate of the mos transistor Q1 through a resistor R1, and the release unit includes: the first pin1 is further connected with the source of the mos tube Q1 through a resistor R2, a transistor Q2 and a resistor R3 in sequence, the base of the transistor Q2 is connected with the resistor R2, the collector is connected between the resistor R1 and the mos tube Q1, and the emitter is connected with the source of the mos tube Q1 through the resistor R3.
When the pulse width modulator U1 normally works, the first pin1 outputs a pulse square wave signal with a fixed frequency, when the pulse square wave signal is at a high level, the MOS transistor Q1 is driven through the resistor R1, and when the pulse square wave signal is at a low level, a certain charge exists in the G-S of the MOS transistor Q1, and because of the existence of the parameter (Ciss) of the MOS transistor Q1, more and more potential energy is accumulated between the MOS transistors G-S.
The utility model discloses an increase triode Q2 and resistance R2 in the circuit, when pulse square wave signal is the low level, can discharge the electric charge and the potential energy of accumulation between mos pipe Q1G-S through triode Q2 and resistance R2 to can avoid the electromagnetic interference that accumulated electric charge and potential energy produced.
The technical solution of the present invention for the adapter pwm driving circuit is illustrated below with reference to a specific embodiment.
As shown in fig. 1, the adaptor pwm drive circuit of the present embodiment includes: the pulse width modulator U1, a mos tube Q1, a release unit, a resistor R1 and a resistor R3;
the pulse width modulator U1 has a first pin1 and a second pin2, the first pin1 is connected with the gate of the mos tube Q1 through a resistor R1, and the second pin2 is grounded. In one embodiment, an existing pulse width modulator model RT7740 may be used.
The release unit includes: the resistor R2 and the triode Q2. the first pin1 is further connected with the source electrode of the mos tube Q1 through a resistor R2, a triode Q2 and a resistor R3 in sequence, the base electrode of the triode Q2 is connected with the resistor R2, the collector electrode is connected between the resistor R1 and the mos tube Q1, and the emitter electrode is connected with the source electrode of the mos tube Q1 through the resistor R3.
The first pin1 outputs a pulse square wave signal of a fixed frequency. When the pulse square wave signal is high level, the mos tube Q1 is driven through the resistor R1; when the pulse square wave signal is at a low level, the charges accumulated between the gate and the source of the mos transistor are discharged by the discharging unit.
In addition, the adapter pulse width modulation driving circuit further comprises a capacitor C1, wherein one end of the capacitor C1 is connected between the resistor R1 and the mos tube, and the other end of the capacitor C1 is connected between the triode Q2 and the resistor R3.
To sum up, the utility model discloses an adapter pulse width modulation drive circuit is through providing the route of bleeding when the mos pipe is turn-offed, and when the mos pipe was turn-offed, triode Q2 switched on to the earthing terminal is released through triode Q2 to the voltage on the mos pipe drive signal, has reduced the electromagnetic energy, thereby can improve electromagnetic interference.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (5)

1. An adapter pulse width modulation drive circuit, comprising: the pulse width modulator U1, a mos tube Q1, a release unit, a resistor R1 and a resistor R3;
the pulse width modulator U1 has a first pin1 and a second pin2, the first pin1 is connected to the gate of the mos transistor Q1 through a resistor R1, and the release unit includes: the first pin1 is further connected with the source of the mos tube Q1 through a resistor R2, a transistor Q2 and a resistor R3 in sequence, the base of the transistor Q2 is connected with the resistor R2, the collector is connected between the resistor R1 and the mos tube Q1, and the emitter is connected with the source of the mos tube Q1 through the resistor R3.
2. The adapter pwm drive circuit according to claim 1, characterized in that the second pin2 is arranged to be connected to ground.
3. The adapter pwm drive line according to claim 1, characterized in that the first pin1 outputs a pulse square wave signal of fixed frequency.
4. The adapter pwm drive circuit according to claim 3, characterized in that when the pulse square wave signal is high level, mos tube Q1 is driven through resistor R1; when the pulse square wave signal is at a low level, the charges accumulated between the gate and the source of the mos transistor are discharged by the discharging unit.
5. The adapter pwm drive circuit according to claim 1, further comprising a capacitor C1, wherein the capacitor C1 is connected between the resistor R1 and the mos transistor at one end and between the transistor Q2 and the resistor R3 at the other end.
CN202020412253.0U 2020-03-27 2020-03-27 Adapter pulse width modulation drive circuit Active CN211656003U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202020412253.0U CN211656003U (en) 2020-03-27 2020-03-27 Adapter pulse width modulation drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202020412253.0U CN211656003U (en) 2020-03-27 2020-03-27 Adapter pulse width modulation drive circuit

Publications (1)

Publication Number Publication Date
CN211656003U true CN211656003U (en) 2020-10-09

Family

ID=72686900

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202020412253.0U Active CN211656003U (en) 2020-03-27 2020-03-27 Adapter pulse width modulation drive circuit

Country Status (1)

Country Link
CN (1) CN211656003U (en)

Similar Documents

Publication Publication Date Title
CN200976577Y (en) MOS tube driving circuit and television set having the same
CN101753000A (en) Power MOS pipe grid drive circuit and method for grid floating and level switching
CN106385165A (en) SiC MOSFET driving circuit with crosstalk suppression capability
CN1917369A (en) IGBT drive, and process method for driving signal
CN103532353A (en) Bootstrap power-supply MOSFET/IGBT (metal-oxide-semiconductor field effect transistor/insulated gate bipolar translator) driving circuit with high negative voltage
EP4080696A1 (en) Laser emission circuit and lidar
CN101640527A (en) IGBT driving circuit capable of realizing signal transmission by pulse modulation demodulation system
CN108874011A (en) A kind of grid modulation circuit of LDMOS solid-state power amplifier
CN114039589B (en) MOS tube driving circuit
CN203933357U (en) A kind of metal-oxide-semiconductor drive circuit for fast detecting equipment
CN211656003U (en) Adapter pulse width modulation drive circuit
CN101009486A (en) Narrow pulse driver of insulation bar power tube
CN201839100U (en) Power supply device based on impulse power amplifier
CN103078617B (en) The drive circuit of IGBT
CN101951034A (en) Power supply unit based on pulsed power amplifier
CN102355236A (en) High frequency high voltage pulse generator
CN106100433A (en) A kind of pulse power supply circuit being applicable to more modulation pattern
CN106603055A (en) Driving circuit of power switch tube, and switch power supply
CN115912976A (en) Intelligent inverter circuit
CN215580886U (en) Drive circuit, circuit board assembly, and electronic device
CN202231633U (en) High voltage pulse power supply
CN203537222U (en) Bootstrapping power supply MOSFET/IGBT driver circuit having high negative voltage
CN207869069U (en) A kind of CLASSD audio frequency power amplifiers pre-driver circuit and audio frequency power amplifier
CN109495092B (en) Power switch tube driving circuit and driving method
CN202276325U (en) Large power high voltage pulse power supply drive circuit

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20221101

Address after: No. 310, Shuangyuehu Road, Linyi Hi tech Industrial Development Zone, Shandong 276000

Patentee after: Haiyingte Power Technology Co.,Ltd.

Address before: Room 728, building 3, No. 588, Binhe Road, high tech Zone, Suzhou, Jiangsu 215000

Patentee before: Suzhou Jiande Electronic Technology Co.,Ltd.