CN108874011A - A kind of grid modulation circuit of LDMOS solid-state power amplifier - Google Patents
A kind of grid modulation circuit of LDMOS solid-state power amplifier Download PDFInfo
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- CN108874011A CN108874011A CN201811176273.6A CN201811176273A CN108874011A CN 108874011 A CN108874011 A CN 108874011A CN 201811176273 A CN201811176273 A CN 201811176273A CN 108874011 A CN108874011 A CN 108874011A
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- ldmos
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The present invention discloses a kind of grid modulation circuit of LDMOS solid-state power amplifier, including adjustable stabilized voltage supply, buffer, unlatching circuit, breaking circuit；The adjustable stabilized voltage supply is connect by the unlatching circuit with LDMOS pipe, the buffer is connect by the unlatching circuit, the breaking circuit with the LDMOS pipe, the adjustable stabilized voltage supply provides stable output voltage, and the buffer, the unlatching circuit, the breaking circuit connect the state switching for realizing the LDMOS solid-state power amplifier with the LDMOS pipe and adjust；The present invention realizes LDMOS tube grid modulation circuit using adjustable stabilized voltage supply, in the same direction/reverse buffer, unlatching circuit, breaking circuit, realizes that LDMOS tube grid voltage amplitude is adjustable, it is adjustable along the time before and after impulse waveform, circuit is simple, and it is convenient to realize, high reliablity.
Description
Technical field
The present invention relates to microwave solid-state power amplifier technical fields, and in particular to a kind of LDMOS solid-state power amplifier
Grid modulation circuit.
Background technique
LDMOS (lateral diffusion metal oxide semiconductor) is the microwave that a kind of market demand is huge, development prospect is wide
Power device.Since LDMOS has many advantages, such as High Linear, high-gain, high reliability, obtain widely answering in civil field
With.Currently, silicon microwave LDMOS has become the important selection of base station power technology.In addition, wideband frequency modulation transmitter, number
After using ldmos transistor, systematic entirety can obtain very the systems such as transmitter, the airborne transponder of terrestrial TV system
Big raising.
Second breakdown, safety operation area is not present compared with microwave power bipolar device in microwave power ldmos transistor
Greatly, and there is negative temperature coefficient, high linearity, burn-out resistance is strong, and switching speed is fast, and match circuit is simple, and drive loss is small
The characteristics of.LDMOS device obtains extensive favorable comment in the application of civil field.In military domain, LDMOS also one
The common power amplifying device of kind, is widely used in the products such as radar, electronic countermeasure, satellite communication.
When LDMOS solid-state amplifier works, input signal generally uses rf modulated signal, while adjusting to power amplifier
System controls the work of LDMOS pipe or cut-off by external TTL signal, and radio-frequency modulations and power amplifier modulation combine, can reduce power and put
The noise elimination of big device, improves the efficiency of amplifier.
The modulation of LDMOS solid-state amplifier is generally divided into two ways：Grid modulation and drain modulation.Grid modulation voltage
It is low, electric current is small, therefore circuit is simple, it is easy to accomplish.When drain modulation, the electric current that modulation switch flows through is big, and drain voltage is high,
ON-OFF control circuit is complicated, and the rising edge and failing edge of output of pulse signal are larger.It the characteristics of due to LDMOS device, generally adopts
Use grid modulation circuit.Existing grid modulation circuit is usually the grid that external TTL modulation pulse is applied directly to LDMOS device
Pole, when modulation pulse is high level, LDMOS device conducting, when modulation pulse is low level, LDMOS device cut-off.But due to
There are distribution capacity between LDMOS device grid and source electrode, need discharge time when modulating pulse and being low level, lead to LDMOS
The shutdown of device is there are trailing phenomenon, and power amplifier modulates the rear along larger of pulse output, it is difficult to which satisfaction needs pulse delay small with before
Afterwards along small occasion.
In view of the above drawbacks, creator of the present invention obtains the present invention by prolonged research and practice finally.
Summary of the invention
To solve above-mentioned technological deficiency, the technical solution adopted by the present invention is, provides a kind of LDMOS solid state power amplification
The grid modulation circuit of device, including adjustable stabilized voltage supply, buffer, unlatching circuit, breaking circuit；The adjustable stabilized voltage supply is logical
The unlatching circuit is crossed to connect with LDMOS pipe, the buffer by the unlatching circuit, the breaking circuit with it is described
The connection of LDMOS pipe, the adjustable stabilized voltage supply provide stable output voltage, the buffer, the unlatching circuit, the pass
Deenergizing connect the state switching for realizing the LDMOS solid-state power amplifier with the LDMOS pipe and adjusts.
Preferably, the adjustable stabilized voltage supply include first resistor, potentiometer, the first storage capacitor, the second storage capacitor,
Voltage-stablizer；The anode of first storage capacitor is connected to the first pin, third pin, the 4th pin of the voltage-stablizer, institute
State the negativing ending grounding of the first storage capacitor；The anode of second storage capacitor is connected to the 5th pin of the voltage-stablizer,
Six pins, the 7th pin, the negativing ending grounding of second storage capacitor；The second pin of the voltage-stablizer U1 is grounded；Described
One resistance and potentiometer series connection, the 8th of the public termination of the first resistor and the potentiometer voltage-stablizer draw
Foot, one end of the first resistor connect the 5th pin, the 6th pin and the 7th pin of the voltage-stablizer,
One end of the potentiometer is grounded.
Preferably, the input of the buffer terminates external TTL modulated signal, the output end of the buffer includes first
Output end and second output terminal, are connected to described second resistance one end after first output end output forward signal, and described the
The 7th resistance one end of the breaking circuit, two paths of signals opposite in phase are connected to after two output ends output reverse signal.
Preferably, the unlatching circuit include second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance,
Tube used for bottom pouring, the first zener diode, grid capacitance；The cathode of the 3rd resistor and first zener diode is in parallel, institute
The cathode for stating the first zener diode is connected with after the connection of described second resistance one end with the grid of the tube used for bottom pouring, and described first
The plus earth of zener diode；The source electrode of one end and the tube used for bottom pouring after the 4th resistance and the 5th resistor coupled in parallel
Connection, other end ground connection；6th resistance one terminates the source electrode of the tube used for bottom pouring, and the other end connects the grid capacitance, institute
State the other end ground connection of grid capacitance.
Preferably, the breaking circuit further includes the 8th resistance, the 9th resistance, the tenth resistance, shutdown pipe, the second pressure stabilizing two
Pole pipe, third zener diode；The cathode of 8th resistance and second zener diode is in parallel, second pressure stabilizing two
The cathode of pole pipe is connected after connecting with described 7th resistance one end with the grid of the shutdown pipe, second zener diode
Plus earth；The both ends of 9th resistance are connect with the source electrode of the shutdown drain electrode of pipe, the tube used for bottom pouring respectively, and described the
Ten resistance and the third zener diode are in parallel, and the cathode of the third zener diode connects the source electrode of the tube used for bottom pouring,
The plus earth of the third zener diode.
Preferably, the output voltage of the voltage-stablizer is adjusted by the potentiometer, adjustable range is by described first
The intrinsic standoff ratio of resistance and the potentiometer determines.
Preferably, the grid modulation rising edge of a pulse time of the LDMOS pipe is by adjusting the 6th resistance and described
The value of grid capacitance is adjusted；The grid modulation pulse falling edge time of the LDMOS pipe can be by adjusting the 6th resistance, institute
The value for stating the 9th resistance and the grid capacitance is adjusted.
Preferably, the radio frequency output signal of the LDMOS solid-state power amplifier is continuous wave or pulse signal.
Preferably, first pin is en foot, the second pin is gnd foot, the third pin and the described 4th
Pin is in foot, and the 5th pin and the 6th pin are vout foot, and the 7th pin is sen foot, and described the
Eight pins are adj foot.
Preferably, the buffer is set as in the same direction/reverse buffer.
Compared with the prior art the beneficial effects of the present invention are：The present invention using adjustable stabilized voltage supply, in the same direction/it is reversed slow
It rushes device, open circuit, breaking circuit, realize LDMOS tube grid modulation circuit, realize that LDMOS tube grid voltage amplitude is adjustable, arteries and veins
Rush adjustable along the time before and after waveform, circuit is simple, and it is convenient to realize, high reliablity.
Detailed description of the invention
Fig. 1 is the circuit diagram of the grid modulation circuit of LDMOS solid-state power amplifier of the present invention；
Fig. 2 is the timing diagram of the grid modulation circuit of LDMOS solid-state power amplifier of the present invention.
Specific embodiment
Below in conjunction with attached drawing, the forgoing and additional technical features and advantages are described in more detail.
Embodiment one
As shown in FIG. 1, FIG. 1 is the circuit diagrams of the grid modulation circuit of LDMOS solid-state power amplifier of the present invention；This
The grid modulation circuit for inventing the LDMOS solid-state power amplifier includes adjustable stabilized voltage supply, buffer, opens circuit, closes
Deenergizing.
Specifically, the adjustable stabilized voltage supply includes first resistor R1, potentiometer RP1, the first storage capacitor C1, the second storage
It can capacitor C2, voltage-stablizer U1.
The voltage-stablizer U1 draws including the first pin, second pin, third pin, the 4th pin, the 5th pin, the 6th
Foot, the 7th pin, the 8th pin, first pin are en foot, and the second pin is gnd foot, the third pin and institute
Stating the 4th pin is in foot, and the 5th pin and the 6th pin are vout foot, and the 7th pin is sen foot,
8th pin is adj foot.
The anode of the first storage capacitor C1 is connected to first pin of the voltage-stablizer U1, the third is drawn
Foot, the 4th pin, the negativing ending grounding of the first storage capacitor C1.
The anode of the second storage capacitor C2 is connected to the 5th pin of the voltage-stablizer U1, the described 6th draws
Foot, the 7th pin, the negativing ending grounding of the second storage capacitor C2.
The second pin of the voltage-stablizer U1 is grounded.
The first resistor R1 and potentiometer RP1 series connection, the first resistor R1 and the potentiometer RP1's is public
The adjustable side of the voltage-stablizer U1 is terminated, i.e., one end of described 8th pin, the first resistor R1 connects the voltage-stablizer U1
The 5th pin, the 6th pin and the 7th pin, the potentiometer RP1 one end ground connection.The voltage-stablizer
The output voltage values of U1 are adjusted by the potentiometer RP1.
Preferably, the input of the buffer U2 terminates external TTL modulated signal, the output end of the buffer U2 includes
First output end and second output terminal, to divide external TTL modulated signal to two paths of signals, the first output end output is positive
It is connected to the one end the second resistance R2 after signal, is connected to the 7th resistance R7 mono- after the second output terminal output reverse signal
End, two paths of signals opposite in phase.
The buffer U2 is preferably arranged in the same direction/reverse buffer.
Preferably, the unlatching circuit includes second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5,
Six resistance R6, tube used for bottom pouring V1, the first zener diode V2, grid capacitance C3.
The cathode of the 3rd resistor R3 and the first zener diode V2 are in parallel, the first zener diode V2's
Cathode is connected after connecting with the one end the second resistance R2 with the grid of the tube used for bottom pouring V1, the first zener diode V2's
Plus earth.The second resistance R2, the 3rd resistor R3 and the first zener diode V2 are the tube used for bottom pouring V1
Gate protection circuit prevents overtension from damaging the tube used for bottom pouring V1.
One end after the 4th resistance R4 and the 5th resistance R5 is in parallel is connect with the source electrode of the tube used for bottom pouring V1, separately
One end ground connection, so that the source electrode of the tube used for bottom pouring V1 is ground potential when guaranteeing the input of no external TTL signal.
The 6th resistance R6 mono- terminates the source electrode of the tube used for bottom pouring V1, and the other end connects the grid capacitance C3, described
The other end of grid capacitance C3 is grounded.The 6th resistance R6 and grid capacitance C3 forms charge circuit, and LDMOS is adjusted
The leading edge time of tube grid pulse.
Preferably, the breaking circuit includes the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, the tenth resistance
R10, shutdown pipe V3, the second zener diode V4, third zener diode V5.
The cathode of the 8th resistance R8 and the second zener diode V4 are in parallel, the second zener diode V4's
Cathode is connected after connecting with described 7th one end resistance R7 with the grid of the shutdown pipe V3, the second zener diode V4's
Plus earth.The 7th resistance R7, the 8th resistance R8 and the second zener diode V4 are the shutdown pipe V3
Gate protection circuit prevents overtension damage shutdown pipe.
The both ends of the 9th resistance R9 are connect with the source electrode of the drain electrode of the shutdown pipe V3, the tube used for bottom pouring V1 respectively,
For limiting the electric current passed through when turning off pipe and being connected.The tenth resistance R10 and third zener diode V5 is in parallel, institute
The cathode for stating third zener diode V5 connects the source electrode of the tube used for bottom pouring V1, and the anode of the third zener diode V5 connects
Ground, for filtering out the due to voltage spikes between the shutdown pipe V3 drain electrode and source electrode.
Embodiment two
Specifically, the concrete operating principle of the grid modulation circuit of LDMOS solid-state power amplifier of the present invention is, it is described steady
Depressor U1 output voltage can be adjusted by the first resistor R1 and the potentiometer RP1, choose suitable described first
The resistance value of resistance R1 and the potentiometer RP1, so that it may by the voltage-stablizer U1 output voltage values scope control 0.8V~
Between 5V.
When external TTL modulated signal is low level, first output end of the buffer U2 exports low level, institute
State second output terminal output high level, the tube used for bottom pouring V1 cut-off, the shutdown pipe V3 conducting, the LDMOS tube grid voltage
For 0V, the LDMOS pipe ends, thus guarantee that the LDMOS solid-state power amplifier is in off state, it is defeated without signal
Out, it ensure that reliable cut-off；When external TTL modulated signal is high level, first output end of the buffer U2 is defeated
High level out, the second output terminal export low level, the tube used for bottom pouring V1 conducting, the shutdown pipe V3 cut-off, the LDMOS
Tube grid voltage is the voltage value of voltage-stablizer U1 output, the LDMOS pipe conducting, to guarantee the LDMOS solid-state function
Rate amplifier is in magnifying state, and commencing signal output ensure that reliable conducting amplification.
Fig. 2 is the timing diagram of the grid modulation circuit of LDMOS solid-state power amplifier of the present invention, to the tool of each point in Fig. 2
Bulk wave shape is illustrated：
RFin is radio frequency input pulse signal, and the pulse-modulated signal that TTL is an externally input, H is the tube used for bottom pouring V1 grid
Pole pulse signal, L are the shutdown pipe V3 grid impulse signal, and M is the grid pulse modulation signal of LDMOS pipe.
Wherein, RFin signal is generally pulse-modulated signal, is nested in TTL signal, but sometimes for certain applications,
RFin signal peak pulse duration TTL signal is wide, or can be continuous wave signal, is amplified by the LDMOS solid-state power amplifier
The front and back for the grid impulse signal for being added in LDMOS pipe is depended on along the time along the time before and after signal output pulse afterwards.
In Fig. 2, the rising time t1 of the grid pulse modulation signal of LDMOS pipe is adjustable, when the tube used for bottom pouring V1 is led
After logical, the voltage-stablizer U1 out-put supply is by the 6th resistance R6 between the grid capacitance C3 and LDMOS pipe grid source
Capacitor charges, and when LDMOS tube grid voltage reaches cut-in voltage (VGS (TH)), LDMOS pipe is begun to turn on, conducting
Time is determined by the capacitance between the 6th resistance R6 and grid capacitance C3 and LDMOS pipe grid source, due to LDMOS pipe grid
Capacitance between source is substantially stationary, so passing through the i.e. adjustable institute of the value for adjusting the 6th resistance R6 and grid capacitance C3
State the size of rising time t1.
In Fig. 2, the failing edge time t2 of the grid pulse modulation signal of LDMOS pipe is adjustable, when the tube used for bottom pouring V1 is cut
After only, the shutdown pipe V3 is opened, and the charge on capacitor between the grid capacitance C3 and LDMOS pipe grid source passes through the described 6th
Resistance R6 and the 9th resistance R9 discharge over the ground, when LDMOS tube grid voltage is lower than cut-in voltage (VGS (TH)), LDMOS pipe
It begins to shut off, deadline is by the 6th resistance R6, the 9th resistance R9 and the grid capacitance C3 and LDMOS pipe grid
Capacitor between source determines, since the capacitor between LDMOS pipe grid source is fixed value, so by adjusting the 6th resistance R6, institute
The size of the failing edge time t2 is adjusted in the value for stating the 9th resistance R9 and grid capacitance C3.
The present invention realizes LDMOS pipe using adjustable stabilized voltage supply, in the same direction/reverse buffer, unlatching circuit, breaking circuit
Grid modulation circuit realizes that LDMOS tube grid voltage amplitude is adjustable, and adjustable along the time before and after impulse waveform, circuit is simple, realizes
It is convenient, high reliablity.
The foregoing is merely presently preferred embodiments of the present invention, is merely illustrative for the purpose of the present invention, and not restrictive
's.Those skilled in the art understand that in the spirit and scope defined by the claims in the present invention many changes can be carried out to it,
It modifies or even equivalent, but falls in protection scope of the present invention.
Claims (10)
1. a kind of grid modulation circuit of LDMOS solid-state power amplifier, which is characterized in that including adjustable stabilized voltage supply, buffering
Device opens circuit, breaking circuit；The adjustable stabilized voltage supply is connect by the unlatching circuit with LDMOS pipe, the buffer
It is connect by the unlatching circuit, the breaking circuit with the LDMOS pipe, the adjustable stabilized voltage supply provides stable output
Voltage, the buffer, the unlatching circuit, the breaking circuit are connect with the LDMOS pipe realizes the LDMOS solid-state function
The state of rate amplifier switches and adjusts.
2. the grid modulation circuit of LDMOS solid-state power amplifier as described in claim 1, which is characterized in that described adjustable
Regulated power supply includes first resistor, potentiometer, the first storage capacitor, the second storage capacitor, voltage-stablizer；First storage capacitor
Anode be connected to the first pin, third pin, the 4th pin of the voltage-stablizer, the negative terminal of first storage capacitor connects
Ground；The anode of second storage capacitor is connected to the 5th pin, the 6th pin, the 7th pin of the voltage-stablizer, and described
The negativing ending grounding of two storage capacitors；The second pin of the voltage-stablizer U1 is grounded；The first resistor and potentiometer series connection,
8th pin of the public termination of the first resistor and the potentiometer voltage-stablizer, one end connection of the first resistor
The 5th pin, the 6th pin and the 7th pin of the voltage-stablizer, one end ground connection of the potentiometer.
3. the grid modulation circuit of LDMOS solid-state power amplifier as claimed in claim 2, which is characterized in that the buffering
The input of device terminates external TTL modulated signal, and the output end of the buffer includes the first output end and second output terminal, described
It is connected to described second resistance one end after first output end output forward signal, connects after the second output terminal output reverse signal
It is connected to the 7th resistance one end of the breaking circuit, first output end and the second output terminal phase of output signal phase
Instead.
4. the grid modulation circuit of LDMOS solid-state power amplifier as claimed in claim 3, which is characterized in that the unlatching
Circuit includes second resistance, 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance, tube used for bottom pouring, the first zener diode, grid
Electrode capacitance；The cathode of the 3rd resistor and first zener diode is in parallel, the cathode of first zener diode and
It is connected after second resistance one end connection with the grid of the tube used for bottom pouring, the plus earth of first zener diode；Institute
One end after stating the 4th resistance and the 5th resistor coupled in parallel is connect with the source electrode of the tube used for bottom pouring, other end ground connection；Described
Six resistance one terminate the source electrode of the tube used for bottom pouring, and the other end connects the grid capacitance, the other end ground connection of the grid capacitance.
5. the grid modulation circuit of LDMOS solid-state power amplifier as claimed in claim 4, which is characterized in that the shutdown
Circuit further includes the 8th resistance, the 9th resistance, the tenth resistance, shutdown pipe, the second zener diode, third zener diode；Institute
The cathode for stating the 8th resistance and second zener diode is in parallel, the cathode of second zener diode and the 7th electricity
It is connected after the connection of resistance one end with the grid of the shutdown pipe, the plus earth of second zener diode；9th resistance
Both ends connect respectively with the source electrode of the shutdown drain electrode of pipe, the tube used for bottom pouring, the tenth resistance and the third pressure stabilizing
Diodes in parallel, the cathode of the third zener diode connect the source electrode of the tube used for bottom pouring, the third zener diode
Plus earth.
6. the grid modulation circuit of LDMOS solid-state power amplifier as claimed in claim 2, which is characterized in that the pressure stabilizing
The output voltage of device is adjusted by the potentiometer, adjustable range by the first resistor and the potentiometer intrinsic standoff ratio
It determines.
7. the grid modulation circuit of LDMOS solid-state power amplifier as claimed in claim 5, which is characterized in that the LDMOS
The grid modulation rising edge of a pulse time of pipe is adjusted by adjusting the value of the 6th resistance and the grid capacitance；It is described
The grid modulation pulse falling edge time of LDMOS pipe can be by adjusting the 6th resistance, the 9th resistance and the grid
The value of capacitor is adjusted.
8. the grid modulation circuit of LDMOS solid-state power amplifier as described in claim 1, which is characterized in that the LDMOS
The radio frequency output signal of solid-state power amplifier is continuous wave or pulse signal.
9. the grid modulation circuit of LDMOS solid-state power amplifier as claimed in claim 2, which is characterized in that described first
Pin is en foot, and the second pin is gnd foot, and the third pin and the 4th pin are in foot, and the described 5th draws
Foot and the 6th pin are vout foot, and the 7th pin is sen foot, and the 8th pin is adj foot.
10. the grid modulation circuit of LDMOS solid-state power amplifier as claimed in claim 2, which is characterized in that the buffering
Device is set as in the same direction/reverse buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811176273.6A CN108874011B (en) | 2018-10-09 | 2018-10-09 | Grid electrode modulation circuit of LDMOS solid-state power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811176273.6A CN108874011B (en) | 2018-10-09 | 2018-10-09 | Grid electrode modulation circuit of LDMOS solid-state power amplifier |
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| Publication Number | Publication Date |
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| CN108874011A true CN108874011A (en) | 2018-11-23 |
| CN108874011B CN108874011B (en) | 2020-02-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811176273.6A Active CN108874011B (en) | 2018-10-09 | 2018-10-09 | Grid electrode modulation circuit of LDMOS solid-state power amplifier |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110380709A (en) * | 2019-07-12 | 2019-10-25 | 浙江大学 | High speed grid pulse modulation circuit and radio-frequency power amplifier |
| CN112039499A (en) * | 2020-08-31 | 2020-12-04 | 中国电子科技集团公司第十四研究所 | Method for improving power amplifier output frequency spectrum purity |
| CN112631358A (en) * | 2020-12-28 | 2021-04-09 | 陕西烽火电子股份有限公司 | Grid voltage stabilizing circuit of LDMOS power amplifier tube |
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| CN101002379A (en) * | 2004-07-21 | 2007-07-18 | 电力波技术公司 | Auxiliary transistor gate bias control system and method |
| CN201063587Y (en) * | 2007-07-16 | 2008-05-21 | 浙江三维通信股份有限公司 | TDD RF high power LDMOS amplifier gate voltage control circuit |
| CN104539271A (en) * | 2014-11-14 | 2015-04-22 | 合肥雷科电子科技有限公司 | Grid modulator based on cathode positive and negative outputs and implementation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6661679B1 (en) * | 2002-10-28 | 2003-12-09 | System General Corporation | PWM controller having adaptive off-time modulation for power saving |
| CN1914787A (en) * | 2004-01-28 | 2007-02-14 | 株式会社瑞萨科技 | Switching power supply and semiconductor integrated circuit |
| CN101002379A (en) * | 2004-07-21 | 2007-07-18 | 电力波技术公司 | Auxiliary transistor gate bias control system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110380709A (en) * | 2019-07-12 | 2019-10-25 | 浙江大学 | High speed grid pulse modulation circuit and radio-frequency power amplifier |
| CN112039499A (en) * | 2020-08-31 | 2020-12-04 | 中国电子科技集团公司第十四研究所 | Method for improving power amplifier output frequency spectrum purity |
| CN112631358A (en) * | 2020-12-28 | 2021-04-09 | 陕西烽火电子股份有限公司 | Grid voltage stabilizing circuit of LDMOS power amplifier tube |
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| Publication number | Publication date |
|---|---|
| CN108874011B (en) | 2020-02-28 |
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