CN108874011B - Grid electrode modulation circuit of LDMOS solid-state power amplifier - Google Patents
Grid electrode modulation circuit of LDMOS solid-state power amplifier Download PDFInfo
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- CN108874011B CN108874011B CN201811176273.6A CN201811176273A CN108874011B CN 108874011 B CN108874011 B CN 108874011B CN 201811176273 A CN201811176273 A CN 201811176273A CN 108874011 B CN108874011 B CN 108874011B
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention discloses a grid electrode modulation circuit of an LDMOS solid-state power amplifier, which comprises an adjustable voltage-stabilized power supply, a buffer, a starting circuit and a turn-off circuit, wherein the buffer is connected with the starting circuit; the adjustable stabilized voltage supply is connected with the LDMOS tube through the starting circuit, the buffer is connected with the LDMOS tube through the starting circuit and the turn-off circuit, the adjustable stabilized voltage supply provides stable output voltage, and the buffer, the starting circuit and the turn-off circuit are connected with the LDMOS tube to realize state switching and adjustment of the LDMOS solid-state power amplifier; the LDMOS transistor grid electrode modulation circuit is realized by utilizing the adjustable voltage-stabilized power supply, the syntropy/reverse buffer, the turn-on circuit and the turn-off circuit, the amplitude of the LDMOS transistor grid electrode voltage is adjustable, the time of the front edge and the back edge of a pulse waveform is adjustable, the circuit is simple, the realization is convenient, and the reliability is high.
Description
Technical Field
The invention relates to the technical field of microwave solid-state power amplifiers, in particular to a grid electrode modulation circuit of an LDMOS solid-state power amplifier.
Background
The LDMOS (laterally diffused metal oxide semiconductor) is a microwave power device with huge market demand and wide development prospect. The LDMOS has the advantages of high linearity, high gain, high reliability and the like, and is widely applied to the civil field. Currently, silicon microwave LDMOS has become an important choice for base station power technology. In addition, after the LDMOS transistors are adopted by systems such as a broadband frequency modulation transmitter, a transmitter of a digital terrestrial television system, an airborne transponder and the like, the overall performance of the system is greatly improved.
Compared with a microwave power bipolar device, the microwave power LDMOS transistor has the characteristics of no secondary breakdown, large safe working area, negative temperature coefficient, high linearity, strong burnout resistance, high switching speed, simple matching circuit and small driving loss. The application of the LDMOS device in the civil field is widely favored. In the military field, the LDMOS is also a commonly used power amplifier device, and is widely applied to products such as radars, electronic countermeasure, satellite communication and the like.
When the LDMOS solid-state amplifier works, an input signal generally adopts a radio frequency modulation signal, a power amplifier is modulated at the same time, the LDMOS transistor is controlled to work or stop through an external TTL signal, and the radio frequency modulation and the power amplifier modulation are combined, so that the noise of the power amplifier can be reduced, and the efficiency of the amplifier is improved.
The modulation of LDMOS solid state amplifiers is generally divided into two ways: gate modulation and drain modulation. The grid modulation voltage is low, and the current is small, so the circuit is simple and easy to realize. When the drain electrode is modulated, the current flowing through a modulation switch is large, the drain electrode voltage is high, a switch control circuit is complex, and the rising edge and the falling edge of pulse signal output are large. Due to the characteristics of the LDMOS device, a gate modulation circuit is generally used. In the existing gate modulation circuit, an external TTL modulation pulse is generally directly applied to a gate of an LDMOS device, the LDMOS device is turned on when the modulation pulse is at a high level, and the LDMOS device is turned off when the modulation pulse is at a low level. However, due to the fact that distributed capacitors exist between the grid electrode and the source electrode of the LDMOS device, discharging time is needed when modulation pulses are low level, the LDMOS device is turned off to have a trailing phenomenon, the rear edge of the output of the modulation pulses of the power amplifier is large, and the situation that pulse delay is small and the situation that the front edge and the rear edge are small is difficult to meet.
In view of the above-mentioned drawbacks, the inventors of the present invention have finally obtained the present invention through a long period of research and practice.
Disclosure of Invention
In order to solve the technical defects, the invention adopts the technical scheme that the grid electrode modulation circuit of the LDMOS solid-state power amplifier comprises an adjustable voltage-stabilized power supply, a buffer, a starting circuit and a turn-off circuit; the adjustable stabilized voltage power supply is connected with the LDMOS tube through the starting circuit, the buffer is connected with the LDMOS tube through the starting circuit and the turn-off circuit, the adjustable stabilized voltage power supply provides stable output voltage, and the buffer is connected with the starting circuit and the turn-off circuit and the LDMOS tube to realize the state switching and adjustment of the LDMOS solid-state power amplifier.
Preferably, the adjustable voltage-stabilized power supply comprises a first resistor, a potentiometer, a first energy-storage capacitor, a second energy-storage capacitor and a voltage stabilizer; the positive end of the first energy storage capacitor is connected to the first pin, the third pin and the fourth pin of the voltage stabilizer, and the negative end of the first energy storage capacitor is grounded; the positive end of the second energy storage capacitor is connected to the fifth pin, the sixth pin and the seventh pin of the voltage stabilizer, and the negative end of the second energy storage capacitor is grounded; a second pin of the voltage regulator U1 is grounded; the first resistor is connected with the potentiometer in series, the common end of the first resistor and the potentiometer is connected with an eighth pin of the voltage stabilizer, one end of the first resistor is connected with the fifth pin, the sixth pin and the seventh pin of the voltage stabilizer, and one end of the potentiometer is grounded.
Preferably, the input terminal of the buffer is connected to an external TTL modulation signal, the output terminal of the buffer includes a first output terminal and a second output terminal, the first output terminal outputs a forward signal and then is connected to one end of the second resistor, the second output terminal outputs a reverse signal and then is connected to one end of the seventh resistor of the turn-off circuit, and the two paths of signals have opposite phases.
Preferably, the turn-on circuit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a turn-on tube, a first voltage regulator diode, and a gate capacitor; the third resistor is connected with the negative electrode of the first voltage stabilizing diode in parallel, the negative electrode of the first voltage stabilizing diode is connected with one end of the second resistor and then is connected with the grid electrode of the starting tube, and the positive electrode of the first voltage stabilizing diode is grounded; one end of the fourth resistor and one end of the fifth resistor after being connected in parallel are connected with the source electrode of the starting tube, and the other end of the fourth resistor and the fifth resistor are grounded; one end of the sixth resistor is connected with the source electrode of the starting tube, the other end of the sixth resistor is connected with the grid capacitor, and the other end of the grid capacitor is grounded.
Preferably, the turn-off circuit further includes an eighth resistor, a ninth resistor, a tenth resistor, a turn-off transistor, a second zener diode, and a third zener diode; the eighth resistor is connected with the negative electrode of the second voltage stabilizing diode in parallel, the negative electrode of the second voltage stabilizing diode is connected with one end of the seventh resistor and then is connected with the grid electrode of the turn-off tube, and the positive electrode of the second voltage stabilizing diode is grounded; the two ends of the ninth resistor are respectively connected with the drain electrode of the turn-off tube and the source electrode of the turn-on tube, the tenth resistor is connected with the third voltage stabilizing diode in parallel, the negative electrode of the third voltage stabilizing diode is connected with the source electrode of the turn-on tube, and the positive electrode of the third voltage stabilizing diode is grounded.
Preferably, the output voltage of the voltage stabilizer is adjusted by the potentiometer, and the adjustment range is determined by the voltage division ratio of the first resistor and the potentiometer.
Preferably, the rising edge time of the gate modulation pulse of the LDMOS transistor is adjusted by adjusting the values of the sixth resistor and the gate capacitor; the falling edge time of the grid electrode modulation pulse of the LDMOS transistor can be adjusted by adjusting the values of the sixth resistor, the ninth resistor and the grid electrode capacitor.
Preferably, the radio frequency output signal of the LDMOS solid-state power amplifier is a continuous wave or a pulse signal.
Preferably, the first pin is an en pin, the second pin is a gnd pin, the third pin and the fourth pin are in pins, the fifth pin and the sixth pin are vout pins, the seventh pin is a sen pin, and the eighth pin is an adj pin.
Preferably, the buffer is configured as a syntropic/inverse buffer.
Compared with the prior art, the invention has the beneficial effects that: the LDMOS transistor grid electrode modulation circuit is realized by utilizing the adjustable voltage-stabilized power supply, the syntropy/reverse buffer, the turn-on circuit and the turn-off circuit, the amplitude of the LDMOS transistor grid electrode voltage is adjustable, the time of the front edge and the back edge of a pulse waveform is adjustable, the circuit is simple, the realization is convenient, and the reliability is high.
Drawings
FIG. 1 is a circuit diagram of a gate modulation circuit of an LDMOS solid-state power amplifier according to the present invention;
fig. 2 is a timing diagram of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention.
Detailed Description
The above and further features and advantages of the present invention are described in more detail below with reference to the accompanying drawings.
Example one
As shown in fig. 1, fig. 1 is a circuit diagram of a gate modulation circuit of an LDMOS solid-state power amplifier according to the present invention; the grid electrode modulation circuit of the LDMOS solid-state power amplifier comprises an adjustable voltage-stabilized power supply, a buffer, a starting circuit and a turn-off circuit.
Specifically, the adjustable voltage-stabilized power supply comprises a first resistor R1, a potentiometer RP1, a first energy-storage capacitor C1, a second energy-storage capacitor C2 and a voltage stabilizer U1.
The voltage stabilizer U1 includes first pin, second pin, third pin, fourth pin, fifth pin, sixth pin, seventh pin, eighth pin, first pin is the en pin, the second pin is the gnd pin, the third pin with the fourth pin is the in pin, the fifth pin with the sixth pin is the vout pin, the seventh pin is the sen pin, the eighth pin is the adj pin.
The positive end of the first energy storage capacitor C1 is connected to the first pin, the third pin and the fourth pin of the voltage stabilizer U1, and the negative end of the first energy storage capacitor C1 is grounded.
The positive end of the second energy-storing capacitor C2 is connected to the fifth pin, the sixth pin and the seventh pin of the voltage stabilizer U1, and the negative end of the second energy-storing capacitor C2 is grounded.
The second pin of the regulator U1 is connected to ground.
The first resistor R1 and the potentiometer RP1 are connected in series, the common end of the first resistor R1 and the potentiometer RP1 is connected with the adjusting end of the voltage stabilizer U1, namely the eighth pin, one end of the first resistor R1 is connected with the fifth pin, the sixth pin and the seventh pin of the voltage stabilizer U1, and one end of the potentiometer RP1 is grounded. The output voltage value of the voltage stabilizer U1 is adjusted through the potentiometer RP 1.
Preferably, the input end of the buffer U2 is connected to an external TTL modulated signal, the output end of the buffer U2 includes a first output end and a second output end, so as to divide the external TTL modulated signal into two paths of signals, the first output end outputs a forward signal and then is connected to one end of the second resistor R2, the second output end outputs a reverse signal and then is connected to one end of the seventh resistor R7, and the two paths of signals have opposite phases.
The buffer U2 is preferably configured as a co/reverse buffer.
Preferably, the turn-on circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a turn-on transistor V1, a first zener diode V2, and a gate capacitor C3.
The third resistor R3 is connected in parallel with the cathode of the first voltage-stabilizing diode V2, the cathode of the first voltage-stabilizing diode V2 is connected with one end of the second resistor R2 and then connected with the gate of the starting tube V1, and the anode of the first voltage-stabilizing diode V2 is grounded. The second resistor R2, the third resistor R3 and the first zener diode V2 are gate protection circuits of the turn-on transistor V1, and prevent the turn-on transistor V1 from being damaged by overhigh voltage.
One end of the fourth resistor R4 connected with the fifth resistor R5 in parallel is connected with the source electrode of the starting tube V1, and the other end of the fourth resistor R4 connected with the fifth resistor R5 is grounded, so that the source electrode of the starting tube V1 is at the ground potential when no external TTL signal is input.
One end of the sixth resistor R6 is connected to the source of the turn-on transistor V1, the other end is connected to the gate capacitor C3, and the other end of the gate capacitor C3 is grounded. The sixth resistor R6 and the gate capacitor C3 form a charging loop, and the leading edge time of the gate pulse of the LDMOS transistor can be adjusted.
Preferably, the turn-off circuit includes the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the turn-off transistor V3, the second zener diode V4, and the third zener diode V5.
The eighth resistor R8 is connected in parallel with the cathode of the second zener diode V4, the cathode of the second zener diode V4 is connected with one end of the seventh resistor R7 and then connected with the gate of the turn-off tube V3, and the anode of the second zener diode V4 is grounded. The seventh resistor R7, the eighth resistor R8 and the second zener diode V4 are gate protection circuits of the shut-off tube V3, and prevent the shut-off tube from being damaged by overhigh voltage.
Two ends of the ninth resistor R9 are respectively connected to the drain of the turn-off transistor V3 and the source of the turn-on transistor V1 for limiting the current passing through the turn-off transistor when it is turned on. The tenth resistor R10 is connected in parallel with the third zener diode V5, a negative electrode of the third zener diode V5 is connected to the source of the turn-on transistor V1, and a positive electrode of the third zener diode V5 is grounded, so as to filter a voltage spike between the drain and the source of the turn-off transistor V3.
Example two
Specifically, the specific working principle of the gate modulation circuit of the LDMOS solid-state power amplifier is that the output voltage of the voltage stabilizer U1 can be adjusted through the first resistor R1 and the potentiometer RP1, and the output voltage value range of the voltage stabilizer U1 can be controlled between 0.8V and 5V by selecting appropriate resistance values of the first resistor R1 and the potentiometer RP 1.
When an external TTL modulation signal is at a low level, the first output end of the buffer U2 outputs a low level, the second output end outputs a high level, the opening tube V1 is cut off, the closing tube V3 is switched on, the gate voltage of the LDMOS tube is 0V, and the LDMOS tube is cut off, so that the LDMOS solid-state power amplifier is ensured to be in a cut-off state, no signal is output, and reliable cut-off is ensured; when an external TTL modulation signal is at a high level, the first output end of the buffer U2 outputs a high level, the second output end outputs a low level, the opening tube V1 is connected, the closing tube V3 is cut off, the gate voltage of the LDMOS tube is the voltage value output by the voltage stabilizer U1, and the LDMOS tube is connected, so that the LDMOS solid-state power amplifier is ensured to be in an amplification state, signal output is started, and reliable conduction and amplification are ensured.
Fig. 2 is a timing diagram of the gate modulation circuit of the LDMOS solid-state power amplifier of the present invention, illustrating specific waveforms of points in fig. 2:
RFin is a radio frequency input pulse signal, TTL is an externally input pulse modulation signal, H is a gate pulse signal of the opening tube V1, L is a gate pulse signal of the closing tube V3, and M is a gate pulse modulation signal of the LDMOS tube.
The RFin signal is generally a pulse modulation signal and is nested in the TTL signal, but sometimes for some applications, the pulse width of the RFin signal is wider than that of the TTL signal, or the RFin signal can be a continuous wave signal, and the time of the front edge and the back edge of the output pulse of the signal amplified by the LDMOS solid-state power amplifier depends on the time of the front edge and the back edge of a gate pulse signal applied to the LDMOS transistor.
In fig. 2, the rising edge time t1 of the gate pulse modulation signal of the LDMOS transistor is adjustable, after the turn-on transistor V1 is turned on, the output power of the voltage regulator U1 charges the capacitance between the gate capacitor C3 and the gate source of the LDMOS transistor through the sixth resistor R6, when the gate voltage of the LDMOS transistor reaches the turn-on voltage (vgs (th)), the LDMOS transistor starts to turn on, the turn-on time is determined by the sixth resistor R6, the gate capacitor C3, and the capacitance between the gate source of the LDMOS transistor, and since the capacitance between the gate sources of the LDMOS transistor is substantially fixed, the value of the rising edge time t1 can be adjusted by adjusting the values of the sixth resistor R6 and the gate capacitor C3.
In fig. 2, the falling edge time t2 of the gate pulse modulation signal of the LDMOS transistor is adjustable, when the turn-on transistor V1 is turned off, the turn-off transistor V3 is turned on, the charge on the capacitor between the gate capacitor C3 and the LDMOS transistor gate source is discharged to ground through the sixth resistor R6 and the ninth resistor R9, and the LDMOS transistor gate voltage is lower than the turn-on voltage (vgs (th)), the LDMOS transistor starts to turn off, and the turn-off time is determined by the sixth resistor R6, the ninth resistor R9, the gate capacitor C3 and the capacitor between the LDMOS transistor gate source, and since the capacitor between the LDMOS transistor gate sources is a fixed value, the size of the falling edge time t2 can be adjusted by adjusting the values of the sixth resistor R6, the ninth resistor R9 and the gate capacitor C3.
The LDMOS transistor grid electrode modulation circuit is realized by utilizing the adjustable voltage-stabilized power supply, the syntropy/reverse buffer, the turn-on circuit and the turn-off circuit, the amplitude of the LDMOS transistor grid electrode voltage is adjustable, the time of the front edge and the back edge of a pulse waveform is adjustable, the circuit is simple, the realization is convenient, and the reliability is high.
The foregoing is merely a preferred embodiment of the invention, which is intended to be illustrative and not limiting. It will be understood by those skilled in the art that various changes, modifications and equivalents may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (6)
1. A grid electrode modulation circuit of an LDMOS solid-state power amplifier is characterized by comprising an adjustable voltage-stabilized power supply, a buffer, a starting circuit and a turn-off circuit; the adjustable stabilized voltage supply is connected with the LDMOS tube through the starting circuit, the buffer is connected with the LDMOS tube through the starting circuit and the turn-off circuit, the adjustable stabilized voltage supply provides stable output voltage, and the buffer, the starting circuit and the turn-off circuit are connected with the LDMOS tube to realize state switching and adjustment of the LDMOS solid-state power amplifier;
the adjustable voltage-stabilized power supply comprises a first resistor, a potentiometer, a first energy-storage capacitor, a second energy-storage capacitor and a voltage stabilizer; the positive end of the first energy storage capacitor is connected to the first pin, the third pin and the fourth pin of the voltage stabilizer, and the negative end of the first energy storage capacitor is grounded; the positive end of the second energy storage capacitor is connected to the fifth pin, the sixth pin and the seventh pin of the voltage stabilizer, and the negative end of the second energy storage capacitor is grounded; a second pin of the voltage stabilizer is grounded; the first resistor is connected with the potentiometer in series, the common end of the first resistor and the potentiometer is connected with an eighth pin of the voltage stabilizer, the other end of the first resistor is connected with the fifth pin, the sixth pin and the seventh pin of the voltage stabilizer, and the other end of the potentiometer is grounded;
the first pin is an en pin, the second pin is a gnd pin, the third pin and the fourth pin are in pins, the fifth pin and the sixth pin are vout pins, the seventh pin is a sen pin, and the eighth pin is an adj pin; the input end of the buffer is connected with an external TTL modulation signal, the output end of the buffer comprises a first output end and a second output end, the first output end is connected to the first end of the second resistor after outputting a forward signal, the second output end is connected to the first end of the seventh resistor of the turn-off circuit after outputting a reverse signal, and the phases of the output signals of the first output end and the second output end are opposite;
the starting circuit comprises a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a starting tube, a first voltage stabilizing diode and a grid capacitor; the third resistor is connected with the first voltage stabilizing diode in parallel, the negative electrode of the first voltage stabilizing diode is connected with the second end of the second resistor and then connected with the grid electrode of the starting tube, and the positive electrode of the first voltage stabilizing diode is grounded; one end of the fourth resistor and one end of the fifth resistor after being connected in parallel are connected with the source electrode of the starting tube, and the other end of the fourth resistor and the fifth resistor are grounded; one end of the sixth resistor is connected with the source electrode of the starting tube, the other end of the sixth resistor is connected with the grid capacitor, and the other end of the grid capacitor is grounded; and the drain electrode of the starting tube is connected with the fifth pin, the sixth pin and the seventh pin of the voltage stabilizer.
2. The gate modulation circuit of an LDMOS solid state power amplifier of claim 1 wherein the turn-off circuit further comprises an eighth resistor, a ninth resistor, a tenth resistor, a turn-off transistor, a second zener diode, a third zener diode; the eighth resistor is connected in parallel with the second voltage stabilizing diode, the negative electrode of the second voltage stabilizing diode is connected with the second end of the seventh resistor and then connected with the grid electrode of the turn-off tube, and the positive electrode of the second voltage stabilizing diode is grounded; the two ends of the ninth resistor are respectively connected with the drain electrode of the turn-off tube and the source electrode of the turn-on tube, the tenth resistor is connected with the third voltage stabilizing diode in parallel, the negative electrode of the third voltage stabilizing diode is connected with the source electrode of the turn-on tube, and the positive electrode of the third voltage stabilizing diode is grounded.
3. The gate modulation circuit of an LDMOS solid state power amplifier of claim 1, wherein the output voltage of the voltage regulator is adjusted by the potentiometer, the adjustment range being determined by the voltage division ratio of the first resistor and the potentiometer.
4. The gate modulation circuit of an LDMOS solid state power amplifier of claim 2, wherein the gate modulation pulse rising edge time of the LDMOS transistor is adjusted by adjusting the values of the sixth resistor and the gate capacitor; the falling edge time of the grid electrode modulation pulse of the LDMOS transistor can be adjusted by adjusting the values of the sixth resistor, the ninth resistor and the grid electrode capacitor.
5. The gate modulation circuit of an LDMOS solid state power amplifier of claim 1, wherein the radio frequency output signal of the LDMOS solid state power amplifier is a continuous wave or a pulsed signal.
6. The gate modulation circuit of an LDMOS solid state power amplifier of claim 1, wherein the buffer is provided as a in/reverse buffer.
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| CN110380709B (en) * | 2019-07-12 | 2021-08-27 | 浙江大学 | High-speed grid pulse modulation circuit and radio frequency power amplifier |
| CN112039499A (en) * | 2020-08-31 | 2020-12-04 | 中国电子科技集团公司第十四研究所 | Method for improving power amplifier output frequency spectrum purity |
| CN112631358A (en) * | 2020-12-28 | 2021-04-09 | 陕西烽火电子股份有限公司 | Grid voltage stabilizing circuit of LDMOS power amplifier tube |
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| TW200525869A (en) * | 2004-01-28 | 2005-08-01 | Renesas Tech Corp | Switching power supply and semiconductor IC |
| CN101002379A (en) * | 2004-07-21 | 2007-07-18 | 电力波技术公司 | Auxiliary transistor gate bias control system and method |
| CN201063587Y (en) * | 2007-07-16 | 2008-05-21 | 浙江三维通信股份有限公司 | TDD RF high power LDMOS amplifier gate voltage control circuit |
| CN104539271A (en) * | 2014-11-14 | 2015-04-22 | 合肥雷科电子科技有限公司 | Grid modulator based on cathode positive and negative outputs and implementation method thereof |
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