CN211427183U - Reference current compensation circuit applied to high-precision analog-to-digital converter - Google Patents
Reference current compensation circuit applied to high-precision analog-to-digital converter Download PDFInfo
- Publication number
- CN211427183U CN211427183U CN201922288994.2U CN201922288994U CN211427183U CN 211427183 U CN211427183 U CN 211427183U CN 201922288994 U CN201922288994 U CN 201922288994U CN 211427183 U CN211427183 U CN 211427183U
- Authority
- CN
- China
- Prior art keywords
- type mos
- mos tube
- circuit
- drain electrode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The utility model belongs to the technical field of reference current compensation circuits, in particular to a reference current compensation circuit applied to a high-precision analog-to-digital converter; the circuit comprises a bias current generating circuit, a source follower, a resistance feedback circuit, a first-stage operational amplifier circuit, a level shift circuit, an output-stage circuit and a feedback bias-stage circuit which are sequentially and electrically connected. The current compensation circuit generates bias current by using voltage bias, solves the problem that the fixed voltage difference of a source follower changes along with the temperature, isolates an input signal through the source follower, and solves the problem that the change of the input current of a closed-loop operational amplifier affects a front-end voltage-dividing resistance module; the output stage circuit has the capacity of absorbing and providing current, and solves the problem of overlarge current caused by the compensation module. The circuit compensates the base current to keep the static current of the reference constant, so that the reference output voltage is not influenced by the input signal of the analog-to-digital converter, and the performance of the data converter is improved.
Description
Technical Field
The utility model belongs to the technical field of the reference current compensating circuit, especially, relate to a be applied to high accuracy analog to digital converter's reference current compensating circuit.
Background
With the gradual increase of national requirements and requirements for the localization military aerospace chip, the analog-digital converter chip applied to the military field is used as one of the core circuits, and the localization of the core technology is imperative. Because many chips in the military industry field are positive and negative high-voltage input, from the viewpoint of power consumption and performance, the chips must be converted into positive low voltage for being processed by a back-end analog-digital converter, however, the high-voltage input is converted into a low-voltage domain in a resistance voltage division manner, so that a reference voltage faces a static load which linearly changes along with the input, and the integral nonlinearity of the ADC is caused.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problems, the present invention provides a reference current compensation circuit applied to a high-precision analog-to-digital converter, which comprises a bias current generating circuit, a source follower, a resistance feedback circuit, a first-stage operational amplifier circuit, a level shift circuit, an output stage circuit and a feedback bias stage circuit, which are electrically connected in sequence; the device also comprises a bias circuit, a reference voltage source, a power supply voltage source and an analog-to-digital converter;
the bias circuit comprises a first bias circuit, a second bias circuit, a third bias circuit and a fourth bias circuit; the first bias circuit is respectively connected with the first-stage operational amplifier circuit and the level shift circuit; the second bias circuit, the third bias circuit and the fourth bias circuit are all connected with the level shift circuit; the reference voltage source is respectively connected with the bias current generating circuit and the feedback bias stage circuit; the power supply voltage source is respectively connected with the source follower, the level shift circuit, the output stage circuit and the feedback bias stage circuit; the analog-to-digital converter is connected with the source follower.
As a further explanation of the above scheme, the bias current generating circuit includes a first resistor, a second resistor, a first N-type MOS transistor and a first P-type MOS transistor;
the source follower comprises a second N-type MOS tube, a second P-type MOS tube and a third P-type MOS tube;
the resistance feedback circuit comprises a third resistor and a fourth resistor;
the first-stage operational amplifier circuit comprises a third N-type MOS tube, a fourth P-type MOS tube, a fifth P-type MOS tube and a sixth P-type MOS tube;
the level shift circuit comprises a fifth N-type MOS tube, a sixth N-type MOS tube, a seventh P-type MOS tube and an eighth P-type MOS tube;
the output stage circuit comprises a seventh N-type MOS tube, a ninth P-type MOS tube, a first capacitor and a second capacitor;
the feedback bias stage circuit comprises an eighth N-type MOS tube, a tenth P-type MOS tube, a third capacitor and a fourth capacitor;
one end of the first resistor is connected with the grid electrode of the first P-type MOS tube;
one end of the second resistor is connected with the grid electrode of the first P-type MOS tube, and the other end of the second resistor is connected with the ground;
the drain electrode of the first P-type MOS tube is connected with the drain electrode of the first N-type MOS tube;
the drain electrode of the first N-type MOS tube is connected with the grid electrode, and the source electrode of the first N-type MOS tube is connected with the ground;
the grid electrode of the second N-type MOS tube is connected with the grid electrode of the first N-type MOS tube, the source electrode of the second N-type MOS tube is connected with the ground, and the drain electrode of the second N-type MOS tube is connected with the drain electrode of the third P-type MOS tube;
the grid electrode of the third P-type MOS tube is connected with the input of the analog-to-digital converter, and the source electrode of the third P-type MOS tube is connected with the drain electrode of the second P-type MOS tube;
the grid electrode of the second P-type MOS tube is connected with the drain electrode of the tenth P-type MOS tube MP10, and the drain electrode is connected with one end of the third resistor;
the other end of the third resistor is connected with one end of the fourth resistor and is connected with a grid electrode of the fifth P-type MOS tube;
the other end of the fourth resistor is connected with one end of the fifth resistor and is connected with the drain electrode of the ninth P-type MOS tube;
the source electrode of the fifth P-type MOS tube is connected with the drain electrode of the fourth P-type MOS tube, and the drain electrode of the fifth P-type MOS tube is connected with the drain electrode of the third N-type MOS tube;
the grid electrode of the fourth P-type MOS tube is connected with a first bias voltage circuit;
the source electrode of the sixth P-type MOS tube is connected with the drain electrode of the fourth P-type MOS tube, and the drain electrode of the sixth P-type MOS tube is connected with the drain electrode of the fourth N-type MOS tube;
the drain electrode of the third N-type MOS tube is connected with the grid electrode, and the source electrode of the third N-type MOS tube is connected with the ground;
the grid electrode of the fourth N-type MOS tube is connected with the grid electrode of the third N-type MOS tube, and the source electrode of the fourth N-type MOS tube is connected with the ground;
the grid electrode of the fifth N-type MOS tube is connected with the fourth bias voltage circuit, the source electrode of the fifth N-type MOS tube is connected with the ground, and the drain electrode of the fifth N-type MOS tube is connected with the drain electrode of the fourth N-type MOS tube;
the grid electrode of the sixth N-type MOS tube is connected with bias voltage, the source electrode of the sixth N-type MOS tube is connected with the drain electrode of the fifth N-type MOS tube, and the drain electrode of the sixth N-type MOS tube is connected with the drain electrode of the seventh P-type MOS tube;
the grid electrode of the seventh P-type MOS tube is connected with a first bias voltage circuit;
the source electrode of the eighth P-type MOS tube is connected with the drain electrode of the sixth N-type MOS tube, the grid electrode of the eighth P-type MOS tube is connected with the second bias voltage circuit, and the drain electrode of the eighth P-type MOS tube is connected with the source electrode of the sixth N-type MOS tube;
the grid electrode of the ninth P-type MOS tube is connected with the drain electrode of the seventh P-type MOS tube, and the drain electrode of the seventh N-type MOS tube is connected;
the grid electrode of the seventh N-type MOS tube is connected with the drain electrode of the fifth N-type MOS tube, and the source electrode of the seventh N-type MOS tube is connected with the ground;
the grid electrode of the tenth P-type MOS tube is connected with the grid electrode of the ninth P-type MOS tube, and the drain electrode of the tenth P-type MOS tube is connected with the drain electrode of the eighth N-type MOS tube;
the grid electrode of the eighth N-type MOS tube is connected with the grid electrode of the seventh N-type MOS tube, and the source electrode of the eighth N-type MOS tube is connected with the ground;
one end of the first capacitor is connected with the drain electrode of the seventh P-type MOS tube, and the other end of the first capacitor is connected with the drain electrode of the ninth P-type MOS tube;
one end of the second capacitor is connected with the drain electrode of the fifth N-type MOS tube, and the other end of the second capacitor is connected with the drain electrode of the seventh N-type MOS tube;
one end of the third capacitor is connected with the drain electrode of the seventh P-type MOS tube, and the other end of the third capacitor is connected with the drain electrode of the tenth P-type MOS tube;
and one end of the fourth capacitor is connected with the drain electrode of the fifth N-type MOS tube, and the other end of the fourth capacitor is connected with the drain electrode of the eighth N-type MOS tube.
As a further explanation of the above scheme, the circuit further comprises an input resistance voltage division circuit, which comprises a sixth resistor, a seventh resistor, and an eighth resistor; one end of the sixth resistor is connected with one end of the seventh resistor and one end of the eighth resistor respectively, the other end of the seventh resistor is connected with the ground, and the other end of the eighth resistor is connected with the input end of the analog-to-digital converter.
The utility model has the advantages that: the current compensation circuit generates bias current by using voltage bias, and solves the problem that the fixed voltage difference of a source follower changes along with the temperature; the current compensation circuit isolates an input signal through a P-type MOS tube source follower, and solves the problem that the change of the input current of the closed-loop operational amplifier affects a front-end voltage-dividing resistance module; the output stage circuit has the capacity of absorbing and providing current, solves the problem of overlarge current caused by a compensation circuit, and ensures that the static current of the reference is kept constant by compensating the base current, so that the reference output voltage is not influenced by the input signal of the analog-to-digital converter, and the performance of the analog-to-digital converter is improved.
Drawings
FIG. 1 is a reference current compensation circuit for a high precision analog to digital converter;
fig. 2 (a): an input resistance voltage-dividing circuit;
fig. 2 (b): and (5) a reference voltage equivalent model schematic diagram.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the drawings and specific embodiments of the specification.
Example 1:
the embodiment provides a reference current compensation circuit applied to a high-precision analog-to-digital converter, which comprises a bias current generating circuit 1, a source follower 2, a resistance feedback circuit 3, a first-stage operational amplifier circuit 4, a level shift circuit 5, an output-stage circuit 6 and a feedback bias-stage circuit 7 which are electrically connected in sequence; the device also comprises a bias circuit VB, a reference voltage source VREF, a power supply voltage source VDD and an analog-to-digital converter; the bias circuit comprises a first bias circuit VB1, a second bias circuit VB2, a third bias circuit VB3 and a fourth bias circuit VB4, the first bias circuit is respectively connected with the first-stage operational amplifier circuit 4 and the level shift circuit 5, and the second bias circuit VB2, the third bias circuit VB3 and the fourth bias circuit VB4 are electrically connected with the level shift circuit 5; the reference voltage source VREF is respectively and electrically connected with the bias current generating circuit 1 and the feedback bias stage circuit 7; the power supply voltage source is respectively and electrically connected with the source follower 2, the level shift circuit 5, the output stage circuit 6 and the feedback bias stage circuit 7; the analog-to-digital converter is electrically connected with the source follower 2.
Example 2:
with reference to fig. 2(a), based on embodiment 1, the bias current generating circuit 1 includes a first resistor R1, a second resistor R2, a first N-type MOS transistor MN1, and a first P-type MOS transistor MP 1; the source follower 2 comprises a second N-type MOS transistor MN2, a second P-type MOS transistor (MP2) and a third P-type MOS transistor MP 3; the feedback resistance circuit 3 comprises a third resistor R3 and a fourth resistor R4; the first-stage operational amplifier circuit 4 comprises a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5 and a sixth P-type MOS transistor MP 6; the level shift circuit 5 comprises a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a seventh P-type MOS transistor MP7 and an eighth P-type MOS transistor MP 8; the output stage circuit 6 comprises a seventh N-type MOS transistor MN7, a ninth P-type MOS transistor MP9, a first capacitor C1 and a second capacitor C2; the feedback bias stage circuit 7 includes an eighth N-type MOS transistor (MN8), a tenth P-type MOS transistor MP10, a third capacitor C3, and a fourth capacitor C4.
One end of the first resistor R1 is connected with a reference voltage REF, and the other end is connected with the grid electrode of the first P-type MOS tube MP 1; one end of the second resistor R2 is connected with the grid of the first P-type MOS tube MP1, and the other end is connected with the ground; the source electrode of the first P-type MOS tube MP1 is connected with a reference voltage VREF, and the drain electrode of the first P-type MOS tube MP1 is connected with the drain electrode of the first N-type MOS tube MN 1; the drain electrode of the first N-type MOS transistor MN1 is connected with the grid electrode, and the source electrode is connected with the ground; the grid electrode of the second N-type MOS tube MN2 is connected with the grid electrode of the first N-type MOS tube MN1, the source electrode is connected with the ground, and the drain electrode is connected with the drain electrode of the third P-type MOS tube MP 3; the grid electrode of the third P-type MOS tube MP3 is connected with the input of the analog-to-digital converter, and the source electrode is connected with the drain electrode of the second P-type MOS tube MP 2; the source electrode of the second P-type MOS transistor MP2 is connected with the power supply voltage, the grid electrode of the second P-type MOS transistor MP2 is connected with the drain electrode of the tenth P-type MOS transistor MP10, and the drain electrode of the second P-type MOS transistor MP2 is connected with one end of a third resistor R3; the other end of the third resistor R3 is connected with one end of the fourth resistor R4 and is connected with the grid electrode of the fifth P-type MOS transistor MP 5; the other end of the fourth resistor R4 is connected with one end of the fifth resistor R5 and is connected with the drain electrode of the ninth P-type MOS transistor MP 9; the other end of the fifth resistor R5 is connected with the reference voltage VREF; the source electrode of the fifth P-type MOS tube MP5 is connected with the drain electrode of the fourth P-type MOS tube MP4, and the drain electrode is connected with the drain electrode of the MN3 of the third N-type MOS tube; the grid electrode of the fourth P-type MOS transistor MP4 is connected with a bias voltage VB1, and the source electrode of the fourth P-type MOS transistor MP4 is connected with a power supply voltage; the source electrode of the sixth P-type MOS transistor MP6 is connected with the drain electrode of the fourth P-type MOS transistor MP4, and the drain electrode is connected with the drain electrode of the fourth N-type MOS transistor MN 4; the drain electrode of the third N-type MOS transistor MN3 is connected with the grid electrode, and the source electrode is connected with the ground; the grid electrode of the fourth N-type MOS transistor MN4 is connected with the grid electrode of the third N-type MOS transistor MN3, and the source electrode of the fourth N-type MOS transistor MN4 is connected with the ground; the grid electrode of the fifth N-type MOS tube MN5 is connected with the fourth bias voltage circuit VB4, the source electrode is connected with the ground, and the drain electrode is connected with the drain electrode of the fourth N-type MOS tube MN 4; the grid electrode of the sixth N-type MOS transistor MN6 is connected with the bias voltage VB3, the source electrode of the sixth N-type MOS transistor MN5 is connected with the drain electrode of the fifth N-type MOS transistor MN7, and the drain electrode of the sixth P-type MOS transistor MP7 is connected with the drain electrode of the seventh P-type MOS transistor MP 7; the grid electrode of the seventh P-type MOS tube MP7 is connected with the first bias voltage circuit VB1, and the source electrode is connected with the power supply voltage; the source electrode of the eighth P-type MOS transistor MP8 is connected with the drain electrode of the sixth N-type MOS transistor MN6, the gate electrode of the eighth P-type MOS transistor MP8 is connected with the bias voltage VB2, and the drain electrode of the eighth P-type MOS transistor MP8 is connected with the source electrode of the sixth N-type MOS transistor MN 6; the grid electrode of the ninth P-type MOS tube MP9 is connected with the drain electrode of the seventh P-type MOS tube MP7, the source electrode is connected with the power supply voltage, and the drain electrode of the seventh N-type MOS tube MN7 is connected with the drain electrode; the grid electrode of the seventh N-type MOS tube MN7 is connected with the drain electrode of the fifth N-type MOS tube MN5, and the source electrode is connected with the ground; the grid electrode of the tenth P-type MOS tube MP10 is connected with the grid electrode of the ninth P-type MOS tube MP9, the source electrode is connected with the power supply voltage, and the drain electrode is connected with the drain electrode of the eighth N-type MOS tube MN 8; the grid electrode of the eighth N-type MOS transistor MN8 is connected with the grid electrode of the seventh N-type MOS transistor MN7, and the source electrode of the eighth N-type MOS transistor MN8 is connected with the ground; one end of the first capacitor C1 is connected with the drain of the MP7, and the other end is connected with the drain of the ninth P-type MOS transistor MP 9; one end of the second capacitor C2 is connected with the drain electrode of the MN5, and the other end is connected with the drain electrode of the seventh N-type MOS transistor MN 7; one end of the third capacitor C3 is connected with the drain of the MP7, and the other end is connected with the drain of the tenth P-type MOS transistor MP 10; one end of the fourth capacitor C4 is connected to the drain of the MN5, and the other end is connected to the drain of the eighth N-type MOS transistor MN 8.
In addition, the circuit also comprises an input resistance voltage division circuit which comprises a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8; one end of the sixth resistor R6 is connected with one end of the seventh resistor R7 and one end of the eighth resistor R8 respectively, the other end of the seventh resistor R7 is connected with the ground, and the other end of the eighth resistor R8 is connected with the input end of the analog-to-digital converter.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the technical solutions of the present invention, and the protection scope of the present invention is not limited thereto, and those skilled in the art should understand that: those skilled in the art can still modify or easily conceive of changes in the technical solutions described in the foregoing embodiments or make equivalent substitutions for some technical features within the technical scope of the present disclosure; the modifications, changes or substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be covered by the scope of the present invention.
Claims (3)
1. A reference current compensation circuit applied to a high-precision analog-to-digital converter is characterized by comprising a bias current generating circuit, a source follower, a resistance feedback circuit, a first-stage operational amplifier circuit, a level shift circuit, an output-stage circuit and a feedback bias-stage circuit which are sequentially and electrically connected; the device also comprises a bias circuit, a reference voltage source, a power supply voltage source and an analog-to-digital converter;
the bias circuit comprises a first bias circuit, a second bias circuit, a third bias circuit and a fourth bias circuit; the first bias circuit is respectively connected with the first-stage operational amplifier circuit and the level shift circuit; the second bias circuit, the third bias circuit and the fourth bias circuit are all connected with the level shift circuit; the reference voltage source is respectively connected with the bias current generating circuit and the feedback bias stage circuit; the power supply voltage source is respectively connected with the source follower, the level shift circuit, the output stage circuit and the feedback bias stage circuit; the analog-to-digital converter is connected with the source follower.
2. The reference current compensation circuit applied to a high precision analog-to-digital converter according to claim 1,
the bias current generating circuit comprises a first resistor, a second resistor, a first N-type MOS (metal oxide semiconductor) tube and a first P-type MOS tube;
the source follower comprises a second N-type MOS tube, a second P-type MOS tube and a third P-type MOS tube;
the resistance feedback circuit comprises a third resistor and a fourth resistor;
the first-stage operational amplifier circuit comprises a third N-type MOS tube, a fourth P-type MOS tube, a fifth P-type MOS tube and a sixth P-type MOS tube;
the level shift circuit comprises a fifth N-type MOS tube, a sixth N-type MOS tube, a seventh P-type MOS tube and an eighth P-type MOS tube;
the output stage circuit comprises a seventh N-type MOS tube, a ninth P-type MOS tube, a first capacitor and a second capacitor;
the feedback bias stage circuit comprises an eighth N-type MOS tube, a tenth P-type MOS tube, a third capacitor and a fourth capacitor;
one end of the first resistor is connected with the grid electrode of the first P-type MOS tube;
one end of the second resistor is connected with the grid electrode of the first P-type MOS tube, and the other end of the second resistor is connected with the ground;
the drain electrode of the first P-type MOS tube is connected with the drain electrode of the first N-type MOS tube;
the drain electrode of the first N-type MOS tube is connected with the grid electrode, and the source electrode of the first N-type MOS tube is connected with the ground;
the grid electrode of the second N-type MOS tube is connected with the grid electrode of the first N-type MOS tube, the source electrode of the second N-type MOS tube is connected with the ground, and the drain electrode of the second N-type MOS tube is connected with the drain electrode of the third P-type MOS tube;
the grid electrode of the third P-type MOS tube is connected with the input of the analog-to-digital converter, and the source electrode of the third P-type MOS tube is connected with the drain electrode of the second P-type MOS tube;
the grid electrode of the second P-type MOS tube is connected with the drain electrode of the tenth P-type MOS tube MP10, and the drain electrode is connected with one end of the third resistor;
the other end of the third resistor is connected with one end of the fourth resistor and is connected with a grid electrode of the fifth P-type MOS tube;
the other end of the fourth resistor is connected with one end of the fifth resistor and is connected with the drain electrode of the ninth P-type MOS tube;
the source electrode of the fifth P-type MOS tube is connected with the drain electrode of the fourth P-type MOS tube, and the drain electrode of the fifth P-type MOS tube is connected with the drain electrode of the third N-type MOS tube;
the grid electrode of the fourth P-type MOS tube is connected with a first bias voltage circuit;
the source electrode of the sixth P-type MOS tube is connected with the drain electrode of the fourth P-type MOS tube, and the drain electrode of the sixth P-type MOS tube is connected with the drain electrode of the fourth N-type MOS tube;
the drain electrode of the third N-type MOS tube is connected with the grid electrode, and the source electrode of the third N-type MOS tube is connected with the ground;
the grid electrode of the fourth N-type MOS tube is connected with the grid electrode of the third N-type MOS tube, and the source electrode of the fourth N-type MOS tube is connected with the ground;
the grid electrode of the fifth N-type MOS tube is connected with the fourth bias voltage circuit, the source electrode of the fifth N-type MOS tube is connected with the ground, and the drain electrode of the fifth N-type MOS tube is connected with the drain electrode of the fourth N-type MOS tube;
the grid electrode of the sixth N-type MOS tube is connected with bias voltage, the source electrode of the sixth N-type MOS tube is connected with the drain electrode of the fifth N-type MOS tube, and the drain electrode of the sixth N-type MOS tube is connected with the drain electrode of the seventh P-type MOS tube;
the grid electrode of the seventh P-type MOS tube is connected with a first bias voltage circuit;
the source electrode of the eighth P-type MOS tube is connected with the drain electrode of the sixth N-type MOS tube, the grid electrode of the eighth P-type MOS tube is connected with the second bias voltage circuit, and the drain electrode of the eighth P-type MOS tube is connected with the source electrode of the sixth N-type MOS tube;
the grid electrode of the ninth P-type MOS tube is connected with the drain electrode of the seventh P-type MOS tube, and the drain electrode of the seventh N-type MOS tube is connected;
the grid electrode of the seventh N-type MOS tube is connected with the drain electrode of the fifth N-type MOS tube, and the source electrode of the seventh N-type MOS tube is connected with the ground;
the grid electrode of the tenth P-type MOS tube is connected with the grid electrode of the ninth P-type MOS tube, and the drain electrode of the tenth P-type MOS tube is connected with the drain electrode of the eighth N-type MOS tube;
the grid electrode of the eighth N-type MOS tube is connected with the grid electrode of the seventh N-type MOS tube, and the source electrode of the eighth N-type MOS tube is connected with the ground;
one end of the first capacitor is connected with the drain electrode of the seventh P-type MOS tube, and the other end of the first capacitor is connected with the drain electrode of the ninth P-type MOS tube;
one end of the second capacitor is connected with the drain electrode of the fifth N-type MOS tube, and the other end of the second capacitor is connected with the drain electrode of the seventh N-type MOS tube;
one end of the third capacitor is connected with the drain electrode of the seventh P-type MOS tube, and the other end of the third capacitor is connected with the drain electrode of the tenth P-type MOS tube;
and one end of the fourth capacitor is connected with the drain electrode of the fifth N-type MOS tube, and the other end of the fourth capacitor is connected with the drain electrode of the eighth N-type MOS tube.
3. The reference current compensation circuit applied to the high-precision analog-to-digital converter as claimed in claim 2, further comprising an input resistance voltage divider circuit comprising a sixth resistor, a seventh resistor, and an eighth resistor; one end of the sixth resistor is connected with one end of the seventh resistor and one end of the eighth resistor respectively, the other end of the seventh resistor is connected with the ground, and the other end of the eighth resistor is connected with the input end of the analog-to-digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922288994.2U CN211427183U (en) | 2019-12-18 | 2019-12-18 | Reference current compensation circuit applied to high-precision analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922288994.2U CN211427183U (en) | 2019-12-18 | 2019-12-18 | Reference current compensation circuit applied to high-precision analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211427183U true CN211427183U (en) | 2020-09-04 |
Family
ID=72254443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922288994.2U Active CN211427183U (en) | 2019-12-18 | 2019-12-18 | Reference current compensation circuit applied to high-precision analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211427183U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111026217A (en) * | 2019-12-18 | 2020-04-17 | 西安航天民芯科技有限公司 | Reference current compensation circuit applied to high-precision analog-to-digital converter |
-
2019
- 2019-12-18 CN CN201922288994.2U patent/CN211427183U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111026217A (en) * | 2019-12-18 | 2020-04-17 | 西安航天民芯科技有限公司 | Reference current compensation circuit applied to high-precision analog-to-digital converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105486912B (en) | A kind of quick over-current detection circuit of the high-precision of low pressure difference linear voltage regulator | |
| CN107340796B (en) | A kind of non-resistance formula high-precision low-power consumption a reference source | |
| CN101667046B (en) | Low-dropout voltage regulator | |
| CN103729010B (en) | High-precision band-gap reference source circuit | |
| CN110690864B (en) | Energy gap voltage reference circuit | |
| CN111781983A (en) | High power supply rejection ratio sub-threshold MOSFET compensation band-gap reference voltage circuit | |
| CN111609943A (en) | Temperature detection circuit | |
| CN105320199A (en) | Reference voltage source with higher-order compensation | |
| CN211427183U (en) | Reference current compensation circuit applied to high-precision analog-to-digital converter | |
| CN105897185B (en) | A kind of circuit applied to low imbalance operational amplifier | |
| CN201926944U (en) | Microampere precise constant flow source circuit | |
| US20150277470A1 (en) | Current mirror circuit and receiver using the same | |
| JP2011223130A (en) | Comparison circuit | |
| CN103246311A (en) | Non-resistor band-gap reference voltage source with high-order curvature compensation | |
| CN111026217A (en) | Reference current compensation circuit applied to high-precision analog-to-digital converter | |
| WO2024093602A1 (en) | Voltage reference generation circuit, and chip and electronic device | |
| CN111752325B (en) | High-precision linear voltage stabilizing circuit | |
| CN102707756B (en) | A kind of wide load linearity adjustor using dynamic ESR to compensate resistance | |
| CN116931641B (en) | Low-power consumption high-precision resistance-free CMOS reference voltage source | |
| CN114740938B (en) | Reference circuit and reference voltage ware applied to Sigma-Delta ADC | |
| CN116880644A (en) | High-order curvature temperature compensation band gap reference circuit | |
| CN111458554B (en) | High-precision current monitoring circuit | |
| CN115167596A (en) | Novel sectional compensation band gap reference circuit | |
| CN216313052U (en) | Operational amplification circuit | |
| CN104198066A (en) | Temperature sensor circuit based on reference source |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |