CN211350615U - Semiconductor integrated circuit packaging structure - Google Patents
Semiconductor integrated circuit packaging structure Download PDFInfo
- Publication number
- CN211350615U CN211350615U CN202020166849.7U CN202020166849U CN211350615U CN 211350615 U CN211350615 U CN 211350615U CN 202020166849 U CN202020166849 U CN 202020166849U CN 211350615 U CN211350615 U CN 211350615U
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit substrate
- fixedly connected
- heat dissipation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 230000017525 heat dissipation Effects 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000945 filler Substances 0.000 claims abstract description 19
- 239000004831 Hot glue Substances 0.000 claims abstract description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 238000003466 welding Methods 0.000 abstract description 6
- 239000006071 cream Substances 0.000 abstract description 4
- 238000010030 laminating Methods 0.000 abstract description 4
- 238000012856 packing Methods 0.000 abstract description 2
- 239000003795 chemical substances by application Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The utility model discloses a semiconductor integrated circuit packaging structure, including circuit substrate, integrated circuit device and tin cream layer, the upside fixedly connected with integrated circuit device of circuit substrate, and integrated circuit device and circuit substrate's junction is provided with the tin cream layer, the upper surface laminating of circuit substrate is provided with the protecting film, and circuit substrate's upside fixedly connected with connection frame, the inboard packing of connection frame is provided with the hot melt adhesive agent, and has all seted up the fixed slot on the lateral wall about the connection frame, the inboard middle part welding of fixed slot has the fixed block, the upper end block of connection frame is connected at the protecting crust, and the lower extreme welding of protecting crust has the connecting plate, the inside upside wall welding of protecting crust has spacing frame, and the upside wall of protecting crust is the laminating setting with the heat dissipation filler. The semiconductor integrated circuit packaging structure is convenient for protection processing, improves the reliability and is convenient for heat dissipation processing.
Description
Technical Field
The utility model relates to a semiconductor integrated circuit correlation technique field specifically is a semiconductor integrated circuit packaging structure.
Background
A semiconductor integrated circuit is a core device of an electronic product and plays a crucial role in the electronic product, in which electronic components are integrated on a single semiconductor chip to complete a specific circuit or system function.
However, after the semiconductor integrated circuit is packaged, the reliability of the semiconductor integrated circuit is insufficient, so that the integrated circuit is inconvenient to protect and radiate, the radiating effect is greatly reduced, and the service life of the integrated circuit is influenced.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor integrated circuit packaging structure to the processing of protecting is not convenient for to integrated circuit that proposes in solving above-mentioned background art, and inconvenient heat dissipation treatment that carries on influences integrated circuit life's problem in addition.
In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides a semiconductor integrated circuit packaging structure, includes circuit substrate, integrated circuit device and tin cream layer, the upside fixedly connected with integrated circuit device of circuit substrate, and integrated circuit device and circuit substrate's junction is provided with the tin cream layer, circuit substrate's upper surface laminating is provided with the protecting film, and circuit substrate's upside fixedly connected with connection frame, the inboard packing of connection frame is provided with the hot melt adhesive, and all seted up the fixed slot on the lateral wall about the connection frame, the inboard middle part welding of fixed slot has the fixed block, the upper end block of connection frame is connected at the protecting crust, and the lower extreme welding of protecting crust has the connecting plate, the inside last lateral wall welding of protecting crust has spacing frame, and the last lateral wall and the heat dissipation filler of protecting crust are the laminating setting.
Preferably, the integrated circuit device comprises a packaging shell, a printed circuit board and a chip body, wherein the printed circuit board is fixedly connected to the lower side inside the packaging shell, the chip body is fixedly connected to the upper surface of the printed circuit board, and the lower surface of the printed circuit board is fixedly connected with the upper surface of the circuit substrate through a solder paste layer.
Preferably, the connection frame is sleeved outside the integrated circuit device, and the area size of the cross section of the connection frame is equal to the area size of the cross section of the protective shell.
Preferably, the fixed block is connected with the connecting plate in a clamping mode, and the longitudinal section of the fixed block is in the shape of a right-angled triangle.
Preferably, the connecting plates are symmetrically arranged about a horizontal central axis of the protective shell, and the longitudinal section of each connecting plate is of a structure shaped like a Chinese character 'hui'.
Preferably, the heat dissipation filler is filled inside the limit frame, and the lower surface of the heat dissipation filler is attached to the upper side of the integrated circuit device.
Compared with the prior art, the beneficial effects of the utility model are that: the semiconductor integrated circuit packaging structure is convenient for protection processing, improves the reliability, is convenient for heat dissipation processing, and effectively improves the heat dissipation effect;
1. the protective film is arranged on the upper surface of the circuit substrate in a fitting manner, the hot melt adhesive is filled in the gap between the integrated circuit device and the connecting frame, and the upper end of the connecting frame is connected with the protective shell in a clamping manner, so that the protective treatment is facilitated, and the reliability is effectively improved;
2. the protective shell is provided with connecting plates, the connecting plates are symmetrically arranged about a horizontal central axis of the protective shell, the connecting plates are connected with the fixed block in a clamping mode, and the longitudinal section of the fixed block is in a right-angled triangle shape, so that the protective shell is convenient to mount and fix, and the operation is more convenient;
3. the heat dissipation filler is arranged, the heat dissipation filler is filled and arranged on the inner side of the limiting frame, the lower surface of the heat dissipation filler is attached to the upper side wall of the integrated circuit device, heat dissipation treatment is facilitated due to the arrangement of the heat dissipation filler, and the heat dissipation effect is improved.
Drawings
Fig. 1 is a schematic view of the front cross-sectional structure of the present invention;
FIG. 2 is a schematic diagram of an integrated circuit device according to the present invention;
fig. 3 is a schematic view of the front perspective structure of the present invention.
In the figure: 1. a circuit substrate; 2. an integrated circuit device; 201. a package housing; 202. a printed circuit board; 203. a chip body; 3. a solder paste layer; 4. a protective film; 5. a connecting frame; 6. a hot melt adhesive; 7. fixing grooves; 8. a fixed block; 9. a protective shell; 10. a connecting plate; 11. a limiting frame; 12. a heat-dissipating filler.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-3, the present invention provides a technical solution: a semiconductor integrated circuit package structure comprises a circuit substrate 1, an integrated circuit device 2, a solder paste layer 3, a protective film 4, a connecting frame 5, a hot melt adhesive 6, a fixing groove 7, a fixing block 8, a protective shell 9, a connecting plate 10, a limiting frame 11 and a heat dissipation filler 12, wherein the integrated circuit device 2 is fixedly connected to the upper side of the circuit substrate 1, the solder paste layer 3 is arranged at the joint of the integrated circuit device 2 and the circuit substrate 1, the protective film 4 is attached to the upper surface of the circuit substrate 1, the connecting frame 5 is fixedly connected to the upper side of the circuit substrate 1, the hot melt adhesive 6 is filled in the connecting frame 5, the fixing grooves 7 are respectively arranged on the left side wall and the right side wall of the connecting frame 5, the fixing block 8 is welded to the middle part of the inner side of the fixing groove 7, the upper end of the connecting frame 5 is clamped and connected to the protective shell 9, the connecting plate 10 is welded to the lower end, and the upper side wall of the protective shell 9 is attached to the heat dissipation filler 12.
As shown in fig. 1, the heat dissipation filler 12 is filled inside the position-limiting frame 11, and the lower surface of the heat dissipation filler 12 is attached to the upper side of the integrated circuit device 2, so that the heat dissipation treatment is facilitated and the heat dissipation effect is improved due to the arrangement of the heat dissipation filler 12.
As shown in fig. 1, 2 and 3, the integrated circuit device 2 includes a package housing 201, a printed circuit board 202 and a chip body 203, the printed circuit board 202 is fixedly connected to the lower side of the interior of the package housing 201, the chip body 203 is fixedly connected to the upper surface of the printed circuit board 202, the lower surface of the printed circuit board 202 is fixedly connected to the upper surface of the circuit substrate 1 through a solder paste layer 3, the connection frame 5 is sleeved on the outer side of the integrated circuit device 2, the area size of the cross section of the connection frame 5 is equal to the area size of the cross section of the protective housing 9, the fixed block 8 is connected to the connection board 10 in a snap-fit manner, the longitudinal section of the fixed block 8 is in a right triangle shape, the connection board 10 is symmetrically arranged about the horizontal central axis of the protective housing 9, and the longitudinal section of the connection board 10 is in a "return" shape ", the reliability is effectively improved.
The working principle is as follows: when the semiconductor integrated circuit packaging structure is used, firstly, as shown in figure 2, a chip body 203 is fixedly connected to the upper surface of a printed circuit board 202, the lower surface of the printed circuit board 202 is fixedly connected to the upper surface of a circuit substrate 1 through a solder paste layer 3, a packaging shell 201 is covered on the outer sides of the printed circuit board 202 and the chip body 203, as shown in figure 1, a connecting frame 5 is sleeved on the outer side of an integrated circuit device 2, a gap between the integrated circuit device 2 and the connecting frame 5 is filled with a hot melt adhesive 6, a protective film 4 is attached to the upper surface of the circuit substrate 1, the integrated circuit is subjected to protective treatment, the longitudinal section of a connecting plate 10 is of a 'return' shape structure, the longitudinal section of a fixing block 8 is of a right triangle shape, after the connecting plate 10 is connected with the fixing block 8 in a clamping manner, the connecting plate 10 is, the protective shell 9 is fixed, the inner side of the limiting frame 11 is filled with the heat dissipation filler 12, the lower surface of the heat dissipation filler 12 is attached to the upper surface of the integrated circuit device 2, the heat dissipation effect is improved, and the process is the whole process of using the semiconductor integrated circuit packaging structure.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A semiconductor integrated circuit package structure comprising a circuit substrate (1), an integrated circuit device (2) and a solder paste layer (3), characterized in that: the upper side of the circuit substrate (1) is fixedly connected with an integrated circuit device (2), a tin paste layer (3) is arranged at the joint of the integrated circuit device (2) and the circuit substrate (1), a protective film (4) is arranged on the upper surface of the circuit substrate (1) in a fitting manner, the upper side of the circuit substrate (1) is fixedly connected with a connecting frame (5), the inner side of the connecting frame (5) is filled with hot melt adhesive (6), fixing grooves (7) are formed in the left side wall and the right side wall of the connecting frame (5), a fixing block (8) is welded in the middle of the inner side of each fixing groove (7), the upper end of the connecting frame (5) is connected to the protective shell (9) in a clamping mode, a connecting plate (10) is welded at the lower end of the protective shell (9), a limiting frame (11) is welded on the upper side wall inside the protective shell (9), and the upper side wall of the protective shell (9) is attached to the heat dissipation filler (12).
2. The semiconductor integrated circuit package structure of claim 1, wherein: the integrated circuit device (2) comprises a packaging shell (201), a printed circuit board (202) and a chip body (203), wherein the printed circuit board (202) is fixedly connected to the lower side of the interior of the packaging shell (201), the chip body (203) is fixedly connected to the upper surface of the printed circuit board (202), and the lower surface of the printed circuit board (202) is fixedly connected with the upper surface of the circuit substrate (1) through a tin paste layer (3).
3. The semiconductor integrated circuit package structure of claim 1, wherein: the connecting frame (5) is sleeved on the outer side of the integrated circuit device (2), and the area size of the cross section of the connecting frame (5) is equal to the area size of the cross section of the protective shell (9).
4. The semiconductor integrated circuit package structure of claim 1, wherein: the fixing block (8) is connected with the connecting plate (10) in a clamping mode, and the longitudinal section of the fixing block (8) is in the shape of a right-angled triangle.
5. The semiconductor integrated circuit package structure of claim 1, wherein: the connecting plates (10) are symmetrically arranged about a horizontal central axis of the protective shell (9), and the longitudinal section of each connecting plate (10) is of a structure shaped like a Chinese character 'hui'.
6. The semiconductor integrated circuit package structure of claim 1, wherein: the heat dissipation filling agent (12) is filled inside the limiting frame (11), and the lower surface of the heat dissipation filling agent (12) is attached to the upper side of the integrated circuit device (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020166849.7U CN211350615U (en) | 2020-02-13 | 2020-02-13 | Semiconductor integrated circuit packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020166849.7U CN211350615U (en) | 2020-02-13 | 2020-02-13 | Semiconductor integrated circuit packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211350615U true CN211350615U (en) | 2020-08-25 |
Family
ID=72093375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020166849.7U Expired - Fee Related CN211350615U (en) | 2020-02-13 | 2020-02-13 | Semiconductor integrated circuit packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211350615U (en) |
-
2020
- 2020-02-13 CN CN202020166849.7U patent/CN211350615U/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111883440B (en) | Glue filling method, module packaging structure and electronic equipment | |
| JP6793175B2 (en) | SiP module and its manufacturing method | |
| TW344870B (en) | Semiconductor package and manufacturing method of lead frame | |
| CN210956638U (en) | Embedded type sensing UNITMA chip packaging structure | |
| CN211350615U (en) | Semiconductor integrated circuit packaging structure | |
| CN111696925A (en) | Chip packaging structure and method | |
| CN114792680A (en) | Power management chip packaging structure and manufacturing method thereof | |
| JPH08139235A (en) | Electronic equipment and its manufacture | |
| EP4181185A1 (en) | Power module, and preparation mold and apparatus | |
| CN212046381U (en) | Tin paste brushing mold | |
| CN209963048U (en) | Packaging structure of chip circuit board | |
| CN213042914U (en) | Semiconductor packaging structure | |
| CN210897253U (en) | Semiconductor packaging structure | |
| CN212967690U (en) | High-reliability double-sided PBGA packaging substrate | |
| CN212587485U (en) | Chip on film packaging structure | |
| CN212161789U (en) | Double-layer step-shaped metal device | |
| CN214176018U (en) | Power semiconductor packaging structure | |
| CN212113679U (en) | Chip packaging structure | |
| JPH03266456A (en) | Semiconductor chip heat dissipating member and semiconductor package | |
| CN216213420U (en) | Lead frame packaging structure | |
| CN217332825U (en) | Multi-sensor integrated packaging module | |
| CN203119745U (en) | Plastic package module power supply | |
| CN215301208U (en) | Plastic packaging structure of waterproof communication element | |
| CN216389316U (en) | Semiconductor packaging unit | |
| CN213182534U (en) | Base framework for heat dissipation device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200825 |