CN211293540U - Display panel and display device - Google Patents
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- CN211293540U CN211293540U CN201920872280.3U CN201920872280U CN211293540U CN 211293540 U CN211293540 U CN 211293540U CN 201920872280 U CN201920872280 U CN 201920872280U CN 211293540 U CN211293540 U CN 211293540U
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Abstract
The application discloses a display panel and a display device, wherein the display panel comprises an array substrate and a color film substrate arranged opposite to the array substrate; the array substrate comprises a data line, a scanning line and a pixel unit formed by the scanning line and the data line; the pixel unit comprises a main pixel area, a secondary pixel area and a thin film transistor connected with the pixel unit; the thin film transistor comprises a first thin film transistor connected with the pixel electrode of the main pixel area and a second thin film transistor connected with the pixel electrode of the secondary pixel area; the number of the first thin film transistor and the second thin film transistor is one and only one. The number of the thin film transistors is reduced, the width-to-length ratio of the channels of the thin film transistors is increased, the occupied area of the thin film transistors is reduced, the aperture opening ratio of the display panel is increased, and the problem of color cast of the wide-viewing-angle panel is solved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
Va (vertical alignment) panels are panel types which are widely used in high-end liquid crystal at present, and belong to wide viewing angle panels. When a conventional VA mode liquid crystal panel is viewed at a wide viewing angle, a problem of color shift often occurs. In order to improve the color shift of the wide viewing angle panel, the conventional wide viewing angle panel divides the pixels into two regions, and when the panel is in operation, one region (Main) has higher brightness and the other region (Sub) has lower brightness, so that the wide viewing angle characteristic of the panel is improved by the two regions with different brightness.
Because the area of the Sub area is large (accounting for about 60% of the pixel opening area), the penetration rate of the whole pixel can be greatly sacrificed, the power consumption of the backlight is increased, and the current concept of environmental protection and energy saving is not met. In addition, because the Main area is provided with high-brightness pixels, the Sub area is provided with low-brightness pixels, and the high-brightness pixels and the low-brightness pixels are respectively over-concentrated, the brightness difference of the two areas is over-obvious, and the visual effect is poor.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a display panel and a display device, and the display panel and the display device are used for solving the technical problems that when an existing multi-domain vertical orientation type liquid crystal display panel is watched at a large visual angle position, the contrast of a picture is reduced, color cast occurs, and the display effect is poor.
In order to achieve the above object, the present application discloses a display panel, which includes an array substrate and a color film substrate disposed opposite to the array substrate; the array substrate comprises data lines, scanning lines, pixel units formed by the scanning lines and the data lines in a staggered mode and thin film transistors connected with the pixel units; the pixel unit comprises a main pixel area and a sub-pixel area, and the thin film transistor comprises a first thin film transistor connected with a pixel electrode of the main pixel area and a second thin film transistor connected with a pixel electrode of the sub-pixel area; the number of the first thin film transistor and the second thin film transistor is one and only one.
Optionally, the pixel unit includes a plurality of sub-pixels, and the main pixel area and the sub-pixel area include four domains, where a same sub-pixel of the four domains of the main pixel area and a same sub-pixel of the four domains of the sub-pixel area rotate at different angles.
Optionally, the thin film transistor includes a source electrode, a drain electrode disposed opposite to the source electrode, and a channel region defined by the source electrode and the drain electrode; the first thin film transistor and the second thin film transistor have different channel region width-to-length ratios.
Optionally, the width of the channel region of the first thin film transistor is the same as the width of the channel region of the second thin film transistor, and the length of the channel region of the first thin film transistor is greater than the length of the channel region of the second thin film transistor.
Optionally, the length of the channel region of the first thin film transistor is the same as the length of the channel region of the second thin film transistor, and the width of the channel region of the first thin film transistor is smaller than the width of the channel region of the second thin film transistor.
Optionally, the length of the channel region of the second thin film transistor is smaller than that of the first thin film transistor, and the width of the channel region of the second thin film transistor is larger than that of the channel region of the first thin film transistor.
Optionally, the length of the channel region is not less than 4 um.
Optionally, the thin film transistor is made of one of Al, Cu, Mo, MoW, AlNd, and Cr, and the channel region is U-shaped.
The application also discloses a display panel, which comprises an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer positioned between the array substrate and the color film substrate; the array substrate comprises data lines, scanning lines, pixel units formed by the scanning lines and the data lines in a staggered mode and thin film transistors connected with the pixel units; the pixel unit comprises a main pixel area and a sub-pixel area which are defined by the scanning lines and the data lines; the thin film transistor comprises a first thin film transistor connected with the pixel electrode of the main pixel area and a second thin film transistor connected with the pixel electrode of the secondary pixel area; the main pixel area and the sub-pixel area comprise four domains; the channel width-length ratio of the second thin film transistor is larger than that of the first thin film transistor; the thin film transistor comprises a source electrode, a drain electrode and a channel region; the length of the channel region of the second thin film transistor is smaller than that of the channel region of the first thin film transistor, and the width of the channel region of the second thin film transistor is larger than that of the channel region of the first thin film transistor.
The application also discloses a display device, which comprises the display panel.
Compared with a multi-domain vertical alignment liquid crystal display panel on the market, the eight domains correspond to three thin film transistors; this application all sets up a thin film transistor in main pixel district and sub-pixel district to through the width-length ratio of increase channel, corresponding area that reduces thin film transistor, increase display panel's aperture opening ratio, and then can be under the condition of display panel demonstration same luminance, the corresponding consumption that reduces display panel improves wide visual angle panel and takes place the problem of colour cast.
Drawings
The accompanying drawings, which are included to provide an understanding of embodiments of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic structural diagram of an exemplary display panel of the present application;
FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
FIG. 4 is a schematic structural diagram of a TFT of a display panel according to an embodiment of the present disclosure;
FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a display panel according to another embodiment of the present application;
FIG. 7 is a schematic structural diagram of a display panel according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a display device according to an embodiment of the present application.
100, a display panel; 110. scanning a line; 120. a data line; 130. a pixel unit; 140. a main pixel region; 150. a sub-pixel region; 160. an array substrate; 170. a color film substrate; 200. a thin film transistor; 210. a first thin film transistor; 220. a second thin film transistor; 230. a source electrode; 240. a drain electrode; 250. a channel region; 300. a display device.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present application. This application may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, it is to be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and therefore should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The application is further described with reference to the drawings and alternative embodiments.
As shown in fig. 1 to fig. 3, a display panel 100 of the present disclosure includes an array substrate 160 and a color filter substrate 170 disposed opposite to the array substrate 160; the array substrate 160 includes a data line 120, a scan line 110, a pixel unit 130 formed by interleaving the scan line 110 and the data line 120, and a thin film transistor 200 connected to the pixel unit 130; the pixel unit 130 includes a main pixel region 140 and a sub-pixel region 150 defined by the scan line 110 and the data line 120, and the thin film transistor 200 includes a first thin film transistor 210 connected to a pixel electrode of the main pixel region 140 and a second thin film transistor 220 connected to a pixel electrode of the sub-pixel region 150; the number of the first thin film transistor 210 and the second thin film transistor 220 is one and only one.
Compared with a common display panel, the sub-pixel area 150 usually has two thin film transistors 200, one thin film transistor 200 is reduced, the area of the thin film transistor 200 in the pixel unit 130 is correspondingly reduced, the aperture ratio of the display panel 100 is increased, and the problem of color cast of a wide-viewing-angle panel is solved.
Further, the pixel unit 130 includes a plurality of sub-pixels, and the main pixel area 140 and the sub-pixel area 150 include four domains, wherein the same sub-pixel of the four domains of the main pixel area 140 and the same sub-pixel of the four domains of the sub-pixel area 150 have different rotation angles.
Taking the eight-domain display panel as an example, the eight-domain pixels are set as the four-domain main pixel area 140 and the four-domain sub-pixel area 150, and the sub-pixels of the main pixel area 140 and the sub-pixels of the sub-pixel area 150 have different rotation angles, and different voltages and areas are respectively applied to the main pixel area and the sub-pixel area 150, so that the main pixel area and the sub-pixel area 150 display different gray scales, and the effect of improving the viewing angle is achieved by spatial mixing.
As shown in fig. 4, the thin film transistor 200 includes a source electrode 230 and a drain electrode 240 disposed opposite to the source electrode 230, and a channel region 250 defined by the source electrode 230 and the drain electrode 240; the channel regions 250 of the first thin film transistor 210 and the second thin film transistor 220 have different width-to-length ratios.
When a scan signal is input to the scan line 110, the thin film transistor connected to the scan line 110 is turned on, and a gray-scale signal applied to the data line 120 is applied to the pixel electrode through the thin film transistor to charge the pixel electrode. Since the charging rate of the pixel electrode is related to the on-current of the tft 200, the on-current of the tft 200 is affected by the width-to-length ratio of the channel region 250 of the tft, the width-to-length ratio of the channel of the tft 200 is different between the main pixel region 140 and the sub-pixel region 150, and the larger the width-to-length ratio of the channel of the tft 200 is, the brighter the corresponding pixel region is, thereby reducing the color shift at wide viewing angles.
Conventional aspect ratio affecting the channel of the thin film transistor 200
Specifically, there are two methods for increasing the width-to-length ratio of the channel region 250 of the thin film transistor, one is realized by increasing the width W of the channel, and the other is realized by decreasing the length L of the channel. Since the luminance of the sub-pixel region 150 is low, the aspect ratio of the channel region of the second thin film transistor 220 in the sub-pixel region 150 needs to be increased
Therefore, the brightness of the sub-pixel region 150 is increased, the brightness of the sub-pixel region 150 is close to the same as that of the main pixel region 140, the difference between the brightness of the two pixel regions is reduced, and the visual effect is improved.
As shown in fig. 5, the channel region 250 of the first thin film transistor 210 and the channel region 250 of the second thin film transistor 220 have the same width W1-W2, and the length L1 of the channel region 250 of the first thin film transistor 210 is greater than the length L2 of the channel region 250 of the second thin film transistor 220.
The width of the channel region 250 of the first thin film transistor 210 is W1, the width of the channel region 250 of the second thin film transistor 220 is W2, and the length L2 of the channel region 250 of the second thin film transistor 220 is reduced, and because the width of the channel region 250 is not changed, W1 is W2, and L1 is changed>L2, the width to length ratio of the channel region 250 of the second TFT 220 is greater than the width to length ratio of the channel region 250 of the first TFT 210 by
The brightness of the entire sub-pixel region 150 is increased to reduce the difference in brightness from the main pixel region 140.
Alternatively, as shown in fig. 6, the channel region 250 of the first thin film transistor 210 and the channel region 250 of the second thin film transistor 220 have the same length L1-L2, and the width W1 of the channel region 250 of the first thin film transistor 210 is smaller than the width W2 of the channel region of the second thin film transistor 220.
By increasing the width W2 of the channel region of the second thin film transistor 220, the length of the channel region of the first thin film transistor 210 is L1, and the width is W1; the channel region 250 of the second thin film transistor 220 has a width L2, and L1 is L2, and W1 is W1<W2, the width to length ratio of the channel region 250 of the first TFT 210 and the second TFT 220 is
The width-to-length ratio of the second thin film transistor 220 is increased, so that the brightness of the whole sub-pixel region 150 is increased and approaches to the brightness of the main pixel region 140, the brightness difference is not obvious, and the display effect is improved.
Of course, as shown in fig. 7, the second thin film transistor 220 can also be adjusted to simultaneously adjust two variables, i.e. to increase the width W2 of the channel region 250 and to decrease the length L2 of the channel region 250, i.e. to W1<W2,L1>L2 having a width to length ratio of
Therefore, the brightness of the sub-pixel area 150 is approximately consistent with the brightness of the main pixel area 140, and the color cast caused by uneven brightness of the picture due to the wide-viewing-angle panel characteristic is improved.
More specifically, in the method of increasing the width-to-length ratio of the channel region 250 by decreasing the length L of the channel region 250, the length L of the channel region 250 cannot be less than 4um due to the substrate arrangement of the display panel 100, and the arrangement of the width W of the channel region 250 is not limited.
The material of the thin film transistor 200 is one of Al, Cu, Mo, MoW, AlNd, and Cr, and the channel region 250 has a U-shape.
The material of the thin film transistor 200 may be any of the above metals or alloy materials, and the source and drain electrodes 240 of the first thin film transistor 210 and the second thin film transistor 220 may be made of the same metal layer; the pixel unit 130 is made of ITO; the shape of the channel region 250 may be a channel shape, and any channel structure formed by the source electrode 230 and the drain electrode 240 is included in the present application regardless of the channel shape.
As another embodiment of the present application, the present application further includes a display panel 100, which includes an array substrate 160, a color filter substrate 170 disposed opposite to the array substrate 160, and a liquid crystal layer located between the array substrate 160 and the color filter substrate 170; the array substrate 160 includes a data line 120, a scan line 110, a pixel unit 130 formed by interleaving the scan line 110 and the data line 120, and a thin film transistor 200 connected to the pixel unit 130; the pixel unit 130 includes a main pixel region 140 and a sub-pixel region 150 defined by the scan line 110 and the data line 120; the thin film transistor 200 includes a first thin film transistor 210 connected to the main pixel region 140 and a second thin film transistor 220 connected to the sub pixel region 150; the main pixel region 140 and the sub-pixel region 150 db include four domains; the channel width-to-length ratio of the second thin film transistor 220 is greater than the channel width-to-length ratio of the first thin film transistor 210; the thin film transistor includes a source electrode 230, a drain electrode 240, and a channel region 250; the length of the channel region 250 of the second thin film transistor 220 is smaller than the length of the channel region 250 of the first thin film transistor 210, and the width of the channel region 250 of the second thin film transistor 220 is greater than the width of the channel region 250 of the first thin film transistor 210.
As another embodiment of the present application, as shown in fig. 8, the present application further discloses a display device 300 including the display panel 100 described in any one of the above.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the present application is not intended to be limited to the specific embodiments shown. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A display panel, comprising:
an array substrate;
the color film substrate is arranged opposite to the array substrate;
the array substrate includes: the pixel structure comprises data lines, scanning lines, pixel units formed by the scanning lines and the data lines in a staggered mode and thin film transistors connected with the pixel units;
the pixel unit comprises a main pixel area and a sub-pixel area, and the thin film transistor comprises a first thin film transistor connected with a pixel electrode of the main pixel area and a second thin film transistor connected with a pixel electrode of the sub-pixel area;
the number of the first thin film transistor and the second thin film transistor is one and only one.
2. The display panel according to claim 1, wherein the pixel unit comprises a plurality of sub-pixels, the main pixel region and the sub-pixel region respectively comprise four domains, and wherein the same sub-pixel of the main pixel region and the same sub-pixel of the sub-pixel region rotate at different angles.
3. The display panel according to claim 1, wherein the thin film transistor includes a source electrode and a drain electrode disposed opposite to the source electrode, and a channel region defined by the source electrode and the drain electrode;
wherein channel region width-to-length ratios of the first thin film transistor and the second thin film transistor are different.
4. A display panel according to claim 3, wherein the channel region of the first thin film transistor and the channel region of the second thin film transistor have the same width, and the length of the channel region of the first thin film transistor is longer than the length of the channel region of the second thin film transistor.
5. A display panel according to claim 3, wherein the channel region of the first thin film transistor and the channel region of the second thin film transistor have the same length, and wherein the width of the channel region of the first thin film transistor is smaller than the length of the channel region of the second thin film transistor.
6. A display panel according to claim 3, wherein a length of a channel region of the second thin film transistor is smaller than a length of a channel region of the first thin film transistor, and a width of the channel region of the second thin film transistor is larger than a width of the channel region of the first thin film transistor.
7. A display panel according to claim 3, wherein the length of the channel region is not less than 4 um.
8. The display panel according to claim 3, wherein the material of the thin film transistor is one of Al, Cu, Mo, MoW, AlNd, and Cr, and the channel region has a U-shape.
9. A display panel, comprising:
an array substrate;
the color film substrate is arranged opposite to the array substrate;
wherein, the array substrate includes: the pixel structure comprises data lines, scanning lines, pixel units formed by the scanning lines and the data lines in a staggered mode and thin film transistors connected with the pixel units;
the pixel unit comprises a main pixel area and a sub-pixel area which are defined by the scanning lines and the data lines; the main pixel area and the sub-pixel area respectively comprise four domains; the thin film transistor comprises a first thin film transistor connected with the pixel electrode of the main pixel area and a second thin film transistor connected with the pixel electrode of the secondary pixel area;
the thin film transistor comprises a source electrode, a drain electrode and a channel region;
the length of the channel region of the second thin film transistor is smaller than that of the channel region of the first thin film transistor, and the width of the channel region of the second thin film transistor is larger than that of the channel region of the first thin film transistor.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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| CN201920872280.3U CN211293540U (en) | 2019-06-11 | 2019-06-11 | Display panel and display device |
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| CN201920872280.3U CN211293540U (en) | 2019-06-11 | 2019-06-11 | Display panel and display device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112017545A (en) * | 2020-09-03 | 2020-12-01 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN113325645A (en) * | 2021-05-31 | 2021-08-31 | Tcl华星光电技术有限公司 | Pixel structure, design method thereof and display panel |
| CN114355680A (en) * | 2022-01-06 | 2022-04-15 | Tcl华星光电技术有限公司 | Pixel structure, array substrate and display panel |
| US11404580B2 (en) | 2020-09-03 | 2022-08-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel and display device |
| WO2023015834A1 (en) * | 2021-08-12 | 2023-02-16 | 惠科股份有限公司 | Array substrate, display panel, and display apparatus |
-
2019
- 2019-06-11 CN CN201920872280.3U patent/CN211293540U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112017545A (en) * | 2020-09-03 | 2020-12-01 | Tcl华星光电技术有限公司 | Display panel and display device |
| US11404580B2 (en) | 2020-09-03 | 2022-08-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel and display device |
| CN113325645A (en) * | 2021-05-31 | 2021-08-31 | Tcl华星光电技术有限公司 | Pixel structure, design method thereof and display panel |
| CN113325645B (en) * | 2021-05-31 | 2022-05-31 | Tcl华星光电技术有限公司 | Pixel structure, design method thereof and display panel |
| WO2023015834A1 (en) * | 2021-08-12 | 2023-02-16 | 惠科股份有限公司 | Array substrate, display panel, and display apparatus |
| CN114355680A (en) * | 2022-01-06 | 2022-04-15 | Tcl华星光电技术有限公司 | Pixel structure, array substrate and display panel |
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