WO2023015834A1

WO2023015834A1 - Array substrate, display panel, and display apparatus

Info

Publication number: WO2023015834A1
Application number: PCT/CN2021/143355
Authority: WO
Inventors: 常红燕; 郑浩旋
Original assignee: 惠科股份有限公司
Priority date: 2021-08-12
Filing date: 2021-12-30
Publication date: 2023-02-16
Also published as: CN113376912B; CN113376912A

Abstract

Disclosed in the present application are an array substrate, a display panel, and a display apparatus, relating to the technical field of display. In the array substrate (10), a switch circuit (120) connected to a first scan line is a first switch circuit (122), and each first switch circuit (122) comprises a plurality of transistors. The control electrodes of the plurality of transistors in each first switch circuit (122) are all connected to the first scan line, the first electrodes of the plurality of transistors in each first switch circuit (122) are connected to the same data line (130), and the second electrodes of the plurality of transistors in each first switch circuit (122) are connected to sub-pixels (110). The present array substrate (10) can increase the charging amount of the sub-pixels (110) corresponding to the first switch circuits (122), thereby increasing the light emission brightness of the sub-pixels (110) connected to the first scan line in a display panel (20) in which the array substrate (10) is used.

Description

Array substrate, display panel, and display device

This application claims the priority of the Chinese patent application with the application number 202110924277.3 and the application name "Array Substrate and Display Panel" filed at the Patent Office of the State Intellectual Property Office of the People's Republic of China on August 12, 2021. References are incorporated in this application.

technical field

The present application relates to the field of display technology, in particular to an array substrate, a display panel, and a display device.

Background technique

The display panel includes a plurality of scanning lines, a plurality of data lines, a plurality of sub-pixels, and a plurality of switch circuits corresponding to the plurality of sub-pixels. When the display panel is working, the scanning line control switch circuit is turned on. The data lines write electrical signals into the corresponding sub-pixels through the switch circuit, charge the sub-pixels, and make the corresponding sub-pixels emit light. Generally, in the process of displaying a frame of image, the display panel outputs scanning signals from the first scanning line to multiple scanning lines one by one, so as to control multiple sub-pixels to emit light row by row.

In the related art, when the display panel displays a frame of image, the polarity of the data voltage output by each data line relative to the common voltage remains unchanged. When the display panel displays two adjacent frames of images, the polarity of the data voltage output by each data line relative to the common voltage changes.

However, when the polarity of the data voltage output by the data line changes with respect to the common voltage, the voltage value of the data voltage changes greatly. At the same time, due to the resistance of the data line, the change of the voltage value of the data voltage is affected, which will cause the first scan line During the process of outputting the scan signal, the amount of charge charged by the data lines to the sub-pixels is not as high as that required for the sub-pixels to emit light, thus resulting in dim luminance of the sub-pixels connected to the first scan line in the display panel.

technical problem

One of the purposes of the embodiments of the present application is to provide an array substrate, a display panel, and a display device, which can increase the charging capacity of the sub-pixels connected to the first scanning line in the display panel, thereby increasing the charging capacity of the sub-pixels connected to the first scanning line. Luminance of connected sub-pixels.

technical solution

In a first aspect, an array substrate is provided, including:

N×M pixel groups, the N×M pixel groups are arranged in N rows and M columns;

The pixel group includes at least one sub-pixel module, the sub-pixel module includes a switch circuit and sub-pixels correspondingly connected to the switch circuit, the switch circuit in each sub-pixel module is connected to a data line, and each The switch circuits in each of the sub-pixel modules are connected to one scan line; the switch circuits in different pixel groups in the same row are connected to different data lines, and all the switch circuits in the pixel groups in different rows are connected to different data lines. The switch circuits are connected to different scan lines; the scan lines connected to a plurality of switch circuits connected to the same data line are different;

The scanning lines include a first scanning line, and the first scanning line is the first scanning line that outputs a scanning signal when the array substrate is working;

The switch circuit includes a first switch circuit connected to the first scan line, each of the first switch circuits includes a plurality of transistors, and each of the control electrodes of the plurality of transistors in the first switch circuit are all connected to the first scan line, the first poles of the multiple transistors in each of the first switch circuits are connected to the same data line, and the first poles of the multiple transistors in each of the first switch circuits The second poles are all connected to the corresponding sub-pixels of the first switch circuit.

Optionally, each of the sub-pixels includes one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and when the pixel group includes two sub-pixel modules, the first scan line The sub-pixels connected to the connected first switch circuit include all of the green sub-pixels located in the first row and half of the red sub-pixels located in the first row.

Optionally, each of the sub-pixels includes one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and when the pixel group includes three sub-pixel modules, the first scan line The sub-pixel connected to the connected first switch circuit is the green sub-pixel.

Optionally, the sub-pixels connected to the first switch circuit connected to the first scan line are arranged at intervals.

Optionally, the scan lines include a second scan line, and the second scan line is a second scan line that outputs a scan signal when the array substrate is in operation;

The switch circuit also includes a second switch circuit connected to the second scan line, each of the second switch circuits includes a plurality of transistors, and the control of the plurality of transistors in each of the second switch circuits The poles are all connected to the second scanning line, the first poles of the multiple transistors in each of the second switch circuits are connected to the same data line, and the multiple transistors in each of the second switch circuits The second poles of each are connected to the sub-pixels corresponding to the second switch circuit.

Optionally, the number of transistors in the second switch circuit is smaller than the number of transistors in the first switch circuit.

Optionally, a channel width-to-length ratio of at least one transistor in the first switch circuit is greater than a channel width-to-length ratio of at least one transistor in the second switch circuit.

The second aspect provides a display panel, including the array substrate, the color filter substrate and the liquid crystal layer as described in the first aspect;

The array substrate is disposed opposite to the color filter substrate, and the liquid crystal layer is located between the array substrate and the color filter substrate.

In a third aspect, a display device is provided, including the display panel as described in the second aspect.

Beneficial effect

In the present application, the array substrate includes N×M pixel groups. Each pixel group includes at least one sub-pixel module, and each sub-pixel module includes a switch circuit and a sub-pixel connected to the switch circuit. Wherein, the switch circuit in each sub-pixel module is connected to a data line, the switch circuit in each sub-pixel module is connected to a scan line, and connected to the scan line connected to multiple switch circuits of the same data line different. In the array substrate, the switch circuits connected to the first scan line are first switch circuits, and each first switch circuit includes a plurality of transistors. The control poles of the multiple transistors in each first switch circuit are connected to the first scan line, the first poles of the multiple transistors in each first switch circuit are connected to the same data line, and each first The second poles of the plurality of transistors in the switch circuit are all connected to the corresponding sub-pixels of the first switch circuit. In this way, when the first scan line outputs the scan signal and the data line charges the sub-pixels corresponding to the first switch circuit, each sub-pixel can simultaneously obtain electrical signals through multiple transistors in the connected first switch circuit , so as to increase the charging amount of the sub-pixel corresponding to the first switch circuit, thereby increasing the luminous brightness of the sub-pixel connected to the first scanning line in the display panel to which the array substrate is applied.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings that need to be used in the embodiments or exemplary technical descriptions. Obviously, the accompanying drawings in the following descriptions are only for this application. For some embodiments, those skilled in the art can also obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a circuit structure diagram of the first array substrate provided in Embodiment 1 of the present application;

FIG. 2 is a circuit structure diagram of a second array substrate provided in Embodiment 1 of the present application;

FIG. 3 is a circuit structure diagram of a third array substrate provided in Embodiment 1 of the present application;

FIG. 4 is a circuit structure diagram of a fourth array substrate provided in Embodiment 1 of the present application;

FIG. 5 is a circuit structure diagram of a fifth array substrate provided in Embodiment 1 of the present application;

FIG. 6 is a circuit structure diagram of a sixth array substrate provided in Embodiment 1 of the present application;

Fig. 7 is the enlarged view of the circuit structure of C area in Fig. 4;

Fig. 8 is an enlarged view of the circuit structure of the first D area in Fig. 4;

Fig. 9 is an enlarged view of the first switch circuit in Fig. 7;

FIG. 10 is a circuit structure diagram of a seventh array substrate provided in Embodiment 1 of the present application;

Fig. 11 is the enlarged view of the circuit structure of the second D area in Fig. 4;

FIG. 12 is a schematic structural diagram of the first transistor provided in Embodiment 1 of the present application;

FIG. 13 is a schematic structural diagram of a second type of transistor provided in Embodiment 1 of the present application;

FIG. 14 is a schematic structural diagram of a display panel provided in Embodiment 2 of the present application.

Among them, the meanings represented by the symbols in the drawings are respectively:

10. Array substrate; 12. Pixel group; 14. Sub-pixel module; 110. Sub-pixel; 120. Switch circuit; 122. First switch circuit; 124. Second switch circuit; 126. Third switch circuit; 130. Data line; 140, scanning line; 20, display panel; 210, color filter substrate; 220, liquid crystal layer.

Embodiments of the present invention

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, not to limit the present application.

It should be understood that the "plurality" mentioned in this application means two or more. In the description of this application, unless otherwise specified, "/" means or means, for example, A/B can mean A or B; "and/or" in this article is just a description of the relationship between associated objects, It means that there can be three kinds of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in order to clearly describe the technical solution of the present application, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect. Those skilled in the art can understand that words such as "first" and "second" do not limit the number and execution order, and before explaining the embodiment of the present application in detail, the application scenario of the embodiment of the present application will be described first.

The display panel includes an array substrate and a backlight. The array substrate includes a plurality of scanning lines, a plurality of data lines, a plurality of sub-pixels, and a plurality of switch circuits corresponding to the plurality of sub-pixels. When the display panel is working, the scanning line control switch circuit is turned on. The data lines write electrical signals into the corresponding sub-pixels through the switch circuit, charge the sub-pixels, and make the corresponding sub-pixels emit light. Generally, when the display panel displays a frame of image, a plurality of scanning lines starting from the first scanning line output scanning signals one by one, so as to control a plurality of sub-pixels to emit light row by row.

In the related art, when the display panel displays a frame of image, the polarity of the data voltage output by each data line relative to the common voltage remains unchanged. When the display panel displays two adjacent frames of images, the polarity of the data voltage output by each data line relative to the common voltage changes. Wherein, the polarity of the data voltage relative to the common voltage refers to the magnitude of the data voltage relative to the common voltage. When the display panel displays a frame of image, the data voltage output by one of the multiple data lines can be always greater than the common voltage; when the display panel displays the next frame of image, the polarity of the data voltage relative to the common voltage changes, which The data voltage output by a data line can be always lower than the common voltage.

For this reason, embodiments of the present application provide an array substrate and a display panel, which can increase the luminance of sub-pixels connected to the first scanning line in the display panel, thereby improving the display effect of the display panel.

Embodiment one:

The array substrate provided by the embodiment of the present application will be explained in detail below.

1 to 6 are circuit structure diagrams of various array substrates 10 provided by the embodiments of the present application. As shown in FIGS. 1 to 6 , the array substrate 10 includes N×M pixel groups 12 . N×M pixel groups 12 are arranged in N rows and M columns. Each pixel group 12 includes at least one sub-pixel module 14 . Wherein, in the embodiment shown in Figure 1 and Figure 2, each pixel group 12 includes a sub-pixel module 14; in the embodiment shown in Figure 3 and Figure 4, each pixel group 12 includes two sub-pixel modules 14; In the embodiment shown in FIG. 5 and FIG. 6 , each pixel group 12 includes three sub-pixel modules 14 .

Each sub-pixel module 14 includes a switch circuit 120 and a sub-pixel 110 connected to the switch circuit 120 . The switch circuit 120 in each sub-pixel module 14 is connected to one data line 130 , and the switch circuit 120 in each sub-pixel module 14 is connected to one scan line 140 . Switch circuits 120 in different pixel groups 12 in the same row are connected to different data lines 130 . The switch circuits 120 in the pixel groups 12 in different rows are connected to different scan lines 140 . Meanwhile, the scan lines 140 connected to the plurality of switch circuits 120 connected to the same data line 130 are different.

Firstly, the circuit structure of the array substrate 10 provided by the embodiment of the present application will be explained in detail with reference to FIG. 1 to FIG. 6 . As shown in FIGS. 1 to 6 , the array substrate 10 includes N×L sub-pixels 110 , N×L switch circuits 120 , L/X data lines 130 and N×X scan lines 140 . N, L, X, L/X and N×X are all positive integers. Wherein, X is the number of sub-pixel modules 14 included in each pixel group 12, and L/X is equal to M.

The array substrate 10 includes L/X data lines 130 and N×X scan lines 140 . Each of the L/X data lines 130 extends in the column direction. Each of the N×X scan lines 140 extends along the row direction. The row direction here refers to the direction parallel to the horizontal plane on the paper, and the column direction here refers to the direction perpendicular to the row direction on the paper. The array substrate 10 further includes N×L sub-pixels 110 and N×L switch circuits 120 . N×L sub-pixels 110 are arranged in N rows and L columns. The N×L switch circuits 120 are connected to the N×L sub-pixels 110 in one-to-one correspondence. One switch circuit 120 and one sub-pixel 110 in one-to-one correspondence constitute a sub-pixel module 14 .

Each switch circuit 120 has an input terminal, an output terminal and a control terminal. The control terminal of the switch circuit 120 is used to control the conduction and disconnection between the input terminal and the output terminal of the switch circuit 120 . In the N×L switch circuits 120, the input end of each switch circuit 120 is connected to a data line 130, the control end of each switch circuit 120 is connected to a scan line 140, and the output end of each switch circuit 120 is connected to a scanning line 140. The corresponding sub-pixels 110 are connected. When the scan line 140 outputs a scan signal, all the switch circuits 120 connected to the scan line 140 are turned on. When the switch circuit 120 is turned on, the data voltage in the data line 130 can be output to the sub-pixel 110 connected to the switch circuit 120 through the switch circuit 120 , so that the sub-pixel 110 can emit light. Generally, a plurality of switch circuits 120 connected to the same data line 130 are connected to different scan lines 140 , so that each sub-pixel 110 can input a data voltage independently.

Each sub-pixel 110 may include a pixel electrode, and may also include a color resistor on the pixel electrode. The pixel electrode is used to form a voltage difference with the common electrode. When there is a voltage difference between the pixel electrode and the common electrode, an electric field is formed between the pixel electrode and the common electrode, and the liquid crystal rotates under the action of the electric field, thereby realizing light emission. Generally, the voltage of the common electrode is fixed, and the data voltage in the data line 130 is used to output to the pixel electrode.

The circuit structure of the array substrate 10 will be explained below with reference to the drawings and specific embodiments.

In a first possible implementation, X may be equal to one. Taking L equal to 12 and N equal to 4 as an example, the circuit structure of the array substrate 10 may be as shown in FIG. 1 . In the embodiment shown in FIG. 1 , the array substrate 10 includes 48 sub-pixels 110 , 48 switch circuits 120 , 12 data lines 130 and 4 scan lines 140 . Among them, the 48 sub-pixels 110 are arranged in 4 rows and 12 columns, and the 48 sub-pixels 110 include 16 red (Red, R) sub-pixels, 16 green (Green, G) sub-pixels and 16 blue (Blue, B) sub-pixels sub-pixel. The switch circuits 120 correspond to the sub-pixels 110 one by one, and the output end of each switch circuit 120 is connected to one sub-pixel 110 . A switch circuit 120 connected with a sub-pixel 110 constitutes a sub-pixel module 14 . Each pixel group 12 includes a sub-pixel module 14 . For ease of description, the 12 data lines 130 are respectively called D1, D2...D12, and the 4 scan lines 140 are called G1, G2, G3 and G4 respectively. Each data line 130 extends along a column direction, and each scan line 140 extends along a row direction. Wherein, the control terminals of the switch circuits 120 corresponding to the sub-pixels 110 in the first row are all connected to G1, and the control terminals of the switch circuits 120 corresponding to the sub-pixels 110 in the second row are all connected to G2...the switches corresponding to the sub-pixels 110 in the fourth row The control terminals of the circuit 120 are all connected to G4. The input terminals of the switch circuits 120 corresponding to the first column of sub-pixels 110 are all connected to D1, the input terminals of the switch circuits 120 corresponding to the second column of sub-pixels 110 are all connected to D2...the input of the switch circuit 120 corresponding to the twelfth column of sub-pixels 110 Both ends are connected with D12.

When the array substrate 10 is working, G1, G2, G3 and G4 output scanning signals in sequence. When G1 outputs the scanning signal, D1 to D12 output the data voltage at the same time, thereby charging the first row of sub-pixels 110; when G2 outputs the scanning signal, D1 to D12 simultaneously output the data voltage, thereby charging the second row of sub-pixels 110... In the process of displaying a frame of image, the polarity of the data voltage output by each data line 130 relative to the common voltage remains unchanged. Taking the common voltage as 0V and the array substrate 10 being used to display a solid-color image (that is, the gray scale of each sub-pixel 110 is the same) as an example, when displaying the first frame of image, the data voltage output by D1 can be constant equal to 7V, and the output voltage of D2 can be equal to 7V. The data voltage can be constant equal to -7V, the data voltage output by D3 can be constant equal to 7V... the data voltage output by D12 can be constant equal to -7V. When displaying the second frame of image, the data voltage output by D1 can be constant equal to -7V, the data voltage output by D2 can be constant equal to 7V, the data voltage output by D3 can be constant equal to -7V... the data voltage output by D12 can be constant equal to 7V .

In the embodiment shown in FIG. 1 , all switch circuits 120 in pixel groups 12 located in different rows and in the same column may be connected to the same data line 130 . The array substrate 10 shown in FIG. 1 can also be transformed into the array substrate 10 shown in FIG. 2 . In the embodiment shown in Fig. 2, D1 is split into D1-A and D1-B. The input terminals of the 12 switch circuits 120 corresponding to the first row of sub-pixels 110 are respectively connected to D1-A to D12, and the input terminals of the 12 switch circuits 120 corresponding to the second row of sub-pixels 110 are respectively connected to D2 to D1-B... ...the input terminals of the 12 switch circuits 120 corresponding to the sub-pixels 110 in the fourth row are respectively connected to D2 to D1-B. In the embodiment shown in FIG. 2 , all switch circuits 120 in pixel groups 12 located in different rows and in the same column may be connected to different data lines 130 .

When the array substrate 10 is working, G1, G2, G3 and G4 output scanning signals in sequence. When G1 outputs the scanning signal, D1-A to D12 output the data voltage at the same time, thereby charging the first row of sub-pixels 110; when G2 outputs the scanning signal, D2 to D1-B simultaneously output the data voltage, thereby charging the second row of sub-pixels 110 Charging... During the process of displaying a frame of image, the polarity of the data voltage output by each data line 130 relative to the common voltage remains unchanged. The data voltages output by two adjacent data lines 130 have different polarities relative to the common voltage. Taking the common voltage as 0V and the array substrate 10 being used to display a solid-color image (that is, the gray scale of each sub-pixel 110 is the same) as an example, when displaying the first frame of image, the output of D1 (including D1-A and D1-B) The data voltage can be constant equal to 7V, the data voltage output by D2 can be constant equal to -7V, the data voltage output by D3 can be constant equal to 7V... the data voltage output by D12 can be constant equal to -7V. When displaying the second frame of image, the data voltage output by D1 (including D1-A and D1-B) can be constant equal to -7V, the data voltage output by D2 can be constant equal to 7V, and the data voltage output by D3 can be constant equal to -7V... ...The data voltage output by D12 can be equal to 7V. In this way, in the process of displaying a frame of image, the polarity of the data voltage of each sub-pixel 110 on the array substrate 10 with respect to the common voltage is different from that of its adjacent upper, lower, left, and right four sub-pixels 110, which improves the display panel. effect of perspective.

In a second possible implementation, X can be equal to 2. Taking L equal to 12 and N equal to 4 as an example, the circuit structure of the array substrate 10 may be as shown in FIG. 3 . In the embodiment shown in FIG. 3 , the array substrate 10 includes 48 sub-pixels 110 , 48 switch circuits 120 , 6 data lines 130 and 8 scan lines 140 . Wherein, the 48 sub-pixels 110 are arranged in 4 rows and 12 columns, and the 48 sub-pixels 110 include 16 red sub-pixels, 16 green sub-pixels and 16 blue sub-pixels. The switch circuits 120 correspond to the sub-pixels 110 one by one, and the output end of each switch circuit 120 is connected to one sub-pixel 110 . A switch circuit 120 connected with a sub-pixel 110 constitutes a sub-pixel module 14 . Each pixel group 12 includes two sub-pixel modules 14 . For ease of description, the six data lines 130 are respectively called D1, D2...D6, and the eight scan lines 140 are respectively called G1, G2...G8. Each data line 130 extends along a column direction, and each scan line 140 extends along a row direction. Wherein, the control terminals of the switch circuits 120 corresponding to the first row of sub-pixels 110 are connected to G1 and G2, and the input terminals of the two switch circuits 120 respectively connected to G1 and G2 can be connected to the same data line 130; the second row of sub-pixels The control terminal of the switch circuit 120 corresponding to 110 is connected to G3 and G4, and the input terminals of the two switch circuits 120 respectively connected to G3 and G4 can be connected to the same data line 130...the switch circuit 120 corresponding to the fourth row of sub-pixels 110 The control terminals of the two switch circuits 120 connected to G7 and G8 respectively can be connected to the same data line 130 .

When the array substrate 10 is working, G1 , G2 . . . G8 sequentially output scanning signals. When G1 outputs the scanning signal, D1 to D6 output the data voltage at the same time, thereby charging the first, fourth, sixth, seventh, tenth, and twelfth sub-pixels 110 in the first row; G2 When outputting the scan signal, D1 to D6 simultaneously output the data voltage, thereby charging the second, third, fifth, eighth, ninth, and eleventh sub-pixels 110 in the first row... During the process of displaying a frame of image, the polarity of the data voltage output by each data line 130 relative to the common voltage remains unchanged. Taking the common voltage as 0V and the array substrate 10 being used to display a solid-color image (that is, the gray scale of each sub-pixel 110 is the same) as an example, when displaying the first frame of image, the data voltage output by D1 can be constant equal to 7V, and the output voltage of D2 can be equal to 7V. The data voltage can be constant equal to -7V, the data voltage output by D3 can be constant equal to 7V... the data voltage output by D6 can be constant equal to -7V. When displaying the second frame of image, the data voltage output by D1 can be constant equal to -7V, the data voltage output by D2 can be constant equal to 7V, the data voltage output by D3 can be constant equal to -7V... the data voltage output by D6 can be constant equal to 7V .

In the embodiment shown in FIG. 3 , all switch circuits 120 in pixel groups 12 located in different rows and in the same column may be connected to the same data line 130 . The array substrate 10 shown in FIG. 3 can also be transformed into the array substrate 10 shown in FIG. 4 . In the embodiment shown in Fig. 4, D1 is split into D1-A and D1-B. The input terminals of the 12 switch circuits 120 corresponding to the sub-pixels 110 in the first row are connected to D1-A to D6, and the input terminals of the 12 switch circuits 120 corresponding to the sub-pixels 110 in the second row are connected to D2 to D1-B... The input terminals of the 12 switch circuits 120 corresponding to the four rows of sub-pixels 110 are connected to D2 to D1-B. In the embodiment shown in FIG. 4 , all switch circuits 120 in pixel groups 12 located in different rows and in the same column may be connected to different data lines 130 .

When the array substrate 10 is working, G1 , G2 . . . G8 sequentially output scanning signals. When G1 outputs the scan signal, D1-A to D6 output the data voltage at the same time, thereby charging the first, fourth, sixth, seventh, tenth, and twelfth sub-pixels 110 in the first row ; When G2 outputs the scanning signal, D1-A to D6 output the data voltage at the same time, so that the second, third, fifth, eighth, ninth and eleventh sub-pixels in the first row 110 charging; when G3 outputs the scan signal, D2 to D1-B output the data voltage at the same time, so that the first, fourth, sixth, seventh, tenth, and twelfth subs in the second row The pixel 110 is charged; when G4 outputs the scan signal, D2 to D1-B output the data voltage at the same time, so that the second, third, fifth, eighth, ninth, and eleventh in the second row Each sub-pixel 110 is charged... During the process of displaying a frame of image, the polarity of the data voltage output by each data line 130 relative to the common voltage remains unchanged. The data voltages output by two adjacent data lines 130 have different polarities relative to the common voltage. Taking the common voltage as 0V and the array substrate 10 being used to display a solid-color image (that is, the gray scale of each sub-pixel 110 is the same) as an example, when displaying the first frame of image, the output of D1 (including D1-A and D1-B) The data voltage can be constant equal to 7V, the data voltage output by D2 can be constant equal to -7V, the data voltage output by D3 can be constant equal to 7V... the data voltage output by D6 can be constant equal to -7V. When displaying the second frame of image, the data voltage output by D1 (including D1-A and D1-B) can be constant equal to -7V, the data voltage output by D2 can be constant equal to 7V, and the data voltage output by D3 can be constant equal to -7V... ...The data voltage output by D6 can be equal to 7V. In this way, when the array substrate 10 displays a frame of image, the polarity of the data voltage of each sub-pixel 110 relative to the common voltage is different from that of its adjacent upper, lower, left, and right sub-pixels 110, which improves the performance of the display panel. The effect of perspective.

In a third possible implementation, X may be equal to three. Taking L equal to 12 and N equal to 3 as an example, the circuit structure of the array substrate 10 can be shown in FIG. 5 . In the embodiment shown in FIG. data lines 130 and nine scan lines 140. Wherein, the 36 sub-pixels 110 are arranged in 3 rows and 12 columns, and the 36 sub-pixels 110 include 12 red sub-pixels, 12 green sub-pixels and 12 blue sub-pixels. The switch circuits 120 correspond to the sub-pixels 110 one by one, and the output end of each switch circuit 120 is connected to one sub-pixel 110 . A switch circuit 120 connected with a sub-pixel 110 constitutes a sub-pixel module 14 . Each pixel group 12 includes three sub-pixel modules 14 . For ease of description, the four data lines 130 are respectively called D1, D2, D3, D4, and the nine scanning lines 140 are called G1, G2...G9, respectively. Each data line 130 extends along a column direction, and each scan line 140 extends along a row direction. Wherein, the control terminals of the switch circuits 120 corresponding to the first row of sub-pixels 110 are connected to G1, G2 and G3, and the input terminals of the three switch circuits 120 respectively connected to G1, G2 and G3 can be connected to the same data line 130... The control terminals of the switch circuits 120 corresponding to the sub-pixels 110 in the third row are connected to G7, G8 and G9, and the input terminals of the three switch circuits 120 respectively connected to G7, G8 and G9 can be connected to the same data line 130 .

When the array substrate 10 is working, G1, G2...G9 sequentially output scanning signals. When G1 outputs the scanning signal, D1 to D4 output the data voltage at the same time, thereby charging the first, fourth, seventh and tenth sub-pixels 110 in the first row; when G2 outputs the scanning signal, D1 to D4 simultaneously output data voltage, thereby charging the second, fifth, eighth and eleventh sub-pixels 110 in the first row; when G3 outputs the scan signal, D1 to D4 simultaneously output the data voltage, thereby charging the first The third, sixth, ninth and twelfth sub-pixels 110 in the row are charged... During the process of displaying a frame of images, the polarity of the data voltage output by each data line 130 relative to the common voltage remains different. Change. Taking the common voltage as 0V and the array substrate 10 being used to display a solid-color image (that is, the gray scale of each sub-pixel 110 is the same) as an example, when displaying the first frame of image, the data voltage output by D1 can be constant equal to 7V, and the output voltage of D2 can be equal to 7V. The data voltage can be equal to -7V, the data voltage output by D3 can be equal to 7V, and the data voltage output by D4 can be equal to -7V. When displaying the second frame of image, the data voltage output by D1 can be constant equal to -7V, the data voltage output by D2 can be constant equal to 7V, the data voltage output by D3 can be constant equal to -7V, and the data voltage output by D4 can be constant equal to 7V.

In the embodiment shown in FIG. 5 , all switch circuits 120 in pixel groups 12 located in different rows and in the same column may be connected to the same data line 130 . The array substrate 10 shown in FIG. 5 can also be transformed into the array substrate 10 shown in FIG. 6 . In the embodiment shown in FIG. 6, D1 is split into D1-A and D1-B. The input terminals of the 12 switch circuits 120 corresponding to the first row of sub-pixels 110 are connected to D1-A to D4, the input terminals of the 12 switch circuits 120 corresponding to the second row of sub-pixels 110 are connected to D2 to D1-B, and the third The input terminals of the 12 switch circuits 120 corresponding to the row sub-pixels 110 are connected to D1-A to D4. In the embodiment shown in FIG. 6 , all switch circuits 120 in pixel groups 12 located in different rows and in the same column may be connected to different data lines 130 .

When the array substrate 10 is working, G1, G2...G9 sequentially output scanning signals. When G1 outputs the scan signal, D1-A to D4 simultaneously output the data voltage, thereby charging the first, fourth, sixth, seventh, tenth, and twelfth sub-pixels 110 in the first row ; When G2 outputs the scanning signal, D1-A to D6 output the data voltage at the same time, so that the second, third, fifth, eighth, ninth and eleventh sub-pixels in the first row 110 charging... When G4 outputs the scan signal, D2 to D1-B output the data voltage at the same time, so that the first, fourth, sixth, seventh, tenth, twelfth in the second row sub-pixels 110 are charged; when G5 outputs the scan signal, D2 to D1-B simultaneously output the data voltage, thus the second, third, fifth, eighth, ninth, tenth in the second row One sub-pixel 110 is charged... During the process of displaying one frame of image, the polarity of the data voltage output by each data line 130 relative to the common voltage remains unchanged. The data voltages output by two adjacent data lines 130 have different polarities relative to the common voltage. Taking the common voltage as 0V and the array substrate 10 being used to display a solid-color image (that is, the gray scale of each sub-pixel 110 is the same) as an example, when displaying the first frame of image, the output of D1 (including D1-A and D1-B) The data voltage can be equal to 7V, the data voltage output by D2 can be equal to -7V, the data voltage output by D3 can be equal to 7V, and the data voltage output by D4 can be equal to -7V. When displaying the second frame of image, the data voltage output by D1 (including D1-A and D1-B) can be equal to -7V, the data voltage output by D2 can be equal to 7V, and the data voltage output by D3 can be equal to -7V. The data voltage output by D4 can be equal to 7V. In this way, when the array substrate 10 displays a frame of image, the polarity of the data voltage of each sub-pixel 110 relative to the common voltage is different from that of its adjacent upper, lower, left, and right sub-pixels 110, which improves the performance of the display panel. The effect of perspective.

FIG. 7 is an enlarged view of a circuit structure in region C in FIG. 4 provided by an embodiment of the present application, and FIG. 8 is an enlarged view of a circuit structure in region D in FIG. 4 provided by an embodiment of the present application. As shown in FIG. 7 and FIG. 8 , in the embodiment of the present application, all the switch circuits 120 connected to the first scan line among the N×X scan lines 140 are referred to as first switch circuits 122 . In other words, the N×L switch circuits 120 include L/X first switch circuits 122 connected to the first scan line of the N×X scan lines 140 . Here, the first scan line refers to the first scan line 140 that outputs scan signals when the array substrate 10 is in operation, that is, G1 in the embodiments shown in FIGS. 1 to 6 . FIG. 9 is an enlarged view of the first switch circuit 122 in FIG. 7 provided by the embodiment of the present application. As shown in FIGS. 7 to 9 , each first switch circuit 122 includes a plurality of transistors. A plurality here refers to two or more than two integers. Each transistor includes a control electrode, a first electrode and a second electrode. Wherein, the first pole of the transistor is used for inputting electrical signals, the second pole of the transistor is used for outputting electrical signals, and the control pole of the transistor is used for controlling on and off between the first pole and the second pole. When the transistor is a MOS (metal oxide semiconductor, metal oxide semiconductor) field effect transistor, the first pole of the transistor can be the drain of an N-type MOS transistor or the source of a P-type MOS transistor; the second pole of the transistor can be an N-type MOS transistor. The source of the P-type MOS tube or the drain of the P-type MOS tube; the control electrode of the transistor can be the gate G of the MOS tube. In some other embodiments, the transistor can also be a one-way thyristor, at this time, the first pole of the transistor can be the anode of the one-way thyristor, and the second pole of the transistor can be the cathode of the one-way thyristor, The control pole of the transistor is the control pole of the one-way thyristor. In each embodiment of the present application, taking the transistor as a P-type MOS transistor as an example, the gates G of multiple transistors in each first switch circuit 122 are connected to the first scanning line, and each first switch circuit 122 The sources S of the plurality of transistors in the circuit 122 are all connected to the same data line 130 , and the drains D of the plurality of transistors in each first switch circuit 122 are connected to the corresponding sub-pixel 110 .

For example, in the embodiment shown in FIG. 8, the three first switch circuits 122 connected to G1 (that is, the first scanning line) correspond to the first, fourth and sixth sub-pixels 110 in the first row respectively, Each first switch circuit 122 includes two transistors. For "the first switch circuit 122 connected to the first sub-pixel 110 in the first row", the gates G of the two transistors in the first switch circuit 122 are connected to G1, and the sources S of the two transistors are connected to D1 is connected, and the drains D of the two transistors are both connected to the first sub-pixel 110 in the first row. For "the first switch circuit 122 connected to the fourth sub-pixel 110 in the first row", the gates G of the two transistors in the first switch circuit 122 are both connected to G1, and the sources S of the two transistors are both connected to D2 The drains D of the two transistors are both connected to the fourth sub-pixel 110 in the first row. For "the first switch circuit 122 connected to the sixth sub-pixel 110 in the first row", the gates G of the two transistors in the first switch circuit 122 are connected to G1, and the sources S of the two transistors are connected to D3 connected, the drains D of the two transistors are both connected to the sixth sub-pixel 110 in the first row. In this way, when G1 outputs the scan signal and the data line 130 charges the sub-pixel 110 corresponding to the first switch circuit 122, each sub-pixel 110 can simultaneously obtain electrical signals through multiple transistors in the corresponding first switch circuit 122 , so as to increase the charging amount of the sub-pixel 110 corresponding to the first switch circuit 122 , thereby increasing the luminance of the sub-pixel 110 connected to the first scanning line in the display panel applied to the array substrate 10 .

In some embodiments, as shown in FIG. 3 and FIG. 4 , N×L sub-pixels 110 include red sub-pixels, green sub-pixels and blue sub-pixels, wherein the red sub-pixel refers to a sub-pixel for emitting red light 110, the green sub-pixel refers to the sub-pixel 110 for emitting green light, and the blue sub-pixel refers to the sub-pixel 110 for emitting blue light. When X is equal to 2, that is, when each pixel group 12 includes two sub-pixel modules 14, the L/X switch circuits 120 connected to the first scan line in the N×X scan lines 140 (that is, the first switch circuit 122 ) corresponding to the sub-pixel 110 includes all of the green sub-pixels located in the first row, and half of the red sub-pixels located in the first row. In other words, the control terminals of the switch circuits 120 connected to all the green sub-pixels in the first row are connected to G1, and the control terminals of the switch circuits 120 connected to half of all the blue sub-pixels in the first row are connected to G1. At this time, the arrangement order of the red sub-pixels, green sub-pixels and blue sub-pixels may be as shown in FIG. 3 and FIG. 4 . Generally, the brightness of the green sub-pixel is about 7.7 times of the brightness of the red sub-pixel, and the brightness of the green sub-pixel is about 4.4 times of the brightness of the blue sub-pixel, so all the green sub-pixels in the first row correspond to the switch circuit 120 The control terminals of the control terminals are all connected to G1, which can increase the brightness of the sub-pixel 110 connected to G1, thereby avoiding the problem that the sub-pixel 110 connected to the first scanning line has a relatively dark luminance, and improving the display of the display panel applied to the array substrate 10. Effect. In some other embodiments, as shown in FIG. 10, when X is equal to 2, the L/X switch circuits 120 connected to the first scan line in the N×X scan lines 140 (that is, the first switch circuit 122 ) may also include all of the green sub-pixels located in the first row and half of the blue sub-pixels located in the first row. At this time, the arrangement order of the red sub-pixels, green sub-pixels and blue sub-pixels may be as shown in FIG. 10 .

Further, as shown in FIG. 3 and FIG. 4 , the subpixels 110 connected to the L/X switch circuits 120 (that is, the first switch circuits 122 ) connected to the first scan line among the N×X scan lines 140 Arranged at intervals. Taking Fig. 3 and Fig. 4 as an example, the spaced arrangement here means that in the first row of sub-pixels 110, at least two sub-pixels 110 corresponding to the first switch circuits 122 have a switch circuit 120 connected to G2 between them. of sub-pixels 110 . Generally, since the scan line 140 connected to the sub-pixel 110 in the first row includes G1 and G2, in the case that the switch circuit 120 corresponding to the green sub-pixel is connected to G1, the sub-pixel 110 corresponding to the first switch circuit 122 can be The intervals are set as far as possible, so as to reduce the problem of the low brightness of the sub-pixels 110 connected to the first scanning line from the visual effect.

In some embodiments, as shown in FIG. 5 and FIG. 6 , the N×L sub-pixels 110 include red sub-pixels, green sub-pixels and blue sub-pixels. When X is equal to 3, that is, when each pixel group 12 includes three sub-pixel modules 14, the L/X switch circuits 120 connected to the first scan line in the N×X scan lines 140 (that is, the first switch circuit 122 ) corresponding sub-pixels 110 include only green sub-pixels. In other words, the control terminals of the switch circuit 120 connected to all the green sub-pixels in the first row are connected to G1. In this way, the luminance of the sub-pixel 110 connected to G1 can be increased, thereby avoiding the problem of low luminance of the sub-pixel 110 connected to the first scanning line, and improving the display effect of the display panel applied to the array substrate 10 .

Further, as shown in FIG. 5 and FIG. 6, the interval between the sub-pixels 110 corresponding to the L/X switch circuits 120 (that is, the first switch circuits 122) connected to the first scan line of the N×X scan lines 140 is arranged. Taking FIG. 5 and FIG. 6 as an example, the spaced arrangement here means that in the first row of sub-pixels 110, there is a switch connected to G2 or/and G3 between the sub-pixels 110 corresponding to at least two first switch circuits 122 The circuit 120 corresponds to the sub-pixel 110 . Generally, since the scan lines 140 connected to the sub-pixels 110 in the first row include G1, G2, and G3, the switch circuit 120 corresponding to the green sub-pixel in the sub-pixels 110 in the first row can be connected to G1, and the sub-pixels in the first row The switch circuit 120 corresponding to the red sub-pixel in 110 may be connected to G2, and the switch circuit 120 corresponding to the blue sub-pixel in the first row of sub-pixels 110 may be connected to G3. The green sub-pixels, blue sub-pixels and red sub-pixels are arranged circularly in sequence. The red sub-pixels connected to the first switch circuit 122 are arranged at intervals, which can visually reduce the problem that the sub-pixels 110 connected to the first scanning line have relatively low luminance.

FIG. 11 is an enlarged view of another circuit structure in area D in FIG. 4 provided by an embodiment of the present application. As shown in FIG. 11 , in the embodiment of the present application, the L/X switch circuits 120 connected to the second scan line among the N×X scan lines 140 are referred to as second switch circuits 124 . In other words, the N×L switch circuits 120 include L/X second switch circuits 124 connected to the second scan line of the N×X scan lines 140 . The second scanning line here refers to the second scanning line 140 outputting scanning signals when the array substrate 10 is in operation, that is, G2 in the embodiments shown in FIGS. 1 to 6 . Each second switch circuit 124 also includes a plurality of transistors. A plurality here refers to two or more than two integers. The gates G (not marked in the figure) of multiple transistors in each second switch circuit 124 are connected to the second scanning line, and the sources S (not marked in the figure) of multiple transistors in each second switch circuit 124 ) are all connected to the same data line 130 , and the drains D (not marked in the figure) of multiple transistors in each second switch circuit 124 are connected to the corresponding sub-pixel 110 of the second switch circuit 124 . The sub-pixel 110 corresponding to the second switch circuit 124 refers to the sub-pixel 110 that forms a sub-pixel module 14 together with the second switch circuit 124 .

For example, in the embodiment shown in FIG. 11 , the three second switch circuits 124 connected to G2 (that is, the second scanning line) respectively correspond to the second, third and fifth sub-pixels 110 of the first row, Each second switch circuit 124 includes two transistors. For "the second switch circuit 124 connected to the second sub-pixel 110 in the first row", the gates G of the two transistors in the second switch circuit 124 are both connected to G2, and the sources S of the two transistors are both connected to D1 connected, the drains D of the two transistors are both connected to the second sub-pixel 110 in the first row. For "the second switch circuit 124 connected to the third sub-pixel 110 in the first row", the gates G of the two transistors in the second switch circuit 124 are connected to G2, and the sources S of the two transistors are connected to D2 The drains D of the two transistors are both connected to the third sub-pixel 110 in the first row. For "the second switch circuit 124 connected to the fifth sub-pixel 110 in the first row", the gates G of the two transistors in the second switch circuit 124 are connected to G2, and the sources S of the two transistors are both connected to D3 , the drains D of the two transistors are both connected to the fifth sub-pixel 110 in the first row. In this way, when G2 outputs the scan signal and the data line 130 charges the sub-pixel 110 corresponding to the second switch circuit 124, each sub-pixel 110 can simultaneously obtain electrical signals through multiple transistors in the corresponding second switch circuit 124 , so as to increase the charging amount of the sub-pixel 110 corresponding to the second switch circuit 124 . When the array substrate 10 is applied to a display panel, it can avoid the problem that the scanning time of each scanning line 140 is shortened as the display panel switches to a high refresh rate, thereby causing the sub-pixel 110 connected to G2 to have a darker luminance.

In some embodiments, taking the display panel applied to the array substrate 10 that needs to display a solid-color image as an example, the data voltage output by each data line 130 when G1 outputs a scan signal is lower than the data voltage output by each data line 130 when G2 outputs a scan signal . Therefore, the number of transistors in the second switch circuit 124 may be smaller than the number of transistors in the first switch circuit 122 . For example, in the embodiment shown in FIG. 11 , each first switch circuit 122 includes three transistors, and each second switch circuit 124 includes two transistors. In some other unshown embodiments, each first switch includes four transistors, and each second switch circuit 124 includes two transistors. In this way, the brightness difference between the sub-pixels 110 corresponding to the first switch circuit 122 and the sub-pixels 110 corresponding to the second switch circuit 124 can be reduced, thereby improving the display effect of the display panel to which the array substrate 10 is applied.

In some other embodiments, the brightness of the sub-pixel 110 corresponding to the first switch circuit 122 and the sub-pixel 110 corresponding to the second switch circuit 124 can also be reduced by adjusting the channel width-to-length ratio of transistors in different switch circuits 120 Difference. The channel width-to-length ratio here refers to the ratio of the channel width to the channel length of the transistor. For example, when the first switch circuit 122 and the second switch circuit 124 both include two transistors, the channel width-to-length ratio of at least one transistor in the first switch circuit 122 is greater than the channel width of at least one transistor in the second switch circuit 124 The length ratio, so that the charging rate of the first switch circuit 122 is greater than that of the second switch circuit 124 .

For example, FIG. 12 is a schematic structural diagram of a transistor provided in an embodiment of the present application. When the structure of the transistor is as shown in FIG. 12 , it is convenient to increase the channel width-to-length ratio of the transistor by increasing the width W of the transistor. At this time, the channel length L of multiple transistors in the first switch circuit 122 can be set to be equal to the channel length L of multiple transistors in the second switch circuit 124, and the channel width of at least one transistor in the first switch circuit 122 W is larger than the channel width W of the transistor in the second switch circuit 124 . In this way, the channel width-to-length ratio of at least one transistor in the first switch circuit 122 is greater than the channel width-to-length ratio of at least one transistor in the second switch circuit 124 .

As another example, FIG. 13 is a schematic structural diagram of another transistor provided in an embodiment of the present application. When the structure of the transistor is as shown in FIG. 13 , it is convenient to increase the channel width-to-length ratio of the transistor by reducing the length L of the transistor. At this time, the channel width W of multiple transistors in the first switch circuit 122 can be set to be equal to the channel width W of multiple transistors in the second switch circuit 124, and the channel length of at least one transistor in the first switch circuit 122 L is smaller than the channel length L of the transistor in the second switch circuit 124 . In this way, the channel width-to-length ratio of at least one transistor in the first switch circuit 122 is greater than the channel width-to-length ratio of at least one transistor in the second switch circuit 124 .

In some embodiments, referring to FIG. 11 , among the N×L switch circuits 120, the switch circuit 120 connected to the third scan line to the N×X scan line of the N×X scan lines 140 is referred to as the first scan line. Three switch circuits 126 . The N×X scan line is the last scan line. In other words, the N×L switch circuits 120 include the third switch circuit 126 connected to the third scan line to the last scan line among the N×X scan lines 140 . The third scanning line here refers to the third scanning line 140 outputting scanning signals when the array substrate 10 is in operation, that is, G3 in the examples shown in FIGS. 1 to 6 . The last scan line refers to the last scan line 140 outputting scan signals when the array substrate 10 is in operation. Generally, each third switch circuit 126 includes a transistor, and the gate G of the transistor in each third switch circuit 126 is connected to one scan line 140 in the third scan line to the N×X scan line , the source of the transistor in each third switch circuit 126 is connected to one data line 130 , and the drain of the transistor in each third switch circuit 126 is connected to the sub-pixel 110 corresponding to the third switch circuit 126 . The sub-pixel 110 corresponding to the third switch circuit 126 refers to the sub-pixel 110 that forms a sub-pixel module 14 together with the third switch circuit 126 .

For example, in the embodiment shown in FIG. 11 , the three third switch circuits 126 connected to G3 (that is, the third scanning line) respectively correspond to the first, fourth and sixth sub-pixels 110 of the second row, Each third switch circuit 126 includes a transistor. For "the third switch circuit 126 connected to the first sub-pixel 110 in the second row", the gate G (not marked in the figure) of the transistor in the third switch circuit 126 is connected to G3, and the source S (in the figure ) is connected to D2, and the drain D (not marked in the figure) is connected to the first sub-pixel 110 in the second row. For "the third switch circuit 126 connected to the fourth sub-pixel 110 in the second row", the gate G of the transistor in the third switch circuit 126 is connected to G3, the source S is connected to D3, and the drain D is connected to the first The fourth sub-pixels 110 of the two rows are connected. For "the third switch circuit 126 connected to the sixth sub-pixel 110 in the second row", the gate G of the transistor in the third switch circuit 126 is connected to G3, the source S is connected to D4, and the drain D is connected to the first The sixth sub-pixels 110 of the two rows are connected.

The three third switch circuits 126 connected to G4 (ie the fourth scan line) respectively correspond to the second, third and fifth sub-pixels 110 in the second row, and each point switch circuit 120 includes a transistor. For "the third switch circuit 126 connected to the second sub-pixel 110 in the second row", the gate G (not marked in the figure) of the transistor in the third switch circuit 126 is connected to G4, and the source S (in the figure not marked) is connected to D2, and the drain D (not marked in the figure) is connected to the second sub-pixel 110 in the second row. For "the third switch circuit 126 connected to the third sub-pixel 110 corresponding to the second row", the gate G of the transistor in the third switch circuit 126 is connected to G4, the source S is connected to D3, and the drain D is connected to The third sub-pixel 110 of the second row is connected. For "the third switch circuit 126 connected to the fifth sub-pixel 110 in the second row", the gate G of the transistor in the third switch circuit 126 is connected to G4, the source S is connected to D4, and the drain D is connected to the first The fifth sub-pixels 110 of the two rows are connected.

In some embodiments, the channel lengths of the plurality of transistors in the first switch circuit 122 are equal to the channel lengths of the transistors in the third switch circuit 126, and the channel width of at least one transistor in the first switch circuit 122 is greater than The channel width of the transistor in the third switch circuit 126 . Or, the channel widths of the plurality of transistors in the first switch circuit 122 are equal to the channel widths of the transistors in the third switch circuit 126, and the channel length of at least one transistor in the first switch circuit 122 is smaller than that of the third switch circuit. The channel length of the transistor in 126.

In the embodiment of the present application, the array substrate 10 includes N×M pixel groups 12 . Each pixel group 12 includes at least one sub-pixel module 14 , and each sub-pixel module 14 includes a switch circuit 120 and a sub-pixel 110 connected to the switch circuit 120 . Wherein, the switch circuit 120 in each sub-pixel module 14 is connected to one data line 130, the switch circuit 120 in each sub-pixel module 14 is connected to one scan line 140, and the multiple switch circuits 120 connected to the same data line 130 are connected to The scan lines 140 are different. In the array substrate 10, the switch circuits 120 connected to the first scan line are first switch circuits 122, and each first switch circuit 122 includes a plurality of transistors. The gates G of multiple transistors in each first switch circuit 122 are connected to the first scan line, and the sources of multiple transistors in each first switch circuit 122 are connected to the same data line 130. The drains of the multiple transistors in each first switch circuit 122 are all connected to the sub-pixel 110 corresponding to the first switch circuit 122 . In this way, when the first scan line outputs the scan signal and the data line 130 charges the sub-pixel 110 corresponding to the first switch circuit 122 , each sub-pixel 110 can pass through multiple transistors in the corresponding first switch circuit 122 . At the same time, the electric signal is obtained, so as to increase the charging amount of the sub-pixel 110 corresponding to the first switch circuit 122, thereby increasing the luminous brightness of the sub-pixel 110 connected to the first scanning line in the display panel applied to the array substrate 10, and improving the display panel. display effect.

In the embodiment of the present application, the control terminal of the switch circuit 120 corresponding to the green sub-pixel in the first row is connected to G1. In this way, the problem that the sub-pixel 110 connected to the first scanning line is darker can be avoided, and the array can be improved. The display effect of the display panel applied to the substrate 10 . The sub-pixels 110 connected to G1 are arranged at intervals, which can visually reduce the problem that the sub-pixels 110 connected to the first scanning line have relatively low luminance. The second switch circuit 124 connected to the second scan line also includes a plurality of transistors connected in parallel, which can prevent the scan time of each scan line 140 from becoming shorter as the display panel switches to a high refresh rate, thereby causing the sub-circuits connected to G2 to The brightness of the pixel 110 is also relatively dark. The number of transistors in the first switch circuit 122 is greater than the number of transistors in the second switch circuit 124, or the channel width-to-length ratio of at least one transistor in the first switch circuit 122 is greater than that of at least one transistor in the second switch circuit 124 The channel width-to-length ratio can reduce the brightness difference between the sub-pixels 110 corresponding to the first switch circuit 122 and the sub-pixels 110 corresponding to the second switch circuit 124 , thereby improving the display effect of the display panel to which the array substrate 10 is applied.

Embodiment two:

The embodiment of the present application also provides a display panel 20, including the array substrate 10 in any one of the above embodiments.

Specifically, FIG. 14 is a schematic structural diagram of a display panel 20 provided by an embodiment of the present application. As shown in FIG. 14 , the display panel 20 includes an array substrate 10 , a color filter substrate 210 and a liquid crystal layer 220 . The array substrate 10 and the color filter substrate 210 are disposed opposite to each other, and the liquid crystal layer 220 is located between the array substrate 10 and the color filter substrate 210 .

The array substrate 10 includes N×M pixel groups 12 , and the N×M pixel groups 12 are arranged in N rows and M columns. Each pixel group 12 includes at least one sub-pixel module 14 . The sub-pixel module 14 includes a switch circuit 120 and a sub-pixel 110 correspondingly connected to the switch circuit 120 . The switch circuit 120 in each sub-pixel module 14 is connected to one data line 130 , and the switch circuit 120 in each sub-pixel module 14 is connected to one scan line 140 . Switch circuits 120 in different pixel groups 12 located in the same row are connected to different data lines 130 . Switch circuits in pixel groups 12 located in different rows are connected to different scan lines 140 . The scan lines 140 connected to the plurality of switch circuits 120 connected to the same data line 130 are different.

The scan lines 140 include a first scan line, and the first scan line is the first scan line 140 that outputs a scan signal when the array substrate 10 is in operation.

The switch circuit 120 includes first switch circuits 122 connected to the first scan line, and each first switch circuit 122 includes a plurality of transistors. The control poles of the multiple transistors in each first switch circuit 122 are connected to the first scan line, and the first poles of the multiple transistors in each first switch circuit 122 are connected to the same data line 130. The second poles of the plurality of transistors in the first switch circuits 122 are all connected to the sub-pixels 110 corresponding to the first switch circuits.

In some embodiments, each sub-pixel 110 includes one of a red sub-pixel, a green sub-pixel and a blue sub-pixel. When each pixel group 12 includes two sub-pixel modules 14, the sub-pixels 110 connected to the first switch circuit 122 connected to the first scanning line include all the green sub-pixels in the first row, and the green sub-pixels in the first row Half of the red subpixel.

In some embodiments, each sub-pixel 110 includes one of a red sub-pixel, a green sub-pixel and a blue sub-pixel. When each pixel group 12 includes three sub-pixel modules 14, the sub-pixel 110 connected to the first switch circuit 122 connected to the first scan line is a green sub-pixel.

In some embodiments, the sub-pixels 110 connected to the first switch circuit 122 connected to the first scan line are arranged at intervals.

In some embodiments, the scan line 140 includes a second scan line, and the second scan line is the second scan line 140 that outputs a scan signal when the array substrate 10 is working. The switch circuit 120 also includes a second scan line connected to the second scan line. The second switch circuit 124. Each second switch circuit 124 includes a plurality of transistors. The control poles of multiple transistors in each second switch circuit 124 are connected to the second scan line, and the first poles of multiple transistors in each second switch circuit 124 are connected to the same data line 130. The second poles of the plurality of transistors in the second switch circuits 124 are all connected to the corresponding sub-pixels 110 of the second switch circuits 124 .

In some embodiments, the number of transistors in the second switch circuit 124 is smaller than the number of transistors in the first switch circuit 122 .

In some embodiments, the channel width-to-length ratio of at least one transistor in the first switch circuit 122 is greater than the channel width-to-length ratio of at least one transistor in the second switch circuit 124 .

In some embodiments, the channel lengths of the plurality of transistors in the first switch circuit 122 are equal to the channel lengths of the transistors in the second switch circuit 124, and the channel width of at least one transistor in the first switch circuit 122 is greater than the channel width of the transistor in the second switch circuit 124; or,

The channel widths of multiple transistors in the first switch circuit 122 are equal to the channel widths of the transistors in the second switch circuit 124, and the channel length of at least one transistor in the first switch circuit 122 is smaller than that in the second switch circuit 124. The channel length of the transistor.

In some embodiments, the switch circuit 120 includes a third switch circuit 126 connected to the third scan line to the last scan line, each of the third switch circuits 126 includes a transistor, and each of the third switch circuits 126 The control poles of the transistors are all connected to a scan line 140, the first poles of the transistors in each third switch circuit 126 are connected to a data line 130, and the second poles of the transistors in each third switch circuit 126 are connected to the first The three switch circuits 126 correspond to the sub-pixels 110 . The third scan line is the third scan line 140 that outputs scan signals when the array substrate 10 is in operation. The last scan line refers to the last scan line 140 that outputs a scan signal when the array substrate 10 is in operation.

In the embodiment of the present application, the display panel 20 includes the array substrate 10 in the above-mentioned embodiments. The array substrate 10 includes N×M pixel groups 12 . Each pixel group 12 includes at least one sub-pixel module 14 , and each sub-pixel module 14 includes a switch circuit 120 and a sub-pixel 110 connected to the switch circuit 120 . Wherein, the switch circuit 120 in each sub-pixel module 14 is connected to one data line 130, the switch circuit 120 in each sub-pixel module 14 is connected to one scan line 140, and the multiple switch circuits 120 connected to the same data line 130 are connected to The scan lines 140 are different. In the array substrate 10, the switch circuits 120 connected to the first scan line are first switch circuits 122, and each first switch circuit 122 includes a plurality of transistors. The control poles of multiple transistors in each first switch circuit 122 are connected to the first scan line, and the sources of multiple transistors in each first switch circuit 122 are connected to the same data line 130, each The drains of the plurality of transistors in the first switch circuit 122 are all connected to the sub-pixels 110 corresponding to the first switch circuit 122 . In this way, when the first scan line outputs the scan signal and the data line 130 charges the sub-pixel 110 corresponding to the first switch circuit 122 , each sub-pixel 110 can pass through multiple transistors in the corresponding first switch circuit 122 . At the same time, the electrical signal is obtained, so as to increase the charging amount of the sub-pixel 110 corresponding to the first switch circuit 122, thereby increasing the luminous brightness of the sub-pixel 110 connected to the first scanning line in the display panel 20 applied to the array substrate 10, and improving the display. The display effect of the panel 20.

In the embodiment of the present application, the control terminal of the switch circuit 120 corresponding to the green sub-pixel in the first row is connected to G1. In this way, the problem that the sub-pixel 110 connected to the first scanning line is darker can be avoided, and the array can be improved. The display effect of the display panel 20 applied to the substrate 10 . The sub-pixels 110 connected to G1 are arranged at intervals, which can visually reduce the problem that the sub-pixels 110 connected to the first scanning line have relatively low luminance. The second switch circuit 124 connected to the second scan line also includes a plurality of transistors connected in parallel, which can prevent the scan time of each scan line 140 from becoming shorter as the display panel 20 switches to a high refresh rate, thereby causing the The sub-pixel 110 also has a relatively low luminance. The number of transistors in the first switch circuit 122 is greater than the number of transistors in the second switch circuit 124, or the channel width-to-length ratio of at least one transistor in the first switch circuit 122 is greater than that of at least one transistor in the second switch circuit 124 The channel width-to-length ratio can reduce the brightness difference between the sub-pixel 110 corresponding to the first switch circuit 122 and the sub-pixel 110 corresponding to the second switch circuit 124 , thereby improving the display effect of the display panel 20 applied to the array substrate 10 .

Embodiment three:

The embodiment of the present application further provides a display device, including the display panel 20 in any one of the above embodiments.

Specifically, the display panel 20 includes an array substrate 10, and the array substrate 10 includes N×M pixel groups 12, and the N×M pixel groups 12 are arranged in N rows and M columns. Each pixel group 12 includes at least one sub-pixel module 14 . The sub-pixel module 14 includes a switch circuit 120 and a sub-pixel 110 correspondingly connected to the switch circuit 120 . The switch circuit 120 in each sub-pixel module 14 is connected to one data line 130 , and the switch circuit 120 in each sub-pixel module 14 is connected to one scan line 140 . Switch circuits 120 in different pixel groups 12 located in the same row are connected to different data lines 130 . Switch circuits in pixel groups 12 located in different rows are connected to different scan lines 140 . The scan lines 140 connected to the plurality of switch circuits 120 connected to the same data line 130 are different.

In the embodiment of the present application, the array substrate 10 includes N×M pixel groups 12 . Each pixel group 12 includes at least one sub-pixel module 14 , and each sub-pixel module 14 includes a switch circuit 120 and a sub-pixel 110 connected to the switch circuit 120 . Wherein, the switch circuit 120 in each sub-pixel module 14 is connected to one data line 130, the switch circuit 120 in each sub-pixel module 14 is connected to one scan line 140, and multiple switch circuits 120 connected to the same data line 130 are connected to The scan lines 140 are different. In the array substrate 10, the switch circuits 120 connected to the first scan line are first switch circuits 122, and each first switch circuit 122 includes a plurality of transistors. The gates G of the plurality of transistors in each first switch circuit 122 are connected to the first scan line, and the sources of the plurality of transistors in each first switch circuit 122 are connected to the same data line 130, each The drains of the multiple transistors in each first switch circuit 122 are all connected to the sub-pixel 110 corresponding to the first switch circuit 122 . In this way, when the first scan line outputs a scan signal and the data line 130 charges the sub-pixel 110 corresponding to the first switch circuit 122 , each sub-pixel 110 can pass through multiple transistors in the corresponding first switch circuit 122 . At the same time, the electrical signal is obtained, so as to increase the charging amount of the sub-pixel 110 corresponding to the first switch circuit 122, thereby increasing the luminous brightness of the sub-pixel 110 connected to the first scanning line in the display panel applied to the array substrate 10, and improving the display panel. display effect.

The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still implement the foregoing embodiments Modifications to the technical solutions described in the examples, or equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application, and should be included in the Within the protection scope of this application.

Claims

An array substrate, comprising: N×M pixel groups (12), wherein the N×M pixel groups (12) are arranged in N rows and M columns;

The pixel group (12) includes at least one sub-pixel module (14), the sub-pixel module (14) includes a switch circuit (120) and sub-pixels (110) correspondingly connected to the switch circuit (120), each The switch circuit (120) in each sub-pixel module (14) is connected to a data line (130), and the switch circuit (120) in each sub-pixel module (14) is connected to a scan line ( 140); the switch circuits (120) in different pixel groups (12) in the same row are connected to different data lines (130), and the switches in the pixel groups (12) in different rows The circuits (120) are connected to different scanning lines (140); the scanning lines (140) connected to the multiple switching circuits (120) connected to the same data line (130) are different;

The scanning lines (140) include a first scanning line, and the first scanning line is the first scanning line (140) outputting scanning signals when the array substrate (10) is working;

Wherein, the switch circuit (120) includes a first switch circuit (122) connected to the first scan line, each of the first switch circuits (122) includes a plurality of transistors, each of the first The control poles of multiple transistors in a switch circuit (122) are all connected to the first scanning line, and the first poles of multiple transistors in each of the first switch circuits (122) are connected to the same line The data line (130), the second electrodes of the multiple transistors in each of the first switch circuits (122) are connected to the corresponding sub-pixels (110) of the first switch circuit (122).
The array substrate according to claim 1, wherein each of the sub-pixels (110) includes one of red sub-pixels, green sub-pixels and blue sub-pixels, and the pixel group (12) includes two of the In the case of the sub-pixel module (14), the sub-pixels (110) connected to the first switch circuit (122) connected to the first scanning line include all the green sub-pixels located in the first row, and the green sub-pixels located in the first row half of the row's red subpixels.
The array substrate according to claim 2, wherein the sub-pixels (110) connected to the first switch circuit (122) connected to the first scanning line are arranged at intervals.
The array substrate according to claim 1, wherein each of the sub-pixels (110) includes one of red sub-pixels, green sub-pixels and blue sub-pixels, and the pixel group (12) includes three of the When using the sub-pixel module (14), the sub-pixel (110) connected to the first switch circuit (122) connected to the first scanning line is the green sub-pixel.
The array substrate according to claim 4, wherein the sub-pixels (110) connected to the first switch circuit (122) connected to the first scanning line are arranged at intervals.
The array substrate according to claim 1, wherein the scan line (140) includes a second scan line, and the second scan line is the second output scan signal when the array substrate (10) is in operation. scanLine(140);

The switch circuit (120) further includes a second switch circuit (124) connected to the second scan line, each of the second switch circuits (124) includes a plurality of transistors, and each of the second The control poles of multiple transistors in the switch circuit (124) are all connected to the second scanning line, and the first poles of the multiple transistors in each of the second switch circuits (124) are connected to the same data line (130), the second poles of the plurality of transistors in each second switch circuit (124) are connected to the corresponding sub-pixel (110) of the second switch circuit (124).
The array substrate according to claim 6, wherein the number of transistors in the second switch circuit (124) is smaller than the number of transistors in the first switch circuit (122).
The array substrate according to claim 6, wherein each of the sub-pixels (110) includes one of red sub-pixels, green sub-pixels and blue sub-pixels, and the pixel group (12) includes three of the When using the sub-pixel module (14), the sub-pixel (110) connected to the second switch circuit (124) connected to the second scanning line is the red sub-pixel.
The array substrate according to claim 6, wherein the channel width-length ratio of at least one transistor in the first switch circuit (122) is greater than the channel width-length ratio of at least one transistor in the second switch circuit (124) Compare.
The array substrate according to claim 9, wherein the channel lengths of the multiple transistors in the first switch circuit (122) are all equal to the channel lengths of the transistors in the second switch circuit (124), so The channel width of at least one transistor in the first switch circuit (122) is larger than the channel width of the transistor in the second switch circuit (124).
The array substrate according to claim 9, wherein channel widths of the plurality of transistors in the first switch circuit (122) are all equal to channel widths of transistors in the second switch circuit (124), so The channel length of at least one transistor in the first switch circuit (122) is smaller than the channel length of the transistor in the second switch circuit (124).
The array substrate according to claim 1, wherein the switch circuit (120) comprises a third switch circuit (126) connected to the third scan line to the last scan line, and each of the third switch circuits ( 126) each includes a transistor, the control electrode of each transistor in the third switch circuit (126) is connected to a scan line (140), and the first transistor of each third switch circuit (126) One pole is connected to a data line (130), the second pole of each transistor in the third switch circuit (126) is connected to the corresponding sub-pixel (110) of the third switch circuit (126), the The third scanning line is the third scanning line (140) that outputs scanning signals when the array substrate (10) is working, and the last scanning line is the last scanning line that outputs scanning signals when the array substrate (10) is working. scanlines (140).
The array substrate according to claim 12, wherein a channel width-to-length ratio of at least one transistor in the first switch circuit (122) is greater than a channel width-to-length ratio of a transistor in the third switch circuit (126).
The array substrate according to claim 13, wherein the channel lengths of the plurality of transistors in the first switch circuit (122) are all equal to the channel lengths of the transistors in the third switch circuit (126), so The channel width of at least one transistor in the first switch circuit (122) is larger than the channel width of the transistor in the third switch circuit (126).
The array substrate according to claim 13, wherein channel widths of the plurality of transistors in the first switch circuit (122) are all equal to channel widths of transistors in the third switch circuit (126), so The channel length of at least one transistor in the first switch circuit (122) is smaller than the channel length of the transistor in the third switch circuit (126).
A display panel (20), comprising: a color filter substrate (210), a liquid crystal layer (220), and the array substrate (10) according to any one of claims 1 to 15;

The array substrate (10) is arranged opposite to the color filter substrate (210), and the liquid crystal layer (220) is located between the array substrate (10) and the color filter substrate (210).
A display device, comprising the display panel (20) according to claim 16.