CN107065366B - Array substrate and driving method thereof - Google Patents
Array substrate and driving method thereof Download PDFInfo
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- CN107065366B CN107065366B CN201710466285.1A CN201710466285A CN107065366B CN 107065366 B CN107065366 B CN 107065366B CN 201710466285 A CN201710466285 A CN 201710466285A CN 107065366 B CN107065366 B CN 107065366B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Abstract
The invention provides an array substrate and a driving method thereof. According to the array substrate, a row of virtual sub-pixels are additionally arranged in front of a first row of sub-pixels, a pre-charging line and an electrode connecting line are arranged corresponding to the row of virtual sub-pixels, each virtual sub-pixel comprises a shared thin film transistor, a grid electrode of the shared thin film transistor is electrically connected with the pre-charging line, a source electrode of the shared thin film transistor is electrically connected with a data line, a drain electrode of the shared thin film transistor is electrically connected with a common electrode of a color film substrate through the electrode connecting line, when the array substrate is scanned, the pre-charging line is firstly scanned, then the pre-charging line and the first scanning line are simultaneously scanned, the first row of sub-pixels are pre-charged, finally the first scanning line is independently scanned, and meanwhile, the data line outputs a data signal, so that the charging efficiency of the first row of.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a driving method thereof.
Background
Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, and the like, and are widely used. Such as: liquid crystal televisions, mobile phones, Personal Digital Assistants (PDAs), digital cameras, computer screens, notebook computer screens, or the like, are dominant in the field of flat panel displays.
Generally, a liquid crystal display device includes a housing, a liquid crystal panel disposed in the housing, and a Backlight module (Backlight module) disposed in the housing. The Liquid Crystal display panel is mainly composed of an Array Substrate (Thin film transistor Array Substrate), a Color film Substrate (Color filter Substrate, CFSubstrate) and a Liquid Crystal Layer (Liquid Crystal Layer) arranged between the two substrates, and the Liquid Crystal display panel has the working principle that the rotation of Liquid Crystal molecules of the Liquid Crystal Layer is controlled by applying driving voltages to a pixel electrode of the TFT Substrate and a common electrode of the CF Substrate, and light of a backlight module is refracted to generate pictures.
As shown in fig. 1, the conventional array substrate includes: a plurality of horizontal scanning lines 100, a plurality of vertical data lines 200, and a plurality of sub-pixels 300 arranged in an array, each sub-pixel 300 is provided with a driving thin film transistor T1 and a pixel electrode P electrically connected to the drain of the driving thin film transistor T1, the gate of the driving thin film transistor T1 in each sub-pixel 300 of the same row is electrically connected to the same scanning line 100, the sources of the two driving thin film transistors T1 in two sub-pixels 300 of two adjacent rows of the same column are electrically connected to the two data lines 200 at two sides of the row of sub-pixels 300, respectively, when the scanning line 100 is driven, the driving thin film transistor T1 is in a conducting state, the corresponding data line 200 sends a gray scale voltage signal and applies the gray scale voltage signal to the pixel electrode P, so that a corresponding electric field is generated between the pixel electrode P and the common electrode, and liquid crystal molecules in the liquid crystal layer generate orientation change under the action of the electric field, to achieve different image displays.
Further, in the array substrate shown in fig. 1, the Data line 200 adopts a structure in which left and right sub-pixels are alternately driven, which is advantageous in that a dot inversion driving effect can be achieved by column inversion, low power consumption can be achieved by reducing a pixel inversion frequency, and charging efficiency can be improved by pre-charging, as shown in fig. 2, when the array substrate is driven, first, the scan signal G1 of the first row of scan line 100 is output to the first row of scan line 100 to start scanning, then, in the latter half time of the output of the scan signal G1 of the first row of scan line 100, the Data signal Data is output while the scan signal G2 of the second row of scan line 100 is output as the second row of sub-pixels 300 to be pre-charged, then, in the latter half time of the output of the scan signal G2 of the second row of scan line 100, the Data signal Data is output again while the scan signal G3 of the third row of scan line 100 is output as the third row of sub, the same goes for scanning of the whole panel, however, the first row of sub-pixels 300 does not have a pre-charging process in the scanning process, and when the frame refresh frequency is too high, the charging rate of the first row of sub-pixels 300 is low, thereby affecting the frame display quality.
Disclosure of Invention
The invention aims to provide an array substrate, which can improve the charging efficiency of pixels in a first row and ensure the picture display quality at a high refresh rate.
The present invention also provides a driving method of an array substrate, which can improve the charging efficiency of the first row of pixels and ensure the image display quality at a high refresh rate.
In order to achieve the above object, the present invention provides an array substrate, including: the pixel array comprises a plurality of scanning lines arranged in parallel at intervals, a plurality of data lines arranged in parallel at intervals and perpendicular to the scanning lines, a plurality of sub-pixels arranged in an array, a plurality of virtual sub-pixels, a pre-charging line and an electrode connecting line;
a row of sub-pixels is arranged corresponding to each scanning line, and a column of sub-pixels is arranged between two adjacent data lines; each sub-pixel includes: the grid electrode of each driving thin film transistor in the sub-pixels in the same row is electrically connected with the scanning line corresponding to the sub-pixels in the row, the source electrode of each driving thin film transistor in the sub-pixels in the odd-numbered rows is respectively electrically connected with the data line positioned on one side of each sub-pixel, and the source electrode of each driving thin film transistor in the sub-pixels in the even-numbered rows is respectively electrically connected with the data line positioned on the other side of each sub-pixel;
the number of the virtual sub-pixels is equal to that of the data lines, the virtual sub-pixels are arranged in a row before the first row of sub-pixels, the pre-charging lines and the electrode connecting lines correspond to the virtual sub-pixels in the row respectively, the electrode connecting lines are electrically connected with a common electrode of the color film substrate, each virtual sub-pixel comprises a shared thin film transistor, a grid electrode of the shared thin film transistor is electrically connected with the pre-charging lines, a source electrode of the shared thin film transistor is electrically connected with the data lines corresponding to the virtual sub-pixels, and a drain electrode of the shared thin film transistor is electrically connected with the electrode connecting lines.
The plurality of sub-pixels include: the red sub-pixel, the green sub-pixel and the blue sub-pixel are sequentially and repeatedly arranged.
The pixel electrodes are all meter-shaped pattern electrodes.
During scanning, the pre-charging lines are scanned first, and then the plurality of scanning lines are scanned sequentially from the first scanning line to the last scanning line.
The driving thin film transistor and the shared thin film transistor are oxide semiconductor thin film transistors, low-temperature polycrystalline silicon thin film transistors or amorphous silicon thin film transistors.
The invention also provides a driving method of the array substrate, which comprises the following steps:
step 1, providing an array substrate, comprising: the pixel array comprises a plurality of scanning lines arranged in parallel at intervals, a plurality of data lines arranged in parallel at intervals and perpendicular to the scanning lines, a plurality of sub-pixels arranged in an array, a plurality of virtual sub-pixels, a pre-charging line and an electrode connecting line;
a row of sub-pixels is arranged corresponding to each scanning line, and a column of sub-pixels is arranged between two adjacent data lines; each sub-pixel includes: the grid electrode of each driving thin film transistor in the sub-pixels in the same row is electrically connected with the scanning line corresponding to the sub-pixels in the row, the source electrode of each driving thin film transistor in the sub-pixels in the odd-numbered rows is respectively electrically connected with the data line positioned on one side of each sub-pixel, and the source electrode of each driving thin film transistor in the sub-pixels in the even-numbered rows is respectively electrically connected with the data line positioned on the other side of each sub-pixel;
the number of the virtual sub-pixels is equal to that of the data lines and the virtual sub-pixels are arranged in a row before the first row of sub-pixels, the pre-charging lines and the electrode connecting lines respectively correspond to the virtual sub-pixels in the row, the electrode connecting lines are electrically connected with a common electrode of the color film substrate, each virtual sub-pixel comprises a shared thin film transistor, the grid electrode of the shared thin film transistor is electrically connected with the pre-charging lines, the source electrode of the shared thin film transistor is electrically connected with the data lines corresponding to the virtual sub-pixels, and the drain electrode of the shared thin film transistor is electrically connected with the electrode connecting lines;
step 2, scanning from the first row of sub-pixels to the last row of sub-pixels in sequence;
assuming that N is a positive integer greater than 1, the scanning process of the nth row of sub-pixels includes: the N-1 scanning line outputs an N-1 scanning signal firstly, the driving thin film transistors in the sub-pixels of the N-1 row are all opened, then the N-1 scanning line continues to output the N-1 scanning signal, the N scanning line starts to output the N scanning signal, all the driving thin film transistors in the sub-pixels of the N row are all opened, the sub-pixels of the N row are pre-charged, finally the N-1 scanning line stops outputting the N-1 scanning signal, the N scanning line continues to output the N scanning signal, and the data line outputs a data signal;
the scanning process of the first row of sub-pixels comprises the following steps: the pre-charging line outputs a pre-charging signal firstly, each shared thin film transistor is opened, then the pre-charging line continues to output pre-charging scanning signals, a first scanning line outputs a first scanning signal, each driving thin film transistor in a first row of sub-pixels is opened to pre-charge the first row of sub-pixels, finally the pre-charging line stops outputting the pre-charging signal, the first scanning line continues to output the first scanning signal, and the data line outputs a data signal.
The plurality of sub-pixels include: the red sub-pixel, the green sub-pixel and the blue sub-pixel are sequentially and repeatedly arranged.
The pixel electrodes are all meter-shaped pattern electrodes.
The driving thin film transistor and the shared thin film transistor are oxide semiconductor thin film transistors, low-temperature polycrystalline silicon thin film transistors or amorphous silicon thin film transistors.
The invention has the beneficial effects that: the invention provides an array substrate, which is characterized in that a row of virtual sub-pixels are additionally arranged in front of a first row of sub-pixels, a pre-charging line and an electrode connecting line are arranged corresponding to the row of virtual sub-pixels, each virtual sub-pixel comprises a shared thin film transistor, a grid electrode of the shared thin film transistor is electrically connected with the pre-charging line, a source electrode of the shared thin film transistor is electrically connected with a data line, a drain electrode of the shared thin film transistor is electrically connected with a common electrode of a color film substrate through the electrode connecting line, when the array substrate is scanned, the pre-charging line is firstly scanned, then the pre-charging line and the first scanning line are scanned simultaneously, the first row of sub-pixels are pre-charged, finally the first scanning line is scanned independently, and meanwhile, the data line outputs a data signal, so that the charging efficiency of the first row of pixels can. The invention also provides a driving method of the array substrate, which can improve the charging efficiency of the first row of pixels and ensure the picture display quality at a high refresh rate.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
fig. 1 is a structural view of a conventional array substrate;
fig. 2 is a timing diagram of a conventional array substrate;
FIG. 3 is a structural diagram of an array substrate according to the present invention;
FIG. 4 is a timing diagram of an array substrate according to the present invention;
fig. 5 is a flowchart of a driving method of an array substrate according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 3, the present invention provides an array substrate, including: the display device comprises a plurality of scanning lines 10 arranged in parallel at intervals, a plurality of data lines 20 arranged in parallel at intervals and perpendicular to the scanning lines 10, a plurality of sub-pixels 30 arranged in an array, a plurality of virtual sub-pixels 31, a pre-charging line 40 and an electrode connecting line 50;
a row of sub-pixels 30 is arranged corresponding to each scanning line 10, and a column of sub-pixels 30 is arranged between two adjacent data lines 20; each sub-pixel 30 includes: the driving thin film transistor T10 and the pixel electrode P10 electrically connected to the drain of the driving thin film transistor T10, the gate of each driving thin film transistor T10 in the same row of sub-pixels 30 is electrically connected to the corresponding scan line 10 of the row of sub-pixels 30, the source of each driving thin film transistor T10 in the odd-numbered row of sub-pixels 30 is electrically connected to the data line 20 on one side of each sub-pixel 30, and the source of each driving thin film transistor T10 in the even-numbered row of sub-pixels 30 is electrically connected to the data line 20 on the other side of each sub-pixel 30;
the number of the virtual sub-pixels 31 is equal to the number of the data lines 20, and the virtual sub-pixels 31 are arranged in a row before the first row of sub-pixels 30, the precharge lines 40 and the electrode connection lines 50 respectively correspond to the row of the virtual sub-pixels 31, the electrode connection lines 50 are electrically connected to a common electrode (CF-Com) of a color filter substrate, each virtual sub-pixel 31 includes a shared thin film transistor T20, a gate of the shared thin film transistor T20 is electrically connected to the precharge lines 40, a source is electrically connected to the data lines 20 corresponding to the virtual sub-pixels 31, and a drain is electrically connected to the electrode connection lines 50.
Preferably, the plurality of sub-pixels 30 may include: the red sub-pixel, the green sub-pixel and the blue sub-pixel are sequentially and repeatedly arranged, and certainly, the plurality of sub-pixels may further include sub-pixels of other colors such as a white sub-pixel and a yellow sub-pixel as required, which does not affect the implementation of the present invention.
Preferably, the pixel electrodes P10 are all m-shaped patterned electrodes, each of which includes a plurality of branch electrodes extending in different directions, and the branch electrodes deflect the liquid crystal in different directions, thereby implementing multi-domain display. Of course, the pixel electrode P10 can also be a common planar electrode, which does not affect the implementation of the present invention.
Preferably, the driving thin film transistor T10 and the sharing thin film transistor T20 may be various types of thin film transistors such as an oxide semiconductor thin film transistor, a low temperature polysilicon thin film transistor, or an amorphous silicon thin film transistor.
Specifically, referring to fig. 4, when the array substrate is scanned, the precharge lines 40 are scanned first, and then the plurality of scan lines 10 are scanned sequentially from the first to the last, and the detailed working process is as follows: the precharge line 40 outputs a precharge signal G0 first, the respective shared thin film transistors T20 are turned on, then the precharge line 40 continues to output a precharge scan signal G0, the first scan line 10 outputs a first scan signal G1, the respective driving thin film transistors T10 in the first row of sub-pixels 30 are turned on, the first row of sub-pixels 30 are precharged, finally the precharge line 40 stops outputting a precharge signal G0, the first scan line 10 continues to output a first scan signal G1, the Data line 20 outputs a Data signal Data, while the second scan line 10 outputs a second scan signal G2, the respective driving thin film transistors T10 in the second row of sub-pixels 30 are turned on, the second row of sub-pixels 30 are precharged, then the first scan line 10 stops outputting a first scan signal G1, the second scan line 10 continues to output a second scan signal G2, the Data line 20 outputs the Data signal Data, and the third scan line 10 outputs the third scan signal G3 to precharge the third row of sub-pixels 30, then the second scan line 10 stops outputting the second scan signal G2, the third scan line 10 continues outputting the third scan signal G3, the Data line 20 outputs the Data signal Data, and so on until the last row of sub-pixels 30.
Compared with the prior art, the virtual sub-pixels 31 in one row are additionally arranged before the sub-pixels 30 in the first row, when the array substrate is scanned, the pre-charging wires 40 are firstly scanned, then the pre-charging wires 40 and the first scanning lines 10 are scanned simultaneously, the sub-pixels 30 in the first row are pre-charged, finally the first scanning lines 10 are scanned independently, and meanwhile, the Data lines 20 output Data signals Data, so that the charging efficiency of the pixels in the first row can be improved, and the picture display quality at a high refresh rate is ensured.
Referring to fig. 5, a driving method of an array substrate includes the following steps:
step 1, providing an array substrate, wherein the specific structure is as above, and the details are not repeated here.
Step 2, scanning is sequentially carried out from the first row of sub-pixels 30 to the last row of sub-pixels 30;
assuming that N is a positive integer greater than 1, the scanning process of the nth row of sub-pixels 30 includes: the N-1 scan line 10 outputs an N-1 scan signal GN-1 first, the driving thin film transistors T10 in the subpixels 30 in the N-1 row are all turned on, then the N-1 scan line 10 continues to output an N-1 scan signal GN-1, the N scan line 10 starts to output an N scan signal GN, the driving thin film transistors T10 in the subpixels 30 in the N row are all turned on, the subpixels 30 in the N row are precharged, finally the N-1 scan line 10 stops outputting the N-1 scan signal GN-1, the N scan line 10 continues to output an N scan signal GN, and the Data line 20 outputs a Data signal Data;
the scanning process of the first row of sub-pixels 30 comprises: the precharge line 40 outputs a precharge signal G0 first, the shared thin film transistors T20 are turned on, then the precharge line 40 continues to output a precharge scan signal G0, the first scan line 10 outputs a first scan signal G1, the driving thin film transistors T10 in the first row of sub-pixels 30 are turned on, the first row of sub-pixels 30 are precharged, finally the precharge line 40 stops outputting a precharge signal G0, the first scan line 10 continues to output a first scan signal G1, and the Data line 20 outputs a Data signal Data.
Preferably, the plurality of sub-pixels 30 may include: the red sub-pixel, the green sub-pixel and the blue sub-pixel are sequentially and repeatedly arranged, and certainly, the plurality of sub-pixels may further include sub-pixels of other colors such as a white sub-pixel and a yellow sub-pixel as required, which does not affect the implementation of the present invention.
Preferably, the pixel electrodes P10 are all m-shaped patterned electrodes, each of which includes a plurality of branch electrodes extending in different directions, and the branch electrodes deflect the liquid crystal in different directions, thereby implementing multi-domain display. Of course, the pixel electrode P10 can also be a common planar electrode, which does not affect the implementation of the present invention.
Preferably, the driving thin film transistor T10 and the sharing thin film transistor T20 may be various types of thin film transistors such as an oxide semiconductor thin film transistor, a low temperature polysilicon thin film transistor, or an amorphous silicon thin film transistor.
Specifically, compared with the prior art, in the present invention, by adding a row of dummy subpixels 31 before a first row of subpixels 30, when the array substrate is scanned, firstly, the precharge lines 40 are scanned, then, the precharge lines 40 and the first scan lines 10 are scanned simultaneously, the first row of subpixels 30 are precharged, finally, the first scan lines 10 are scanned separately, and simultaneously, the Data lines 20 output Data signals Data, so that the charging efficiency of the first row of subpixels can be improved, and the picture display quality at a high refresh rate can be ensured.
In summary, the present invention provides an array substrate, where a row of virtual sub-pixels is added before a first row of sub-pixels, and a pre-charge line and an electrode connection line are arranged corresponding to the row of virtual sub-pixels, each virtual sub-pixel includes a shared thin film transistor, a gate of the shared thin film transistor is electrically connected to the pre-charge line, a source of the shared thin film transistor is electrically connected to a data line, and a drain of the shared thin film transistor is electrically connected to a common electrode of a color film substrate through the electrode connection line, when the array substrate scans, the pre-charge line is scanned first, then the pre-charge line and the first scan line are scanned simultaneously to pre-charge the first row of sub-pixels, and finally the first scan line is scanned separately, and the data line outputs a data signal, so that the charging efficiency of the first row of pixels can be improved, and the picture display quality at a. The invention also provides a driving method of the array substrate, which can improve the charging efficiency of the first row of pixels and ensure the picture display quality at a high refresh rate.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (8)
1. An array substrate, comprising: the pixel structure comprises a plurality of scanning lines (10) which are arranged in parallel at intervals, a plurality of data lines (20) which are arranged in parallel at intervals and are vertical to the scanning lines (10), a plurality of sub-pixels (30) which are arranged in an array, a plurality of virtual sub-pixels (31), a pre-charging line (40) and an electrode connecting line (50);
a row of sub-pixels (30) is arranged corresponding to each scanning line (10), and a column of sub-pixels (30) is arranged between two adjacent data lines (20); each sub-pixel (30) comprises: the driving thin film transistor (T10) and the pixel electrode (P10) are electrically connected with the drain electrode of the driving thin film transistor (T10), the grid electrode of each driving thin film transistor (T10) in the sub-pixel (30) in the same row is electrically connected with the scanning line (10) corresponding to the sub-pixel (30) in the row, the source electrode of each driving thin film transistor (T10) in the sub-pixel (30) in the odd row is respectively electrically connected with the data line (20) on one side of each sub-pixel (30), and the source electrode of each driving thin film transistor (T10) in the sub-pixel (30) in the even row is respectively electrically connected with the data line (20) on the other side of each sub-pixel (30);
the number of the virtual sub-pixels (31) is equal to the number of the data lines (20) and is arranged in a row before a first row of sub-pixels (30), the pre-charging lines (40) and the electrode connecting lines (50) respectively correspond to the virtual sub-pixels (31), the electrode connecting lines (50) are electrically connected with a common electrode of a color film substrate, each virtual sub-pixel (31) comprises a shared thin film transistor (T20), the grid electrode of the shared thin film transistor (T20) is electrically connected with the pre-charging lines (40), the source electrode of the shared thin film transistor is electrically connected with the data lines (20) corresponding to the virtual sub-pixels (31), and the drain electrode of the shared thin film transistor is electrically connected with the electrode connecting lines (50);
during scanning, the pre-charging wires (40) are scanned first, and then the plurality of scanning lines (10) are scanned sequentially from the first line to the last line;
when scanning, firstly, the pre-charging line (40) is scanned, then the pre-charging line (40) and the first scanning line (10) are scanned simultaneously, and the first row of sub-pixels (30) are pre-charged.
2. The array substrate of claim 1, wherein the plurality of sub-pixels (30) comprises: the red sub-pixel, the green sub-pixel and the blue sub-pixel are sequentially and repeatedly arranged.
3. The array substrate of claim 1, wherein the pixel electrodes (P10) are all in a shape of a Chinese character 'mi'.
4. The array substrate of claim 1, wherein the driving thin film transistor (T10) and the sharing thin film transistor (T20) are oxide semiconductor thin film transistors, low temperature polysilicon thin film transistors, or amorphous silicon thin film transistors.
5. A driving method of an array substrate is characterized by comprising the following steps:
step 1, providing an array substrate, comprising: the pixel structure comprises a plurality of scanning lines (10) which are arranged in parallel at intervals, a plurality of data lines (20) which are arranged in parallel at intervals and are vertical to the scanning lines (10), a plurality of sub-pixels (30) which are arranged in an array, a plurality of virtual sub-pixels (31), a pre-charging line (40) and an electrode connecting line (50);
a row of sub-pixels (30) is arranged corresponding to each scanning line (10), and a column of sub-pixels (30) is arranged between two adjacent data lines (20); each sub-pixel (30) comprises: the driving thin film transistor (T10) and the pixel electrode (P10) are electrically connected with the drain electrode of the driving thin film transistor (T10), the grid electrode of each driving thin film transistor (T10) in the sub-pixel (30) in the same row is electrically connected with the scanning line (10) corresponding to the sub-pixel (30) in the row, the source electrode of each driving thin film transistor (T10) in the sub-pixel (30) in the odd row is respectively electrically connected with the data line (20) on one side of each sub-pixel (30), and the source electrode of each driving thin film transistor (T10) in the sub-pixel (30) in the even row is respectively electrically connected with the data line (20) on the other side of each sub-pixel (30);
the number of the virtual sub-pixels (31) is equal to the number of the data lines (20) and is arranged in a row before a first row of sub-pixels (30), the pre-charging lines (40) and the electrode connecting lines (50) respectively correspond to the virtual sub-pixels (31), the electrode connecting lines (50) are electrically connected with a common electrode of a color film substrate, each virtual sub-pixel (31) comprises a shared thin film transistor (T20), the grid electrode of the shared thin film transistor (T20) is electrically connected with the pre-charging lines (40), the source electrode of the shared thin film transistor is electrically connected with the data lines (20) corresponding to the virtual sub-pixels (31), and the drain electrode of the shared thin film transistor is electrically connected with the electrode connecting lines (50);
step 2, scanning is sequentially carried out from the first row of sub-pixels (30) to the last row of sub-pixels (30);
assuming that N is a positive integer greater than 1, the scanning process of the N-th row of sub-pixels (30) comprises: the N-1 scanning line (10) outputs an N-1 scanning signal (GN-1) firstly, the driving thin film transistors (T10) in the sub-pixels (30) of the N-1 row are all opened, then the N-1 scanning line (10) continuously outputs an N-1 scanning signal (GN-1), the N scanning line (10) starts outputting an N scanning signal (GN), each driving thin film transistor (T10) in the sub-pixels (30) of the N row is opened, the sub-pixels (30) of the N row are pre-charged, finally the N-1 scanning line (10) stops outputting the N-1 scanning signal (GN-1), the N scanning line (10) continuously outputs an N scanning signal (GN), and the Data line (20) outputs a Data signal (Data);
the scanning process of the first row of sub-pixels (30) comprises: the pre-charging line (40) outputs a pre-charging signal (G0) first, each shared thin film transistor (T20) is turned on, then the pre-charging line (40) continues to output a pre-charging scanning signal (G0), a first scanning line (10) outputs a first scanning signal (G1), each driving thin film transistor (T10) in a first row of sub-pixels (30) is turned on, the first row of sub-pixels (30) are pre-charged, finally the pre-charging line (40) stops outputting a pre-charging signal (G0), the first scanning line (10) continues to output a first scanning signal (G1), and the Data line (20) outputs a Data signal (Data).
6. The driving method of the array substrate according to claim 5, wherein the plurality of sub-pixels (30) comprise: the red sub-pixel, the green sub-pixel and the blue sub-pixel are sequentially and repeatedly arranged.
7. The method of driving an array substrate according to claim 5, wherein the pixel electrodes (P10) are all in a shape of a Chinese character 'mi'.
8. The method of driving the array substrate of claim 5, wherein the driving thin film transistor (T10) and the sharing thin film transistor (T20) are oxide semiconductor thin film transistors, low temperature polysilicon thin film transistors, or amorphous silicon thin film transistors.
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| CN107749414A (en) * | 2017-09-16 | 2018-03-02 | 合肥惠科金扬科技有限公司 | A kind of display device |
| CN107632430A (en) * | 2017-09-16 | 2018-01-26 | 合肥惠科金扬科技有限公司 | A kind of manufacturing process of the display panel assembly of display device |
| CN107767772A (en) * | 2017-09-16 | 2018-03-06 | 合肥惠科金扬科技有限公司 | A kind of display panel assembly of display device |
| CN107577100B (en) * | 2017-10-10 | 2020-06-19 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN109493779A (en) | 2018-11-27 | 2019-03-19 | 惠科股份有限公司 | Display panel, pixel charging method and computer readable storage medium |
| CN111312193B (en) * | 2020-04-02 | 2021-10-08 | Tcl华星光电技术有限公司 | Driving device and driving method for display array module |
| CN111522161B (en) | 2020-05-29 | 2021-09-17 | 厦门天马微电子有限公司 | Array substrate, display panel, display device and driving method |
| CN113284427B (en) * | 2021-05-28 | 2022-01-14 | 惠科股份有限公司 | Display panel and spliced display screen |
| CN113376912B (en) * | 2021-08-12 | 2021-12-17 | 惠科股份有限公司 | Array substrate and display panel |
| CN114420068B (en) * | 2022-01-29 | 2023-08-08 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114627793A (en) * | 2022-04-06 | 2022-06-14 | Tcl华星光电技术有限公司 | Array substrate, display panel and display device |
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