CN211124033U - Adapter plate for converting U2 interface into 3U VPX interface - Google Patents

Abstract

The utility model provides a realize U.2 interface commentaries on classics keysets of 3U VPX interface, including 3U VPX connector, PCIE clock selection circuit, PCIE driver/Repeater redriver, U.2 connector. The 3U VPX connector includes three sets of sub-connectors, 1 8-column, 7-row RT2 connectors and 2 16-column, 7-row RT2 connectors, respectively, defined on the 3U VPX board connector. The first group is a common connector and provides a maintenance management bus, a test bus and power signals, the second group provides 32 pairs of differential pair signals and 8 single-ended signals, and the third group is user-defined and can be defined as differential signals or single-ended signals. The utility model discloses realize the switching with U.2 interface and VPX interface, remain the advantage of two kinds of interfaces, improved the maintainability of product, improved product life, realized U.2 dish and extended the application.

Description

Adapter plate for converting U2 interface into 3U VPX interface

Technical Field

The utility model belongs to the technical field of solid-state storage, a U.2 interface commentaries on classics 3U VPX interface switching technique is related to, in particular to realize U.2 interface commentaries on classics 3U VPX interface's keysets.

Background

The U.2 interface is also called as SFF-8639 interface, and is an interface specification derived from the solid state disk Form work organization (SSD Form Factor WorkGroup). U.2 not only supports SATA-Express specification, but also is compatible with SAS, SATA and other specifications. Therefore, the U.2 interface can be simply considered as a four-channel SATA-Express interface, and the theoretical bandwidth of the bandwidth of PCIE 3.0x4 is as high as 32 Gbps. SATA is only 6Gbps, which is 5 times faster than SATA

U.2 the equipment interface has the characteristics of SATA and SAS, the middle pin fills the gap left by SATA interface, and reserves L type foolproof design, supports NVMe protocol, even the power supply capability is also improved, which is helpful to improve SSD performance.

The VPX bus is originated from the VME bus, and the VME bus is born 30 years ago, combines the Motorola Versa bus electrical standard and the European card mechanical packaging standard, is an open architecture, and is widely applied to the fields of industrial control, signal processing and national defense.

However, the VME bus is a technology 30 years ago, and as the requirement of the industry on the transmission bandwidth of the bus technology is continuously increased, the VME bus gradually shows disadvantages. For this reason, VITA also successively introduced upgraded versions of VME64, VME64x, VME320, etc., and unfortunately, the market reaction was not ideal. This aspect is not completely reversed until the VPX bus appears.

The VPX bus replaces the parallel bus technology of the VME bus with high-speed serial bus technology. The VPX bus introduces the current state-of-the-art serial bus technology, such as: RapidIO, PCI-Express, and gigabit ethernet, among others, support higher backplane bandwidth. VPX core switching can provide 32 pairs of differential pairs, each pair of differential pairs can theoretically provide 10Gbps of data switching capacity, and one VPX module can theoretically provide 8GByte/s of data switching capacity at most.

The VPX bus also replaces the hosted architecture of the VME with a switched architecture. The switching structure ensures that the overall performance of the system is not limited by the main control board, and improves the overall performance of the system. Meanwhile, under the switching structure, the processor can send data at any time without waiting for the bus to initiate transmission, and the method is particularly suitable for a multiprocessor system.

One of the most important differences between the VME bus and VPX is that the VPX bus employs a new generation 7-row MultiGig RT2 connector developed by Tyco. The MultiGig RT2 connector has excellent performance, controllable characteristic impedance, low insertion loss, and crosstalk less than 3% at transmission rates up to 6.25 Gbps. The MultiGig RT2 connector is tight and robust to join and may be used in military and aerospace applications.

However, in the face of a complex and varied application environment, the U.2 disk cannot satisfy the diversification requirements of users for storage interfaces.

SUMMERY OF THE UTILITY MODEL

To prior art's not enough, the utility model provides a technical scheme can be with U.2 interface switching for the VPX interface to the application of U.2 dish on 3U VPX platform has been expanded. The adopted specific technical scheme is as follows:

the utility model discloses system architecture mainly contains 4 parts: a 3U VPX connector 101, a PCIE clock selection circuit 102, a PCIE driver/Repeater redriver 103, and an U.2 connector 104.

The 3U VPX connector 101 is composed of three groups of sub-connectors P0, P1 and P2, and 1 8-column 7-row RT2 connector P0 and 2 16-column 7-row RT2 connectors P1 and P2 are defined on the 3U VPX board connector. Wherein, P0 is a common connector, which provides maintenance management bus, test bus and power signal; p1 provides 32 pairs of differential pair signals and 8 single-ended signals; p2 is user-defined and can be defined as either a differential signal or a single-ended signal.

The PCIE clock selection circuit 102 may switch U.2 the clock of the disk through a dial Switch (SW) to be provided by a system clock or a motherboard on-board clock chip. The circuit has the advantages that the compatibility can be improved, the system clock is adopted by default, and when the system clock cannot be provided, the system clock can be switched to an onboard clock.

The PCIE driver/Repeater re-driver 103 attenuates PCIE 3.0 signals due to too long distance or more connectors in the PCIE transmission process, the transmission speed becomes slow, and the system speed is reduced to PCIE 2.0 or PCIE1.0 in a serious case. The circuit has the function of realizing the aim of redriving by adjusting the output amplitude and the balanced value of an input PCIE signal through a Redrive/Repeater circuit, so that a fuzzy eye pattern is clearer, and the quality of the PCIE signal is improved.

U.2 connector 104, signals include power, low speed signal, clock signal, high speed signal. Wherein the power supply is direct current 12V. The low-speed signal is a single-ended GPIO interface, and is used for control, for example, PCIE reset is realized by GPIO and PCIE signals are configured to 2X 2 paths or 1X 4 paths, a clock signal provides a PCIE clock for a U.2 disk, and the high-speed signal has 6 paths in total, the standard U.2 interface includes 2 SATA/SAS signal positions, and 4 PCIE interface (which may be set to 2X 2 paths or 1X 4 path) signal positions. The claimed technical solution is as follows:

an adapter board for converting an U.2 interface into a 3U VPX interface, comprising: a 3U VPX connector, a PCIE clock selection circuit, a PCIE driver/Repeater redriver, and an U.2 connector;

the 3U VPX connector comprises three groups of sub-connectors, wherein the first group of sub-connectors are 1 8-column 7-row RT2 connectors defined on the 3U VPX board connector, and the second group of sub-connectors and the third group of sub-connectors are 2 16-column 7-row RT2 connectors defined on the 3U VPX board connector respectively; the first group of sub-connectors are public connectors and provide a maintenance management bus, a test bus and a power supply signal; the second set of sub-connectors provides 32 pairs of differential pair signals and 8 single-ended signals; a third set of sub-connectors, which may be defined as either differential signals or as single-ended signals;

the PCIE clock selection circuit (102) comprises a dial Switch (SW), wherein a clock of an U.2 disk is provided by a system clock or provided by a mainboard on-board clock chip, the system clock is adopted by default, and when the system clock cannot be provided, the system clock can be switched to an on-board clock through the dial Switch (SW);

the PCIE driver/Repeater redriver comprises a driver/Repeater circuit, and redrivers are realized by adjusting the output amplitude and the balance value of an input PCIE signal through the driver/Repeater circuit;

the U.2 connector includes power, low-speed signal, clock signal, high-speed signal, and the clock signal provides the U.2 dish with the PCIE clock.

Further, the U.2 connector power supply is direct current 12V.

Further, the U.2 connector low-speed signal is a single-ended GPIO interface.

Furthermore, the U.2 connector high-speed signal has 6 paths including 2 paths of SATA/SAS signal positions and 4 paths of PCIe interface signal positions.

Further, the 4-path PCIe interface signal position is set to be a 2-path X2 or 1-path X4 interface signal position.

The PCIE driver/Repeater driver re-drives the PCIE signal, thereby improving the signal quality.

The PCIE clock selection circuit provides multiple sources for U.2 disk PCIE clock sources, and improves product compatibility.

The utility model discloses realize the switching with U.2 interface and 3U VPX interface, remain the advantage of two kinds of interfaces, can improve the maintainability of product, improve product life, realized U.2 dish and extended the application.

Drawings

Fig. 1 is a schematic block diagram of an adapter plate structure for implementing conversion from an U.2 interface to a 3U VPX interface according to the present invention.

Detailed Description

For a better understanding of the objects, technical solutions and advantages of the present invention, the following description, together with the accompanying drawings and an embodiment of the present invention, will make a further detailed description of the present invention, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended to limit the present invention.

Referring to fig. 1, fig. 1 shows a schematic block diagram of a patch panel converting an U.2 interface into a 3U VPX interface. The present embodiment adopts a standard 3U VPX structure, and complies with the VITA specification standard, with VPX and U.2 connectors as external physical interfaces.

The 3U VPX connector 101 adopts a connector defined by VITA specification, the connector is divided into three types (models of TE herein) including a P0 type of 1410189-3, a P1 type of 1410187-4, a P1410187 type of 1410187-3, and the P1410187 connector has no signal connection.P 1410187 not only provides a DC12 1410187 for working as a 1410187 disk to provide 12V power supply input, but also provides a reset signal and a system Clock required by working of the 1410187 disk.4 groups of signal positions before the P1410187 connector are connected with PCIE 3.0X 1410187 of the PCIE 72 disk, so that the switching of the 1410187 interface to the 3U VPX interface is realized, the P1410187 is a high-speed connector which can fully play the characteristic of fast read-write speed of the 1410187 disk, the PCIE 3.0X 1410187 has a theoretical bandwidth as high-speed, the PCIE 72 is as high-speed interface, the PCIE 72 has a theoretical bandwidth as high as 32Gbps, meanwhile, the multi-GIg-RT 1410187 connectors have the advantages of being connected with a compact and firm connection, low insertion loss and low as well as a USB interface, the life cycle Clock signal output of an MH signal output signal, a USB interface signal output signal, a USB interface switch compatible with a USB interface of a USB interface switch, a USB interface of a USB interface switch 72, a USB interface of a USB 3, a USB 3-3, a USB interface of a USB 3-3, a USB interface of a USB interface, a USB interface of a USB 3, a USB interface of a USB interface, a USB interface of a USB drive circuit board, a USB.

Claims (5)

1. An adapter board for converting an U.2 interface into a 3U VPX interface, comprising: a 3U VPX connector, a PCIE clock selection circuit, a PCIE driver/Repeater redriver, and an U.2 connector;

the 3U VPX connector comprises three groups of sub-connectors, wherein the first group of sub-connectors are 1 8-column 7-row RT2 connectors defined on the 3U VPX board connector, and the second group of sub-connectors and the third group of sub-connectors are 2 16-column 7-row RT2 connectors defined on the 3U VPX board connector respectively; the first group of sub-connectors are public connectors and provide a maintenance management bus, a test bus and a power supply signal; the second set of sub-connectors provides 32 pairs of differential pair signals and 8 single-ended signals; a third set of sub-connectors, which may be defined as either differential signals or as single-ended signals;

the PCIE clock selection circuit (102) comprises a dial Switch (SW), wherein a clock of an U.2 disk is provided by a system clock or provided by a mainboard on-board clock chip, the system clock is adopted by default, and when the system clock cannot be provided, the system clock can be switched to an on-board clock through the dial Switch (SW);

the PCIE driver/Repeater redriver comprises a driver/Repeater circuit, and redrivers are realized by adjusting the output amplitude and the balance value of an input PCIE signal through the driver/Repeater circuit;

the U.2 connector includes power, low-speed signal, clock signal, high-speed signal, and the clock signal provides the U.2 dish with the PCIE clock.

2. The patch panel of claim 1, wherein the patch panel is used for switching an U.2 interface to a 3U VPX interface, and comprises: the power supply of the U.2 connector is direct current 12V.

3. The patch panel of claim 1, wherein the patch panel is used for switching an U.2 interface to a 3U VPX interface, and comprises: the U.2 connector low-speed signal is a single-ended GPIO interface.

4. The patch panel of claim 1, wherein the patch panel is used for switching an U.2 interface to a 3U VPX interface, and comprises: the U.2 connector high-speed signal has 6 paths including 2 paths of SATA/SAS signal positions and 4 paths of PCIe interface signal positions.

5. The patch panel of claim 4, wherein the patch panel is used for switching an U.2 interface to a 3U VPX interface, and comprises: the 4-path PCIe interface signal position is set to be a 2-path X2 or 1-path X4 interface signal position.

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