CN211019432U

CN211019432U - Chip packaging structure

Info

Publication number: CN211019432U
Application number: CN201922167173.3U
Authority: CN
Inventors: 胡亮; 刘平; 余玉明; 刘生良
Original assignee: GUANGDONG HERON PHOTOELECTRIC CO Ltd
Current assignee: GUANGDONG HERON PHOTOELECTRIC CO Ltd
Priority date: 2019-12-05
Filing date: 2019-12-05
Publication date: 2020-07-14
Anticipated expiration: 2029-12-05

Abstract

The utility model discloses a chip packaging structure, including first base plate and L ED chip, L ED chip set up in on the first base plate, still include the second base plate, the second base plate set up in on the side of L ED chip is kept away from to first base plate, be equipped with first through-hole on the first base plate, be equipped with the second through-hole on the second base plate, the second through-hole for first through-hole dislocation set, just first through-hole with second through-hole electricity switches on first through-hole and the second through-hole of dislocation set carry out electricity and switch on first base plate and second base plate, avoid using printing ink half consent technology, can not cause the false open circuit, the utility model discloses a chip packaging structure easily makes, and its quality easily manages and controls, and the production yield is high, and is with low costs.

Description

Chip packaging structure

Technical Field

The utility model relates to a chip package technical field especially relates to a chip package structure.

Background

The traditional packaging structure is that a plurality of through holes are manufactured on a PCB substrate, a plurality of different areas are arranged at each through hole on one side of the substrate, and conductive materials which are open-circuited are arranged at each through hole, the conductive materials are paved on the surface of the substrate, a plurality of L ED chips are arranged at each through hole on one side of the conductive materials, positive and negative contacts of the L ED chips are connected with the conductive materials on the surface of the substrate through conductive wires, protective colloid is packaged on the surface of the L ED chips, and finally, L ED which is distributed in a whole edition is divided into single L ED through a cutting process.

For micro-size L ED, the PCB substrate structure mostly adopts an ink half hole plugging process, namely, the ink in the hole half plug ink cannot be completely plugged, a pad on the back surface of the hole plug is windowed, and the depth requirement is met.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is: the chip packaging structure is easy to manufacture and manage and control quality.

In order to solve the technical problem, the utility model discloses a technical scheme be:

the utility model provides a chip packaging structure, includes first base plate and L ED chip, L ED chip set up in on the first base plate, still include the second base plate, the second base plate set up in the first base plate is kept away from on the side of L ED chip, be equipped with first through-hole on the first base plate, be equipped with the second through-hole on the second base plate, the second through-hole for first through-hole dislocation set, just first through-hole with second through-hole electrical conduction.

Furthermore, a first conducting layer is arranged on the inner side wall of the first through hole, a second conducting layer is arranged on the inner side wall of the second through hole, and the first conducting layer is connected with the second conducting layer.

Furthermore, a packaging colloid layer is arranged on one side surface of the first substrate close to the L ED chip.

Furthermore, the material of the first substrate is BT or FR4, and the material of the second substrate is BT or FR 4.

Furthermore, the first substrate and the second substrate are provided with electroplated layers, and the electroplated layers are made of at least one of silver and gold.

The beneficial effects of the utility model reside in that: first base plate and second base plate carry out electrical conduction through dislocation set's first through-hole and second through-hole, avoid using printing ink half consent technology, can not cause the false open circuit, the utility model discloses a chip packaging structure easily makes, and its quality easily manages and controls, and the production yield is high, and is with low costs.

Drawings

Fig. 1 is a schematic partial structural view of a chip package structure according to a first embodiment of the present invention;

fig. 2 is a cross-sectional view of a chip package structure according to a first embodiment of the present invention;

fig. 3 is a schematic diagram of a chip package structure manufactured by an ink half-via process in the prior art.

Description of reference numerals:

1. the LED packaging structure comprises a first substrate, a first through hole 11, a first conducting layer 12, a 2, L ED chip, a second substrate 3, a second through hole 31, a second conducting layer 32 and a packaging colloid layer 4.

Detailed Description

In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

The utility model discloses the most crucial design lies in: the first substrate and the second substrate are electrically conducted through the first through holes and the second through holes which are arranged in a staggered mode, the ink semi-hole plugging process is avoided, false open circuit cannot be caused, and manufacturing is easy.

Referring to fig. 1 and 2, a chip package structure includes a first substrate 1 and an L ED chip 2, the L ED chip 2 is disposed on the first substrate 1, and further includes a second substrate 3, the second substrate 3 is disposed on a side surface of the first substrate 1 away from the L ED chip 2, a first through hole 11 is disposed on the first substrate 1, a second through hole 31 is disposed on the second substrate 3, the second through hole 31 is disposed in a staggered manner with respect to the first through hole 11, and the first through hole 11 is electrically connected to the second through hole 31.

From the above description, the beneficial effects of the present invention are: first base plate and second base plate carry out electrical conduction through dislocation set's first through-hole and second through-hole, avoid using printing ink half consent technology, can not cause the false open circuit, the utility model discloses a chip packaging structure easily makes, and its quality easily manages and controls, and the production yield is high, and is with low costs.

Further, a first conductive layer 12 is arranged on the inner side wall of the first through hole 11, a second conductive layer 32 is arranged on the inner side wall of the second through hole 31, and the first conductive layer 12 is connected with the second conductive layer 32.

Furthermore, a packaging colloid layer 4 is arranged on one side surface of the first substrate 1 close to the L ED chip 2.

Furthermore, the material of the first substrate 1 is BT or FR4, and the material of the second substrate 3 is BT or FR 4.

As can be seen from the above description, the material of the substrate can be selected according to the requirement.

Furthermore, the first substrate 1 and the second substrate 3 are provided with electroplated layers, and the electroplated layers are made of at least one of silver and gold.

Referring to fig. 1 and fig. 2, a first embodiment of the present invention is:

a chip packaging structure comprises a first substrate 1 and L ED chips 2, wherein L ED chips 2 are arranged on the first substrate 1, the number of L ED chips 2 can be set as required, L ED chips 2 can be communicated with the first substrate 1 through conductive wires, L ED chips 2 can be reversely arranged on a surface line of the first substrate 1 to form circuit conduction, a packaging colloid layer 4 is arranged on one side of the first substrate 1 close to L ED chips 2, the chip packaging structure further comprises a second substrate 3, the second substrate 3 is arranged on one side of the first substrate 1 far away from L ED chips 2, a first through hole 11 is arranged on the first substrate 1, a second through hole 31 is arranged on the second substrate 3, the second through hole 31 is arranged in a staggered mode relative to the first through hole 11, the first through hole 11 is electrically communicated with the second through hole 31, a first conductive layer 12 is arranged on the inner side wall of the first through hole 11, a second conductive layer 32 is arranged on the inner side wall of the second through hole 31, the first through hole 12 and the second through hole 32 are electrically connected with the second through hole 31, and the second substrate 11, and the second through hole 31 can be made of a gold-plated layer, or a second plated layer, wherein the substrate is made of BT 3, the substrate, the material is at least a material, and the material of the substrate 1, and the substrate, the material of the substrate 3, and the.

Fig. 3 is a chip package structure manufactured by using an ink half-plugging process, in which a via hole is located at four corners, and when the via hole is cut into a single L ED package structure, a copper foil (dotted line in the figure) at a connection position on the back of the via hole is inevitably in contact with a cutting knife, which may generate cutting burrs and affect the soldering performance of a product.

To sum up, the utility model provides a pair of chip packaging structure can not cause the spurious nature to open a way, easily preparation, and its quality is easily managed and controlled, and the production yield is high, and with low costs.

The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.

Claims

1. The utility model provides a chip package structure, includes first base plate and L ED chip, L ED chip set up in on the first base plate, its characterized in that still includes the second base plate, the second base plate set up in the first base plate is kept away from on the side of L ED chip, be equipped with first through-hole on the first base plate, be equipped with the second through-hole on the second base plate, the second through-hole for first through-hole dislocation set, just first through-hole with second through-hole electrical conduction.

2. The chip package structure according to claim 1, wherein a first conductive layer is disposed on an inner sidewall of the first through hole, a second conductive layer is disposed on an inner sidewall of the second through hole, and the first conductive layer is connected to the second conductive layer.

3. The chip package structure according to claim 1, wherein a package glue layer is disposed on a side of the first substrate close to the L ED chip.

4. The chip package structure according to claim 1, wherein the first substrate is BT or FR4, and the second substrate is BT or FR 4.

5. The chip package structure according to claim 1, wherein the first substrate and the second substrate are provided with an electroplated layer, and the electroplated layer is made of at least one of silver and gold.