CN211015192U

CN211015192U - Band gap reference circuit

Info

Publication number: CN211015192U
Application number: CN201922187607.6U
Authority: CN
Inventors: 黄敬馨; 章国豪; 刘祖华
Original assignee: Guangzhou Suiyuan Microelectronics Technology Co ltd; Bluetec Microwaves Inc
Current assignee: Guangzhou Suiyuan Microelectronics Technology Co ltd; Bluetec Microwaves Inc
Priority date: 2019-12-09
Filing date: 2019-12-09
Publication date: 2020-07-14
Anticipated expiration: 2029-12-09

Abstract

The utility model discloses a band gap reference circuit, including producing unit, power supply rejection ratio improvement unit, biasing unit circuit, it includes a basic current mirror band gap reference circuit structure to produce the unit, power supply rejection ratio improvement unit includes an operational amplifier, operational amplifier includes first input, second input and output, biasing circuit includes a PMOS pipe, including first PMOS pipe, second PMOS pipe, third PMOS pipe, first NMOS pipe, second NMOS pipe, first triode, second triode, first resistance and second resistance, the drain electrode junction of second resistance and third PMOS pipe is the reference voltage output; the beneficial effects of the utility model are that, reached and made the more unanimous effect of positive negative input end voltage for band gap reference circuit's precision further improves.

Description

Band gap reference circuit

Technical Field

The utility model belongs to the technical field of integrated circuit, specifically be a band gap reference circuit.

Background

As a reference circuit, the accuracy of the circuit is very important. The band-gap reference power supply to be improved in the patent adopts an operational amplifier to clamp, and aims to ensure that the voltages of positive and negative input ends are the same, but the voltages of the positive and negative input ends can only be close to be equal as far as possible due to factors such as process deviation. In order to further improve the circuit accuracy, the conventional solution is to increase the gain of the operational amplifier, but this increases the complexity of the design of the operational amplifier and increases the chip area. The solution proposed by this patent is to solve this problem by means of feedback.

The working principle of the band-gap reference circuit is that the characteristic that band-gap voltage of a semiconductor material is irrelevant to temperature is utilized, and the negative temperature coefficient of base electrode-emitter voltage of a bipolar transistor and the positive temperature coefficient of the difference value of the base electrode-emitter voltage of the two bipolar transistors under different current densities are utilized to compensate each other, so that the output voltage reaches very low temperature drift.

The operational amplifier in the bandgap reference circuit in the prior art adopts a conventional two-stage amplifier structure as shown in the figure, which has three disadvantages: 1. an additional bias voltage vbias2 is required; 2. the voltage consistency of the positive input end and the negative input end is not good, so that the precision of the band gap voltage source is limited; 3. when the power supply voltage is used, the layout design also has complexity, and the design difficulty and the yield are increased. The solution proposed by this patent is to solve this problem by means of feedback.

SUMMERY OF THE UTILITY MODEL

Technical problem to be solved

Not enough to prior art, the utility model provides a band gap reference circuit solves the positive negative input end voltage uniformity of operational amplifier not enough among the band gap reference circuit among the prior art, and the area is problem slightly bigger.

(II) technical scheme

In order to achieve the above object, the utility model provides a following technical scheme: in order to solve the above technical problem, the utility model provides a band gap circuit, including producing unit, power supply rejection ratio improvement unit, biasing unit circuit. The generating unit comprises a basic current mirror band-gap reference circuit structure. The power supply rejection ratio improving unit comprises an operational amplifier, and the operational amplifier comprises a first input end, a second input end and an output end. The bias circuit includes a PMOS transistor.

The generating unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first triode, a second triode, a first resistor and a second resistor, wherein the joint of the second resistor and the drain electrode of the third PMOS tube is a reference voltage output end.

The operational amplifier comprises a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a third resistor. The grid end of the fourth PMOS tube is the second input end of the operational amplifier, and the grid end of the fifth PMOS tube is the first input end of the operational amplifier. The source end of the fourth PMOS tube is the output end of the operational amplifier.

And the grid electrode of the fourth PMOS tube is the second input end of the operational amplifier, the source electrode is connected with the source electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube, and the drain electrode is connected with the drain electrode of the third NMOS tube and the grid electrode of the fifth NMOS tube.

And the grid electrode of the fifth PMOS tube is the first input end of the operational amplifier, the source electrode is connected with the source electrode of the fourth PMOS tube, and the drain electrode is connected with the drain electrode of the fourth NMOS tube and the grid electrode of the fourth NMOS tube.

And the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is connected with a second power supply end, and the drain electrode of the third NMOS tube is connected with the grid electrode of the fifth NMOS tube.

And the grid electrode of the fourth NMOS tube is connected to the grid electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is connected to a second power supply end, and the drain electrode of the fourth NMOS tube is connected to the grid electrode of the fourth NMSO tube and the drain electrode of the fifth PMOS tube.

And the grid electrode of the fifth NMOS tube is connected to the drain electrode of the fourth PMOS tube and the drain electrode of the third NMOS tube, the source electrode of the fifth NMOS tube is connected to the third resistor, and the drain electrode of the fifth NMOS tube is connected to the source electrode of the fourth PMOS tube.

One end of the third resistor is connected to the source electrode of the fifth NMOS tube, and the other end of the third resistor is connected to the second power supply end.

The grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the drain electrode of the first PMOS transistor and the first output end of the amplifier, the source electrode of the first PMOS tube is connected with the output end of the amplifier, and the drain electrode of the first PMOS tube is connected with the first input end of the operational amplifier, the drain electrode of the first NMOS tube and the grid electrode of the first PMOS tube.

The grid electrode of the second PMOS transistor is connected with the grid electrodes of the first PMOS transistor and the third PMOS transistor, the source electrode of the second PMOS transistor is connected with the output end of the amplifier, and the drain electrode of the second PMOS transistor is connected with the second input end of the operational amplifier and the drain electrode of the second NMOS transistor.

And the grid electrode of the third PMOS transistor is connected with the grid electrodes of the first PMOS transistor and the second PMOS transistor, the source electrode of the third PMOS transistor is connected with the output end of the amplifier, and the drain electrode of the third PMOS transistor is connected with the second resistor of the operational amplifier.

The grid electrode of the first NMOS transistor is connected with the grid electrode of the second NMOS transistor, the source electrode of the first NMOS transistor is connected with the first resistor, and the drain electrode of the first NMOS transistor is connected with the first input end of the operational amplifier and the drain electrode of the first PMOS transistor.

The grid electrode of the second NMOS transistor is connected with the drain electrode of the second NMOS tube and the second input end of the operational amplifier, the source electrode of the second NMOS transistor is connected with the source electrode of the second triode, and the drain electrode of the second NMOS transistor is connected with the drain electrode of the second PMOS tube.

The first triode is a PNP triode, the base electrode of the first triode is connected to the second power supply end, the collector electrode of the first triode and the base electrode of the second triode, the emitter electrode of the first triode is connected to the first resistor, and the collector electrode of the first triode is connected to the second power supply end.

The second triode is a PNP triode, the base electrode of the second triode is connected to a second power supply end, the collector electrode of the second triode and the base electrode of the first triode, the emitter electrode of the second triode is connected to the second resistor and the second NMOS tube, and the collector electrode of the second triode is connected to the second power supply end.

The first power supply terminal is an operating voltage of the circuit, the second power supply terminal is a ground terminal, and the third power supply terminal is a bias voltage of the circuit.

The bias circuit comprises a PMOS transistor, wherein the grid electrode of the PMOS transistor is connected to a third power supply end, the source electrode of the PMOS transistor is connected to the first power supply end, and the drain electrode of the PMOS transistor is connected to the output end of the operational amplifier, the first PMOS transistor, the second PMOS transistor and the third PMOS transistor.

(III) advantageous effects

Compared with the prior art, the utility model provides a band gap reference circuit possesses following beneficial effect:

the beneficial effects of the utility model are that, reached and made the more unanimous effect of positive negative input end voltage for band gap reference circuit's precision further improves.

Drawings

Fig. 1 shows a structure of a bandgap reference circuit amplifier according to the prior art.

Fig. 2 shows a structure of a bandgap reference circuit amplifier according to the present invention.

Fig. 3 shows a bandgap reference circuit structure to be improved in the present invention.

Detailed Description

The bandgap reference circuit of the present invention will now be described in greater detail with reference to the schematic drawings in which preferred embodiments of the invention are shown, it being understood that those skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.

The utility model discloses a core thought lies in, provides a band gap reference circuit's amplifier improvement scheme for original band gap reference voltage source's precision is higher.

The bandgap reference circuit to be improved is shown in fig. 3, and the generating unit comprises a basic current mirror bandgap reference circuit structure. The power supply rejection ratio improving unit comprises an operational amplifier, and the operational amplifier comprises a first input end, a second input end and an output end. The bias circuit includes a PMOS transistor. The generating unit is characterized by comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first triode, a second triode, a first resistor and a second resistor, wherein the connection position of the second resistor and the drain electrode of the third PMOS tube is a reference voltage output end. The grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the drain electrode of the first PMOS transistor and the first output end of the amplifier, the source electrode of the first PMOS tube is connected with the output end of the amplifier, and the drain electrode of the first PMOS tube is connected with the first input end of the operational amplifier, the drain electrode of the first NMOS tube and the grid electrode of the first PMOS tube. The grid electrode of the second PMOS transistor is connected with the grid electrodes of the first PMOS transistor and the third PMOS transistor, the source electrode of the second PMOS transistor is connected with the output end of the amplifier, and the drain electrode of the second PMOS transistor is connected with the second input end of the operational amplifier and the drain electrode of the second NMOS transistor. The third PMOS transistor is characterized in that a gate of the third PMOS transistor is connected to gates of the first PMOS transistor and the second PMOS transistor, a source of the third PMOS transistor is connected to an output end of the amplifier, and a drain of the third PMOS transistor is connected to a second resistor of the operational amplifier. The grid electrode of the first NMOS transistor is connected with the grid electrode of the second NMOS transistor, the source electrode of the first NMOS transistor is connected with the first resistor, and the drain electrode of the first NMOS transistor is connected with the first input end of the operational amplifier and the drain electrode of the first PMOS transistor. The grid electrode of the second NMOS transistor is connected with the drain electrode of the second NMOS tube and the second input end of the operational amplifier, the source electrode of the second NMOS transistor is connected with the source electrode of the second triode, and the drain electrode of the second NMOS transistor is connected with the drain electrode of the second PMOS tube. The first triode is a PNP triode, the base electrode of the first triode is connected to the second power supply end, the collector electrode of the first triode and the base electrode of the second triode, the emitter electrode of the first triode is connected to the first resistor, and the collector electrode of the first triode is connected to the second power supply end. The second triode is a PNP triode, the base electrode of the second triode is connected to a second power supply end, the collector electrode of the second triode and the base electrode of the first triode, the emitter electrode of the second triode is connected to the second resistor and the second NMOS tube, and the collector electrode of the second triode is connected to the second power supply end. The first power supply terminal is an operating voltage of the circuit, the second power supply terminal is a ground terminal, and the third power supply terminal is a bias voltage of the circuit. The bias circuit comprises a PMOS transistor, wherein the grid electrode of the PMOS transistor is connected to a third power supply end, the source electrode of the PMOS transistor is connected to the first power supply end, and the drain electrode of the PMOS transistor is connected to the output end of the operational amplifier, the first PMOS transistor, the second PMOS transistor and the third PMOS transistor.

The improved amplifier structure of the patent is shown in fig. 2, and the operational amplifier comprises a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a third resistor. The grid end of the fourth PMOS tube is the second input end of the operational amplifier, and the grid end of the fifth PMOS tube is the first input end of the operational amplifier. The source end of the fourth PMOS tube is the output end of the operational amplifier. And the grid electrode of the fourth PMOS tube is the second input end of the operational amplifier, the source electrode is connected with the source electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube, and the drain electrode is connected with the drain electrode of the third NMOS tube and the grid electrode of the fifth NMOS tube. And the grid electrode of the fifth PMOS tube is the first input end of the operational amplifier, the source electrode is connected with the source electrode of the fourth PMOS tube, and the drain electrode is connected with the drain electrode of the fourth NMOS tube and the grid electrode of the fourth NMOS tube. And the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is connected with a second power supply end, and the drain electrode of the third NMOS tube is connected with the grid electrode of the fifth NMOS tube. And the grid electrode of the fourth NMOS tube is connected to the grid electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is connected to a second power supply end, and the drain electrode of the fourth NMOS tube is connected to the grid electrode of the fourth NMSO tube and the drain electrode of the fifth PMOS tube. And the grid electrode of the fifth NMOS tube is connected to the drain electrode of the fourth PMOS tube and the drain electrode of the third NMOS tube, the source electrode of the fifth NMOS tube is connected to the third resistor, and the drain electrode of the fifth NMOS tube is connected to the source electrode of the fourth PMOS tube. One end of the third resistor is connected to the source electrode of the fifth NMOS tube, and the other end of the third resistor is connected to the second power supply end.

The utility model discloses a band gap reference circuit's theory of operation is as follows, through being connected to output (output) in the input loop, constitutes a negative feedback system, makes the voltage of positive negative input more unanimous through the feedback. When negative feedback is formed, the tail current source of the first-stage amplifier and the current source load of the second-stage circuit can be combined into one current source, and the purpose of accurately distributing current is achieved through other MOS (metal oxide semiconductor) tubes and resistors of the regulating circuit. When the bias circuit of the whole bandgap is considered, the current source circuit can be removed, and an external bandgap bias circuit provides a path of current, so that the aims of reducing the area and simplifying the layout design are fulfilled.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front end", "rear end", "both ends", "one end", "the other end" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element to which the reference is made must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The band-gap reference circuit is characterized by comprising a generating unit, a power supply rejection ratio improving unit and a bias unit circuit, wherein the generating unit comprises a basic current mirror band-gap reference circuit structure, the power supply rejection ratio improving unit comprises an operational amplifier, the operational amplifier comprises a first input end, a second input end and an output end, and the bias unit circuit comprises a PMOS (P-channel metal oxide semiconductor) tube.

2. A bandgap reference circuit as claimed in claim 1, wherein: the high-voltage power supply comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first triode, a second triode, a first resistor and a second resistor, wherein the connection position of the second resistor and the drain electrode of the third PMOS tube is a reference voltage output end.

3. A bandgap reference circuit as claimed in claim 1, wherein: the operational amplifier comprises a fourth PMOS tube, a fifth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a third resistor, wherein the gate end of the fourth PMOS tube is the second input end of the operational amplifier, the gate end of the fifth PMOS tube is the first input end of the operational amplifier, and the source end of the fourth PMOS tube is the output end of the operational amplifier.

4. A bandgap reference circuit as claimed in claim 1, wherein: the grid electrode of the fourth PMOS tube is the second input end of the operational amplifier, the source electrode is connected with the source electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube, and the drain electrode is connected with the drain electrode of the third NMOS tube and the grid electrode of the fifth NMOS tube.

5. A bandgap reference circuit as claimed in claim 1, wherein: the grid electrode of the fifth PMOS tube is the first input end of the operational amplifier, the source electrode is connected with the source electrode of the fourth PMOS tube, and the drain electrode is connected with the drain electrode of the fourth NMOS tube and the grid electrode of the fourth NMOS tube.

6. A bandgap reference circuit as claimed in claim 1, wherein: the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is connected with the second power supply end, and the drain electrode of the third NMOS tube is connected with the grid electrode of the fifth NMOS tube.

7. A bandgap reference circuit as claimed in claim 1, wherein: the grid electrode of the fourth NMOS tube is connected to the grid electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is connected to the second power supply end, and the drain electrode of the fourth NMOS tube is connected to the grid electrode of the fourth NMSO tube and the drain electrode of the fifth PMOS tube.

8. A bandgap reference circuit as claimed in claim 1, wherein: the grid electrode of the fifth NMOS tube is connected to the drain electrode of the fourth PMOS tube and the drain electrode of the third NMOS tube, the source electrode of the fifth NMOS tube is connected to the third resistor, and the drain electrode of the fifth NMOS tube is connected to the source electrode of the fourth PMOS tube.

9. A bandgap reference circuit as claimed in claim 1, wherein: one end of the third resistor is connected to the source electrode of the fifth NMOS tube, and the other end of the third resistor is connected to the second power supply end.

10. A bandgap reference circuit as claimed in claim 2, wherein: the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the drain electrode of the first PMOS tube and the first output end of the amplifier, the source electrode of the first PMOS tube is connected with the output end of the amplifier, and the drain electrode of the first PMOS tube is connected with the first input end of the operational amplifier, the drain electrode of the first NMOS tube and the grid electrode of the first PMOS tube.