CN210956691U - Double-junction laminated battery - Google Patents

Abstract

A double-junction laminated cell belongs to the field of solar cells. The double-junction laminated cell comprises a bottom cell, a top cell and a transparent conducting layer. The bottom cell is based on a semiconductor material and comprises a P-type silicon layer, an N-type doped layer formed on the front surface of the P-type silicon layer, a front passivation layer on the N-type doped layer and a back passivation layer on the back surface of the P-type silicon layer. The transparent conductive layer is bonded on the front passivation layer of the bottom cell. The top cell is based on perovskite material and the perovskite layer has a hole transport layer on the front side and an electron transport layer on the back side. The perovskite layer is combined on the transparent conductive layer through the electron transport layer on the back surface. The double-junction tandem cell in the present application combines a semiconductor solar cell and a perovskite solar cell, thereby enabling an absorption wavelength range to be extended, thereby utilizing more light energy.

Description

Double-junction laminated battery

Technical Field

The application relates to the field of solar cells, in particular to a double-junction laminated cell.

Background

Photovoltaic power generation is a technology of directly converting light energy into electric energy by using the photovoltaic effect of a semiconductor interface. If light impinges on the solar cell and light is absorbed at the interface layer, photons of sufficient energy can excite electrons from covalent bonds in the P-type silicon and N-type silicon so that electron-hole pairs are generated. The electrons and holes near the interface layer will be separated from each other by the electric field effect of space charge before recombination. Electrons move to the positively charged N-region and holes to the negatively charged P-region. The sun shines on a semiconductor p-n junction to form a new hole-electron pair, under the action of an electric field built in the p-n junction, holes flow from an n region to a p region, electrons flow from the p region to the n region, and current is formed after a circuit is switched on.

Currently, solar cells mainly use crystalline silicon as a substrate material. Due to the periodic destruction of the silicon wafer surface, a large number of dangling bonds (dangling bonds) are generated, so that a large number of defect energy levels located in the band gap exist on the crystal surface. In addition, the deposition of dislocations, chemical residues and surface metals can introduce defect energy levels, so that the surface of the silicon wafer becomes a recombination center, a large surface recombination rate is caused, and the conversion efficiency is limited.

Based on this, a solar cell back passivation technology is developed, and compared with a conventional solar cell, a back Passivation (PERC) solar cell can greatly improve open-circuit voltage and short-circuit current, greatly improve conversion efficiency, has a simple preparation process and good compatibility with a production line, and can effectively control the manufacturing cost of the solar cell. However, solar cell conversion efficiency based on existing back passivation techniques is yet to be improved.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings, the present application provides a double-junction tandem cell to partially or completely improve, and even solve, the problem in the related art that the back passivation technology causes the cell conversion efficiency of the solar cell to be difficult to further improve.

The application is realized as follows:

in a first aspect, examples of the present application provide a double junction tandem cell.

The double-junction stacked cell includes a bottom cell, a transparent conductive layer, and a top cell.

The bottom cell is based on a semiconductor material and has a P-type silicon layer, an N-type doped layer formed on a front surface of the P-type silicon layer, a front passivation layer on the N-type doped layer, and a back passivation layer on a back surface of the P-type silicon layer.

The transparent conductive layer is bonded on the front passivation layer of the bottom cell.

The top cell is based on perovskite material and the perovskite layer has a hole transport layer on the front side and an electron transport layer on the back side. The perovskite layer of the top cell is bonded on the transparent conductive layer through the electron transport layer on the back side.

In the implementation process, the double-junction tandem cell provided by the embodiment of the application combines the semiconductor solar cell and the perovskite solar cell, so that the spectral response range is expanded, and a strong absorption effect on near infrared light can be realized. The configuration mode of the double batteries is beneficial to realizing current matching, improving the open-circuit voltage of the batteries and further improving the conversion efficiency. Due to the double-cell configuration, the perovskite cell in the double-cell structure is used as a top cell to absorb photons with shorter wavelength, and the silicon solar cell with smaller forbidden band width is used as a bottom cell to absorb photons with longer wavelength.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the description of the embodiments or the prior art will be briefly described below.

FIG. 1 is a schematic diagram of a back passivated solar cell;

fig. 2 shows a schematic structural diagram of a double-junction tandem cell provided in an embodiment of the present application.

Icon: 100-back passivated solar cells; 102-a back side gate electrode; 103-backside local contact; 101-P type silicon chip substrate; 104-front silver grid lines; 105-front side antireflection film; 106-lightly doped emitter; 107-heavily doped emitter; 200-double junction tandem cell; 201-back electrode; 202-an anti-reflective layer; 203-back side passivation layer; 204-aluminum doped region; 205-P-type silicon layer; 206-N type doped layer; 207-front side passivation layer; 208-a transparent conductive layer; 209-electron transport layer; 210-a perovskite layer; 211-hole transport layer; 212-a buffer layer; 213-front electrode.

Detailed Description

Embodiments of the present application will be described in detail below with reference to examples, but those skilled in the art will appreciate that the following examples are only illustrative of the present application and should not be construed as limiting the scope of the present application. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.

The following is a detailed description of a double-junction tandem cell and a method for manufacturing the same according to embodiments of the present application:

it has long been a difficulty in the art to improve the conversion efficiency of solar cells. In order to make a breakthrough, many researches on the structure and material aspects of the solar cell are carried out in the industry. Through research on solar cells, the inventor finds that the existing solar cells have the following problems: solar cells mainly use crystalline silicon as a substrate material. A large number of dangling bonds (dangling bonds) are generated due to the destruction of the periodicity of the silicon wafer surface, and thus a large number of defect levels located in the band gap exist on the crystal surface. In addition, the deposition of dislocations, chemical residues and surface metals can introduce defect energy levels, so that the surface of the silicon wafer becomes a recombination center, a large surface recombination rate is caused, and the conversion efficiency is limited.

Compared with the conventional battery, the back passivated battery can reduce the interface state of the back surface of the battery piece, improve the passivation capability, and improve the long-wave response and the short-circuit current by prolonging the light path, so that the conversion efficiency of the back passivated battery is improved by 1.0-1.2% or even more than that of the conventional battery. Therefore, the back passivation technique can improve the aforementioned problems to some extent.

The present inventors have implemented a back passivation technique in order to conduct research to find existing problems or defects in order to improve them.

The back passivation technique is implemented in a back passivated solar cell 100, the structure of which is disclosed in fig. 1. The main processes of the back passivated solar cell 100 are: texturing, phosphorus diffusion (N-type doping), back etching, annealing, back film coating AlOx, back film coating SiNx, front film coating SiNx, back passivation layer laser grooving, printing of a front/back electrode electric field, and high-temperature sintering to finally form the back passivation solar cell.

By the arrangement of the back passivation structure, the back interface state of the manufactured solar cell can be reduced, the passivation effect can be improved, the light path can be prolonged, and the long-wave response and the short-circuit current can be improved. The back electrode is etched through laser to selectively etch part of the passivation layer to expose the silicon layer, and then back electric field aluminum paste is printed in the laser etching area to be in direct contact with the silicon layer, so that electric conduction is achieved.

Thus, the back passivated solar cell has a back side gate electrode 102; a back side local contact 103, which is doped with aluminum to form a P + doping type; a P-type silicon wafer substrate 101; a front silver grid line 104; a front antireflection film 105; a lightly doped emitter 106(N + doping type); heavily doped emitter 107(N + + doping type).

In the structure, the back passivation film and the P-type silicon wafer substrate form Al₂O₃-a Si contact interface. Due to Al₂O₃the/Si contact interface has higher fixed negative charge density, so that the obvious field effect passivation characteristic can be obtained by shielding minority carriers (electrons) on the surface of the P-type silicon wafer substrate, and the passivation effect of the back of the silicon wafer is greatly improved. In practice, use is made ofAl₂O₃The silicon chip surface recombination rate can be reduced to 10 by being used as a passivation layer²In the order of cm/s.

In the implementation process, the inventor still finds that a good balance between the conversion efficiency and the process feasibility of the solar cell based on the back passivation technology is difficult to achieve. The process is implementable compared to the selection of improved materials for solar cell fabrication to increase conversion efficiency. In other words, it is relatively more difficult and the improvement of the conversion efficiency of the solar cell by improving the manufacturing material is not obvious, and the conversion efficiency can be effectively improved by combining the top cell and the bottom cell in the embodiment of the present application. For example, at present, for the problem of improving the conversion efficiency of solar cells, a method is generally adopted to develop new solar cell manufacturing materials, mainly new semiconductor materials; or by reducing incident light loss.

The inventors have considered in their studies that the causes of the above problems include at least the following.

Firstly, the energy distribution of the solar spectrum is wide, and the photoelectric response spectral range of a single semiconductor material is very narrow relative to the solar spectrum. This limits the improvement of the conversion efficiency from the mechanism.

Secondly, AlO is adopted in the back passivation technology applied in large scale at present_X+SiN_XThe structure is a main back passivation film layer. However, in such a back passivation structure, the presence of Si-H and-NH bonds tends to cause the film to loosen and accumulate a large number of pinholes, and, after high temperature annealing, hydrogen is removed from the Si-H bonds leaving unsaturated Si +. The excessive Si + can be bonded to form silicon aggregates (silicon islands), so that the passivation effect is directly influenced, the efficiency improvement of the back passivation battery is further limited, and the economic benefit of high-efficiency battery production is reduced.

For the above two reasons, the inventors propose an improved solution to make more use of the light energy and improve the passivation effect. In some examples of the present application, in order to fully utilize incident sunlight and improve the conversion efficiency of a solar cell, a perovskite solar cell having a large forbidden band width is used as a top cell to absorb photons having a short wavelength, and a silicon solar cell having a small forbidden band width is used as a bottom cell to absorb photons having a long wavelength.

The perovskite material has special ABX₃A crystal structure. It has high tolerance to crystal defects-in the case of crystals with a large number of defects, it remains structurally stable and facilitates diffusion migration of the defects. Meanwhile, the perovskite material has high carrier mobility, high diffusion length and minority carrier lifetime. Perovskite-based cells have higher open circuit voltages (>1V); the material has a high absorption coefficient in the wavelength range of 300nm to 900 nm.

In addition, perovskites are flexible and have a controllable band gap. Perovskite and crystalline silicon materials have low lattice mismatch and high defect tolerance. The perovskite battery with lower cost and the crystal silicon back passivation battery with the mature technology are combined to prepare the laminated battery, the spectral response is widened, the perovskite/crystal silicon back passivation laminated battery structure can be utilized, near-infrared photons are absorbed strongly, the current matching is realized, the open-circuit voltage of the battery is improved, and the conversion efficiency is further improved.

In an example, the improved solution proposed by the inventors is practiced in the form of a double junction tandem cell. As a whole, the double-junction tandem cell comprises two sub-cells, a bottom cell and a top cell, respectively, and the bottom cell and the top cell are contacted by a transparent conductive layer.

Wherein the bottom cell is made on the basis of semiconductor material. The bottom cell has a back passivation layer and a front passivation layer, and the back passivation layer is located on the back of the bottom cell and the front passivation layer is located on the front of the bottom cell. Based on the passivation structure, a transparent conductive layer is bonded on the front passivation layer of the bottom cell. In other words, in a double junction stacked cell, the transparent conductive layer is located between the bottom of the top cell and the front passivation layer of the bottom cell. The top cell is made of perovskite material, and the perovskite layer is combined on the transparent conducting layer through the electron transport layer on the back side.

Alternatively, the semiconductor material from which the bottom cell is made may be selected from a variety of materials, including, for example, silicon-based semiconductor cells, alloy semiconductor cells, or oxide semiconductor cells, based on the classification of the material. The alloy semiconductor comprises a cadmium telluride-based semiconductor battery, a copper indium gallium selenide-based semiconductor battery or a gallium arsenide-based semiconductor battery. The silicon-based semiconductor battery is a monocrystalline silicon-based semiconductor battery, a polycrystalline silicon-based semiconductor battery, a crystalline silicon-based semiconductor battery or an amorphous silicon-based alloy semiconductor. The silicon-based semiconductor battery is a monocrystalline silicon-based semiconductor battery, a polycrystalline silicon-based semiconductor battery, a crystalline silicon-based semiconductor battery or an amorphous silicon-based alloy semiconductor. In the example of the application, the bottom cell is a P-type silicon-based cell, and the front passivation layer is combined with the N-type doped layer of the P-type silicon-based cell.

Structurally, the top battery has a perovskite layer, and other different functions and structural layers can be selected according to different situations. For example, the top cell includes a hole transport layer bonded to the front side of the perovskite layer. Alternatively, the top cell includes a buffer layer bonded over the hole transport layer. Alternatively, the electrode of the top cell penetrates the buffer layer and is combined with the hole transport layer. Alternatively, the bottom cell includes an anti-reflective layer bonded under the backside passivation layer.

As an alternative embodiment, a double-junction tandem cell 200 in the present example is disclosed in fig. 2. The double-junction laminated battery is in a double-battery combined structure formed by connecting a perovskite top battery and a crystalline silicon bottom battery in series.

It includes from the back to the front in proper order:

an anti-reflection layer 202, a back passivation layer 203, a P-type silicon layer 205, an N-type doped layer 206, a front passivation layer 207, a transparent conductive layer 208, an electron transport layer 209, a perovskite layer 210, a hole transport layer 211, and a buffer layer 212 are sequentially stacked. As a structure for current extraction, the hole transport layer 211 is partially in contact with the front electrode 213, and the P-type silicon layer 205 is partially in contact with the back electrode 201 by P-type doping. The electron transmission layer of the top battery is adjacent to the N-type doping layer of the bottom battery, so that electron transmission is facilitated.

The above-mentioned layer structures can be made by using materials and processes which are conventional in the art, and need not be particularly limited. As an exemplary limitation, for example, perovskites have a forbidden bandwidth of 1.55eV to 1.8eV (e.g., 1.56eV, 1.58eV, 1.61eV, 1.62eV, 1.64eV, 1.67eV, 1.72eV, 1.75eV, or 1.79 eV). The thickness of the electron transport layer 209 is 80nm to 120nm (e.g., 81nm, 85nm, 89nm, 92nm, 96nm, 103nm, 108nm, 114nm, or 116 nm). The hole transport layer 211 has a thickness of 60nm to 100nm (e.g., 65nm, 69nm, 73nm, 77nm, 79nm, 82nm, 85nm, 93nm, or 95 nm). The buffer layer 212 has a thickness of 30nm to 60nm (e.g., 33nm, 36nm, 39nm, 47nm, 49nm, 55nm, or 59 nm). The transparent conductive layer 208 has a thickness of 8nm to 25nm (e.g., 9nm, 12nm, 16nm, 19nm, 21nm, 22nm, or 24 nm).

In terms of materials, the front electrode 213 may be a silver finger electrode, and the back electrode 201 may be an aluminum finger electrode. The buffer layer 212 may be selected to be molybdenum oxide or tungsten oxide. The hole transport layer 211 can be selected from nickel oxide, copper aluminum oxide, strontium copper oxide, 2',7,7' -tetrakis [ N, N-bis (4-methoxyphenyl) amino]-9,9' -spirobifluorene, poly [ bis (4-phenyl) (2,4, 6-trimethylphenyl) amine]Or 3-hexylthiophene. Alternatively, perovskite layer 210 may be formed of a material having ABX₃A crystal structure of the form wherein A represents methylamine or formamidinide, B represents lead, tin or antimony, and X represents iodine, bromine or chlorine. The electron transport layer 209 may be selected from aluminum oxide, tin oxide, zinc magnesium oxide, zinc tin oxide, or titanium dioxide. The transparent conductive layer 208 may be selected from zinc tin oxide, indium tungsten oxide, indium zinc oxide, indium titanium oxide, or zinc aluminum oxide. The front passivation layer 207 may optionally be silicon nitride. The N-type doped layer 206 may be optionally phosphorous oxychloride. The P-doped region of the P-type silicon layer 205 may be optionally doped with aluminum. The backside passivation layer 203 may be optionally AlO_xThe anti-reflective layer 202 is of the formula SiN_xWherein x is 0.37 to 0.52.

In an alternative example, a double junction tandem cell is one in which:

the back gate finger electrode is made of aluminum and has a thickness of 30-60 μm.

SiN may be optionally used for the anti-reflective layer_xThe thickness is 100nm to 130 nm.

AlO can be selected as the back passivation layer_xThe thickness is 5nm to 15 nm.

The P-type silicon layer can be selected from P-type crystalline silicon and has a thickness of 160-180 μm.

The N-type doped layer can select phosphorus as a doping element and has a thickness of 0.25nm to 1 nm.

SiN can be selected as the front passivation layer_xAnd the thickness is 70nm to 90 nm.

The transparent conductive layer can be ITO or IWO or IZO or ITiO or AZO, and has a thickness of 8nm to 25 nm.

TiO can be selected as the electron transport layer₂Or ZTO or AlO_xOr SnO₂Or ZnMgO with a thickness of 80nm to 120 nm.

Perovskite layer having ABX₃The organic-inorganic hybrid perovskite with a crystal structure is characterized in that A is methylamine or formamidineamine, B is lead, tin or antimony, X is iodine, bromine or chlorine, the forbidden bandwidth is 1.55-1.8 eV, the value of X is 0.37-0.52, and the thickness is selected to be 100-500 nm.

A hole transport layer of nickel oxide (NiO), copper aluminum oxide (CuAlO), a thin film layer of copper oxide (SrCuO) material, or Spiro-OMeTAD (2, 2',7,7' -tetrakis [ N, N-bis (4-methoxyphenyl) amino ] -9,9' -spirobifluorene) or PTAA (poly [ bis (4-phenyl) (2,4,6 trimethylphenyl) amine ] or P3HT (3-hexylthiophene)) having a thickness of 60nm to 100 nm.

Buffer layer of MoO_xOr WO_x30nm to 60nm

The front electrode is silver with a thickness of 15-30 μm.

A method of making a double junction tandem cell 200 is also provided in the examples.

Step S1, using the double-side polished P-type silicon as the substrate, doping the element on the front side to form the N-type doped layer 206.

In order to obtain a silicon wafer applied to a solar cell, in an example, a P-type silicon wafer is selected, a surface damage layer of the silicon wafer is removed by etching the silicon wafer with an alkaline solution, and then double-side polishing is performed. The alkaline solution can be selected from KOH, 2 to 3V percent (volume ratio), 1 to 2V percent of additive, 65 to 75 ℃ of reaction temperature and 180 seconds of reaction time.

And manufacturing a PN junction by the processed P-type silicon in a high-temperature diffusion mode. For example, phosphorus oxychloride (POCl) is used₃) And high-temperature diffusion is carried out as a doping element source. And forming a phosphorus (P) -doped N + emitter junction (phosphorus doped layer) on the front surface of the silicon wafer, wherein the sheet resistance of the doped layer is 150-200 omega/□. High temperature (800 ℃ to 860 ℃) diffusion method. Depositing by introducing oxygen gas 0.6-1.3slm (Standard Liter per minute), small nitrogen gas 0.7-1.5slm, and big nitrogen gas 20-25 slm. The reaction temperature is 800-820 ℃, and the reaction time is 600-700 s; the temperature is increased and advanced, wherein the nitrogen is introduced at 20-25slm, the reaction temperature is 850 ℃ and 860 ℃, and the reaction time is 500 seconds and 700 seconds.

In the foregoing manner, doped layers can be formed on both surfaces (front and back surfaces) of the silicon substrate, and in the present example, the doped layer on the front surface of the silicon substrate is selected to be retained, so that the phosphorus doped layer on the back surface can be removed before the back surface of the silicon substrate is processed later. Therefore, junctions are formed on the front surface, the back surface and the edge of the base silicon, and the junction of the back surface and the edge can be selectively removed according to different designs. The removing method is, for example, wet etching process with HNO₃And the/HF mixed solution is used for removing the phosphorus-doped N + junction on the back surface and directly exposing the silicon substrate, so that other functional layers can be conveniently combined. Alternatively, the removal may be by plasma etching, which removes the junctions at the edge of the wafer (edge scribing) and the junctions at the back side. Or the junction at the edge of the silicon wafer is removed by plasma etching, the junction at the back can be removed by printing aluminum paste on the junction, and through a high-temperature sintering process, the back is directly inverted by heavy doping of aluminum to form a strong P layer (the concentration of phosphorus atoms is far less than that of aluminum atoms) so as to realize the removal of the back junction.

The wet etching process is, for example: 1. the front surface of the silicon chip, namely the diffusion surface, needs to be sprayed with a water film so as to avoid corroding the pn junction and the light trapping texture surface structure on the front surface in the etching process. 2. The back and the periphery of the silicon wafer can be in contact with etching and liquid medicine under the protection of the front water film, so that the back and the edge PSG can be removed through chemical reaction. 3. And cleaning the residual etching liquid medicine on the silicon wafer in a soaking and spraying mode. 4. The hot air knife passes through the fan to enable the primarily filtered air to pass through the HEPA high-efficiency filter to generate hot air at the temperature of 60-70 ℃, and the surface of the silicon wafer is dried by the air knife. The water film is DI water; removing 5% HF from PSG, reacting at 25 deg.C for 60-70 s; DI water, 400-.

After wet etching, an anneal may optionally be performed, for example by heating, the heating temperature being chosen to be 750 ℃ to 850 ℃. The interface recombination of the silicon chip/aluminum oxide can be reduced through high-temperature annealing, so that the minority carrier lifetime is prolonged, and the passivation effect of a passivation layer (such as aluminum oxide) is ensured. In addition, if the N + doped layer is manufactured by selecting phosphorus doping only on the front surface of the silicon substrate, it is obvious that the aforementioned phosphorus doped layer removing operation may not be performed.

In step S2, a front passivation layer 207 is formed on the N-type doped layer 206 after the doped layer is formed.

The front passivation layer 207 may be formed on the front surface of the silicon wafer by, for example, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. When the passivation layer is silicon nitride (SiNx), SiH is used as the material₄(silane) and NH₃(ammonia gas) at a reaction temperature of 300 ℃ to 550 ℃, the front passivation layer 207 has a thickness of, for example, 70nm to 110nm and a refractive index of 1.9 to 2.2. The passivation layer may be fabricated as a single layer or as multiple layers, such as a bilayer or trilayer, as desired. For the scheme where the front passivation layer 207 is multi-layered, the chemical vapor deposition process may be repeated multiple times.

Step S3, preparing a transparent conductive layer 208 on the front passivation layer 207.

The transparent conductive layer 208 can be selected from metal oxides (such as indium tin oxide ITO), and the fabrication process thereof is magnetron sputtering or evaporation, for example. The nano indium tin metal oxide has good conductivity and transparency, is transparent for collecting and conducting electrons, and allows more light to be transmitted to the bottom cell.

Step S4 is to prepare an electron transport layer 209 on the transparent conductive layer 208.

As the name implies, the electron transport layer 209 is a good conductor of electrons as carriers, which can conduct electrons while isolating holes. The electron transport Layer 209 may be fabricated by Atomic Layer Deposition (ALD) technology. Specific optional materials include, but are not limited to, aluminum oxide or tin oxide, among others. The thickness of the electron transport layer 209 can be selected, for example, from 80nm to 120nm (e.g., 81nm, 85nm, 93nm, 96nm, 105nm, 109nm, 115nm, 118nm, or 119 nm).

In step S5, a perovskite layer 210 (light-absorbing layer) is formed on the electron transport layer 209.

The perovskite is typically fabricated in the form of a slurry and cured by suitable manipulation to dry. Thus, the paste can be transferred with a defined topography to the surface of the electron transport layer 209 by spraying, spin coating, thermal evaporation or screen printing, and then the solvent/dispersant is removed by low temperature heat treatment (e.g., 200 ℃ to 250 ℃, 300 seconds to 600 seconds). In an example, perovskite ABX₃Wherein A is selected from methylamine tin, B is selected from tin, and X is selected from chlorine. The thickness thereof may be, for example, 60nm to 100nm (e.g., 62nm, 64nm, 69nm, 72nm, 76nm, 85nm, 89nm, 94nm, 96nm, or 97 nm).

Step S6 is to form a hole transport layer 211 on the perovskite layer 210.

The hole transport layer 211 is prepared by ion deposition, for example, to prepare the hole transport layer 211. In an example, the hole transport layer 211 is made of nickel oxide and has a thickness of 60nm to 100nm (e.g., 63nm, 65nm, 68nm, 74nm, 79nm, 83nm, 88nm, 92nm, 96nm, or 98 nm).

In step S7, a buffer layer 212 is formed on the hole transport layer 211.

The buffer layer 212 may be fabricated by depositing a metal oxide on the hole transport layer 211 by vacuum evaporation. The metal oxide may be selected from molybdenum oxide having a thickness of 30nm to 60nm (e.g., 33nm, 35nm, 39nm, 41nm, 44nm, 48nm, 55nm, or 59 nm).

In step S8, the front electrode 213 in contact with the buffer layer 212 is formed on the buffer layer 212.

In the example, the front electrode 213 is selected as a silver finger electrode, and thus, it may use a metal line (width of 20 μm to 40 μm and height of 15 μm to 30 μm) of a screen-printed low-temperature silver material. And then drying and curing the substrate at 180-200 ℃ to complete the manufacture of the front electrode 213.

Since the front electrode 213 is in contact with the buffer layer 212, the front electrode 213 may be adjusted according to different manufacturing forms of the buffer layer 212. For example, when the buffer layer 212 is prepared with a hole reserved up to the hole transport layer 211, the front electrode 213 may be prepared by screen printing after the buffer layer 212 is prepared. When the buffer layer 212 is manufactured, and the buffer layer 212 does not reserve a hole reaching the hole transport layer 211, after the buffer layer 212 is manufactured, the buffer layer 212 may be etched to form a hole reaching the hole transport layer 211, and then the front electrode 213 is manufactured by screen printing.

And step S9, sequentially manufacturing a laminated back passivation layer 203 and an antireflection layer 202 on the back of the P-type silicon wafer.

The back passivation layer 203 and the anti-reflection layer 202 are manufactured on the back of the silicon substrate in a plurality of times, specifically, the back passivation layer 203 is manufactured first, and then the anti-reflection layer 202 is manufactured. Both layers can be made of metal compound materials, so that the two layers can be made by atomic layer deposition or plasma enhanced chemical vapor deposition. The antireflection layer can have a textured structure/suede to avoid specular reflection of light, so that a light trapping structure is formed on the surface. In this way, more light can be incident inside the cell without being lost by reflection.

Step S10, the back passivation layer 203 and the anti-reflection layer 202 are partially removed to expose the electrode region of the P-type silicon wafer.

In order to suppress undesired carrier recombination caused by direct contact of the back electrode 201 with the silicon substrate, the silicon substrate is optionally doped, in the example with aluminum, so as to form an aluminum doped region 204 of the P + doping type. Thus, the back electrode 201 formed subsequently contacts the silicon substrate through the electrode region formed by the aluminum doping.

Step S11, P-type doping is performed on the electrode region, and the back electrode 201 contacting the electrode region is disposed.

The back electrode 201 is made of aluminum in this example, and is manufactured by printing aluminum paste and then sintering the aluminum paste at a high temperature.

It should be noted that although a specific sequence of steps is given above, one or more of the above steps may be adjusted within an allowable range without contradiction. For example, in the above steps S1 to S11, the functional layer of the top cell is mainly formed first, and then the functional layer of the bottom cell is manufactured.

In other examples, steps S2-S9 may be performed after steps S10 and S11 are performed. That is, the steps are performed in the order of step S1, step S10, step S11, step S2, step S3, step S4, step S5, step S6, step S7, step S8, and step S9. In other words, in this example, for a double-junction stacked cell, the functional layers that make up the bottom cell are fabricated first, and then the functional layers that make up the top cell are fabricated.

Because the double-junction laminated cell has a cell with a double-sided back passivation structure, the passivation layer is opened by laser grooving (secondary grid line graph) on the back passivation layer, and then aluminum paste is printed and permeates the passivation layer to form ohmic contact with a silicon wafer to form a grid line (secondary grid). Therefore, it has the characteristics of double-sided light absorption and power generation.

The double-junction tandem cell of the present application is described in further detail below with reference to examples.

Example 1

The structure of the double-junction laminated cell is as follows. It comprises a back electrode (aluminum, 30 μm), an anti-reflection layer (SiN)_x100nm), back passivation layer (AlO)_x5nm), P-type silicon layer (P-type crystalline silicon, 160nm), N-type doped layer (phosphorus doped, 0.5nm), front passivation layer (SiN)_x80nm), transparent conductive layer (ITO, 10nm), electron transport layer (TiO)₂100nm), perovskite layer (methylamine, lead, chlorine, 100nm), hole transport layer (nickel oxide, 60nm), buffer layer (WoO nm)_x30nm) and a front electrode (silver, 15 μm).

The manufacturing method comprises the following steps:

(a) and selecting a P-type silicon wafer, removing a damaged layer of the silicon wafer in a groove by adopting an alkaline solution, and polishing two sides of the silicon wafer. The alkaline solution can be selected from KOH, 2% (volume ratio), additive 1% (volume ratio), reaction temperature of 70 deg.C, and reaction time of 200 s.

(b) Adopting phosphorus oxychloride to diffuse at high temperature of 800 ℃ to form a phosphorus element doped N + emitter junction on the front surface of the silicon wafer. Introducing oxygen gas 0.6slm, small nitrogen gas 0.7slm, large nitrogen gas 20slm, reaction temperature 800 deg.C and reaction time 600 s; heating and propelling, introducing 20slm of atmospheric nitrogen, and reacting at 850 ℃ for 500 s.

(c) Adopting wet etching process and HNO₃And removing the P doped N + junction on the back surface by using the/HF mixed solution. 1. Spraying water film on the front surface (diffusion surface) of the silicon wafer. 2. Under the protection of the water film, the back and the periphery of the silicon wafer can be in contact with etching and liquid medicine, so that the back and the edge PSG can be removed through chemical reaction. 3. And cleaning the residual etching liquid medicine on the silicon wafer in a soaking and spraying mode. 4. The hot air knife passes through the fan to enable the primarily filtered air to pass through the HEPA high-efficiency filter to generate hot air at 60 ℃, and the surface of the silicon wafer is dried by the air knife. The water film is DI water; removing 5 percent of HF from PSG, reacting at the temperature of 25 ℃ for 70 s; cleaning with DI water, 500 s.

(d) High temperature annealing is carried out, and the reaction temperature is 750 ℃.

(e) And sequentially depositing an aluminum oxide layer and a silicon nitride layer film on the back of the silicon wafer by adopting an atomic layer deposition method to form a laminated structure of a passivation layer and an antireflection layer.

(f) And forming a silicon nitride layer on the front surface of the silicon wafer by adopting a plasma enhanced chemical vapor deposition method.

(g) And selectively etching off part of the passivation layer on the back of the silicon wafer by adopting laser etching to expose the silicon layer.

(h) And (3) adopting screen printing, printing aluminum paste on the back surface of the silicon wafer according to the design of a screen printing plate pattern, and then sintering at high temperature to form a P + layer and a back electrode to form a P-type back passivation cell as a bottom cell.

(i) And preparing the transparent conductive film connecting layer on the front surface of the P-type back passivation cell by using a magnetron sputtering or evaporation technology.

(j) On the transparent conductive film, an electron transport layer is prepared.

(k) On the electron transport layer, a perovskite layer was prepared to a thickness of 500 μm by low-temperature heat treatment using screen printing.

(l) On the perovskite layer, a hole transport layer was prepared using ion deposition to a thickness of 100 nm.

(m) on the hole transport layer, a buffer layer was deposited using vacuum evaporation to a thickness of 60 nm.

And (n) on the buffer layer, screen printing a low-temperature silver metal circuit with the width of 40 microns and the height of 30 microns is used, and the front electrode is manufactured by curing and drying at 200 ℃ to form the efficient perovskite/crystalline silicon back passivation laminated solar cell.

Performance testing

Photoelectric conversion efficiency (Eta,%)	22.88115
		Open circuit voltage (Uoc, V)	0.74515
Short-circuit current (Isc, mA/cm)2)	9.159365
		Fill factor (FF,%)	81.90162
Series resistance (Rs, omega)	0.002662
		Parallel resistance (Rsh omega)	2187.586
Reverse leakage current (IRev2, mA/cm)2)	0.004937

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (12)

1. A double junction stacked cell, comprising:

the bottom battery based on the semiconductor material is provided with a P-type silicon layer, an N-type doping layer formed on the front surface of the P-type silicon layer, a front passivation layer on the N-type doping layer and a back passivation layer on the back surface of the P-type silicon layer;

a transparent conductive layer bonded on the front passivation layer of the bottom cell;

the perovskite material-based top battery is characterized in that the front surface of a perovskite layer of the top battery is provided with a hole transport layer, the back surface of the perovskite layer of the top battery is provided with an electron transport layer, and the perovskite layer of the top battery is combined on the transparent conductive layer through the electron transport layer on the back surface.

2. The double junction stacked cell of claim 1, wherein said bottom cell comprises a silicon-based semiconductor cell, an alloy semiconductor cell, or an oxide semiconductor cell.

3. The double junction stacked cell of claim 1, wherein the top cell comprises a buffer layer bonded over the hole transport layer.

4. The double junction stacked cell as claimed in claim 3, wherein the electrode of the top cell penetrates the buffer layer to be combined with the hole transport layer.

5. The double junction stacked cell of claim 1, wherein said bottom cell comprises an anti-reflective layer bonded below said back passivation layer.

6. A double junction stacked cell, comprising: the hole transport layer is locally contacted and combined with a front electrode, and the P-type silicon layer is locally contacted and combined with a back electrode through local P-type doping.

7. The double junction laminate battery of claim 6, wherein the thickness of the perovskite layer is 100 to 500 μm.

8. The double junction tandem cell according to claim 6 or 7, wherein the thickness of the electron transport layer is 80nm to 120 nm.

9. The double junction stacked cell according to claim 8, wherein the hole transport layer has a thickness of 60nm to 100 nm.

10. The double-junction stacked cell according to claim 9, wherein the buffer layer has a thickness of 30nm to 60nm, and the transparent conductive layer has a thickness of 8nm to 25 nm.

11. The double junction laminated cell of claim 6, wherein said front electrode is a silver finger electrode.

12. The double junction stacked cell according to claim 6 or 11, wherein the back electrode is an aluminum finger electrode.

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