CN210927654U - On-vehicle ethernet interconnection intercommunity testing arrangement - Google Patents

Abstract

The utility model discloses an on-vehicle ethernet interconnection intercommunity testing arrangement, include: the device comprises a test equipment physical layer chip interface, a central processing unit and an error simulation circuit; wherein: the central processing unit is connected with the error simulation circuit and controls the error simulation circuit to carry out error simulation; the error simulation circuit is connected with the tested piece, and the physical layer chip interface of the test equipment is connected with the error simulation circuit. The utility model discloses a central processing unit controls error simulation circuit, can simulate the error condition of various cables automatically, has effectively improved the accuracy and the efficiency of interconnection intercommunity test.

Description

On-vehicle ethernet interconnection intercommunity testing arrangement

Technical Field

The utility model relates to an automotive electronics technical field especially relates to an on-vehicle ethernet interconnection intercommunity testing arrangement.

Background

With the application and development of the vehicle-mounted Ethernet technology, the vehicle-mounted Ethernet test industry standard is more and more mature. At present, in the standard of the test industry, the interconnection test aims to test the interconnection interoperability between each ethernet ECU (Electronic control unit), and ensure that controllers developed by each manufacturer can meet the requirement of vehicle starting time, can correctly perform cable diagnosis, and can correctly feed back link signal quality.

At present, in the process of testing interconnection and interoperability of vehicle-mounted Ethernet, manual testing is mostly adopted to simulate cable errors to carry out cable diagnosis and testing, and the accuracy and the efficiency are low. Even if a small number of cables need to be drawn on the PCB board, the cables connected with the tested equipment cannot be replaced due to the fact that automatic control is adopted in the existing design, and then the real cables cannot be connected into a testing system to be tested, so that the testing environment deviates from the actual requirements, and the testing result is influenced.

Therefore, how to conveniently, quickly and accurately test the interconnection interoperability is a problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a vehicle-mounted ethernet interconnection interoperability testing arrangement can simulate the error condition of various cables automatically, has effectively improved the accuracy and the efficiency of interconnection interoperability test.

The utility model provides a vehicle-mounted Ethernet interconnection intercommunity testing arrangement, include: the device comprises a test equipment physical layer chip interface, a central processing unit and an error simulation circuit; wherein:

the central processing unit is connected with the error simulation circuit and controls the error simulation circuit to carry out error simulation;

the error simulation circuit is connected with the tested piece;

and the physical layer chip interface of the test equipment is connected with the error simulation circuit.

Preferably, the error simulation circuit includes: the device comprises an external cable, a test cable switching module and a cable error injection module; wherein:

the external cable is connected with the test cable switching module;

the test cable switching module is connected with the central processing unit and switches the external cable to be connected or disconnected based on the control of the central processing unit;

the cable error injection module is connected with the central processing unit and switches the error type of the cable based on the control of the central processing unit.

Preferably, the external cable includes: either a real twisted pair or a custom twisted pair.

Preferably, the test cable switching module and the cable fault injection module in the fault simulation circuit are composed of a plurality of single-pole double-throw controllable relay connections.

Preferably, the physical layer chip interface of the test equipment and the tested piece are respectively connected with the single-pole double-throw controllable relay in the test cable switching module and the cable fault injection module through twisted pairs.

Preferably, the test cable switching module and the cable fault injection module are composed of 16 single pole double throw controllable relay connections, wherein:

the tested part is respectively connected with a pin 3 of a No. 12 single-pole double-throw controllable relay, a pin 3 of a No. 10 single-pole double-throw controllable relay, a pin 1 of a No. 14 single-pole double-throw controllable relay and a pin 1 of a No. 15 single-pole double-throw controllable relay through a positive pole BR + of a twisted pair;

the tested piece is respectively connected with a pin 3 of a No. 13 single-pole double-throw controllable relay, a pin 3 of a No. 11 single-pole double-throw controllable relay, a pin 3 of a No. 14 single-pole double-throw controllable relay and a pin 1 of a No. 16 single-pole double-throw controllable relay through a negative pole BR < - >;

pin 1 of the 12 th single-pole double-throw controllable relay is connected with a power supply, pin 1 of the 10 th single-pole double-throw controllable relay is grounded, pin 1 of the 13 th single-pole double-throw controllable relay is connected with the power supply, and pin 1 of the 11 th single-pole double-throw controllable relay is grounded;

pin 2 of the No. 15 single-pole double-throw controllable relay is connected with pin 1 of the No. 1 single-pole double-throw controllable relay;

pin 2 of the No. 16 single-pole double-throw controllable relay is connected with pin 1 of the No. 2 single-pole double-throw controllable relay;

pin 2 of the No. 1 single-pole double-throw controllable relay is connected with pin 2 of the No. 3 single-pole double-throw controllable relay;

pin 2 of the No. 2 single-pole double-throw controllable relay is connected with pin 2 of the No. 4 single-pole double-throw controllable relay;

a near-end positive pole BR + of the external cable is connected with a pin 3 of the No. 1 single-pole double-throw controllable relay, a near-end negative pole BR + of the external cable is connected with the pin 3 of the No. 2 single-pole double-throw controllable relay, a far-end positive pole BR + of the external cable is connected with the pin 3 of the No. 3 single-pole double-throw controllable relay, and a far-end negative pole BR + of the external cable is connected with the pin 3 of the No. 4 single-pole double-throw controllable relay;

the physical layer chip interface of the test equipment is respectively connected with a pin 1 of a No. 9 single-pole double-throw controllable relay, a pin 3 of a No. 7 single-pole double-throw controllable relay, a pin 3 of a No. 5 single-pole double-throw controllable relay and a pin 1 of a No. 3 single-pole double-throw controllable relay through a positive electrode BR + of a twisted pair;

the physical layer chip interface of the test equipment is respectively connected with a pin 3 of a No. 9 single-pole double-throw controllable relay, a pin 3 of a No. 8 single-pole double-throw controllable relay, a pin 3 of a No. 6 single-pole double-throw controllable relay and a pin 1 of a No. 4 single-pole double-throw controllable relay through a negative pole BR < - >;

pin 1 of No. 7 single-pole double-throw controllable relay is connected with the power supply, pin 1 of No. 5 single-pole double-throw controllable relay is grounded, pin 1 of No. 8 single-pole double-throw controllable relay is connected with the power supply, and pin 1 of No. 6 single-pole double-throw controllable relay is grounded.

To sum up, the utility model discloses a vehicle-mounted Ethernet interconnection intercommunity testing arrangement, include: the device comprises a test equipment physical layer chip interface, a central processing unit and an error simulation circuit; wherein: the central processing unit is connected with the error simulation circuit and controls the error simulation circuit to carry out error simulation; the error simulation circuit is connected with the tested piece, and the physical layer chip interface of the test equipment is connected with the error simulation circuit. The utility model discloses a central processing unit controls error simulation circuit, can simulate the error condition of various cables automatically, has effectively improved the accuracy and the efficiency of interconnection intercommunity test.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an embodiment 1 of a device for testing interconnection and interoperability of a vehicle-mounted ethernet disclosed by the present invention;

fig. 2 is a schematic structural diagram of an embodiment 2 of the device for testing interconnection and interoperability of the vehicle-mounted ethernet disclosed by the present invention;

fig. 3 is a circuit topology diagram of an error simulation circuit according to an embodiment of the present invention;

fig. 4 is a circuit topology diagram of a near-end BR + open circuit under the condition of no external cable according to an embodiment of the present invention;

fig. 5 is a circuit topology diagram of the present invention for accessing an external cable and simultaneously making a near-end BR + open circuit;

fig. 6 is a circuit topology diagram of BR + and BR-dual pair short circuit without external cables according to an embodiment of the present invention;

fig. 7 is a circuit topology diagram of the present invention for simultaneously manufacturing BR + and BR-two-wire pair electrical short circuit by accessing external cables.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

As shown in fig. 1, for the utility model discloses a structural schematic diagram of on-vehicle ethernet interconnection intercommunity testing arrangement embodiment 1, the device includes: the device comprises a test equipment physical layer chip interface 11, a central processing unit 12 and an error simulation circuit 13; wherein:

the central processing unit 12 is connected with the error simulation circuit 13 and controls the error simulation circuit to carry out error simulation;

the error simulation circuit 13 is connected with the tested piece 14;

the test equipment physical layer chip interface 11 is connected to an error simulation circuit 13.

The working principle of the device for testing the interconnection and the interoperability of the vehicle-mounted Ethernet disclosed by the embodiment is as follows: when the interconnection interoperability test of the vehicle-mounted ethernet is required, the error simulation circuit 13 is controlled by the central processing unit 12 according to different test requirements, so that the error simulation circuit 13 simulates corresponding errors. After the error simulation circuit 13 simulates a corresponding error, since the device under test 14 is connected to the error simulation circuit 13 and the test equipment physical layer chip interface 11 is connected to the error simulation circuit 13, the test equipment can test whether the device under test 14 is capable of correctly detecting the error occurring in the link under the error condition currently simulated by the error simulation circuit 13.

To sum up, the utility model discloses a central processing unit controls error simulation circuit, can simulate the error condition of various cables automatically, has effectively improved the accuracy and the efficiency of interconnection intercommunity test.

As shown in fig. 2, for the utility model discloses a structural schematic diagram of on-vehicle ethernet interconnection intercommunity testing arrangement embodiment 2, the device includes: a test device physical layer chip interface 21, a central processing unit 22 and an error simulation circuit 23; the error simulation circuit 23 includes: an external cable 231, a test cable switching module 232 and a cable fault injection module 233; wherein:

the error simulation circuit 23 is connected with the tested piece 24;

the physical layer chip interface 21 of the test equipment is connected with the error simulation circuit 23;

the external cable 231 is connected with the test cable switching module 232;

the test cable switching module 232 is connected with the central processing unit 22, and switches the external cable 231 to be connected or disconnected based on the control of the central processing unit 22;

the cable fault injection module 233 is connected to the central processing unit 22, and switches the fault type of the cable based on the control of the central processing unit 22.

The working principle of the device for testing the interconnection and the interoperability of the vehicle-mounted Ethernet disclosed by the embodiment is as follows: when the interconnection interoperability test of the vehicle-mounted ethernet is required, the test cable switching module 232 can be controlled by the central processing unit 22 according to different test requirements, and the external cable 231 can be connected or disconnected by controlling the test cable switching module 232; the cable fault injection module 233 can also be controlled by the central processing unit 22, and different cable fault types can be flexibly generated by controlling the cable fault injection module 233. After the external cable 231 is connected or disconnected and/or the cable fault injection module 233 generates different cable fault types, since the tested piece 24 is connected to the fault simulation circuit 23 and the test device physical layer chip interface 21 is connected to the fault simulation circuit 23, the test device can test whether the tested piece 24 is connected or disconnected in the external cable 231 and/or the cable fault injection module 233 generates different cable fault types and is capable of correctly detecting the fault in the link.

In summary, in this embodiment, on the basis of the foregoing embodiment 1, the test cable switching module can be controlled by the central processing unit, so as to implement connection or disconnection of the external cable; and the central processing unit controls the cable error injection module, so that different cable error types can be flexibly generated, and the accuracy and efficiency of the interconnection interoperability test are effectively improved.

Specifically, in the above embodiment, the external cable may include: a real vehicle twisted pair or a custom twisted pair; the test cable switching module and the cable error injection module in the error simulation circuit can be formed by connecting a plurality of single-pole double-throw controllable relays, and the test equipment physical layer chip interface and the tested piece can be respectively connected with the single-pole double-throw controllable relays in the test cable switching module and the cable error injection module through twisted-pair lines. The central processing unit can send a control signal to the corresponding single-pole double-throw controllable relay through the I/O port to control the suction state of the single-pole double-throw controllable relay, so that the access or disconnection of an external cable is realized, and different cable error types are flexibly generated.

In order to more clearly explain the technical solution provided by the present invention, the following description is made with specific application examples:

as shown in fig. 3, for the utility model discloses a circuit topology of error simulation circuit, test cable switches module and cable error injection module and is connected by 16 single-pole double-throw controllable relays and constitutes, wherein:

a DUT (device under test) is respectively connected with a pin 3 of a No. 12 single-pole double-throw controllable relay, a pin 3 of a No. 10 single-pole double-throw controllable relay, a pin 1 of a No. 14 single-pole double-throw controllable relay and a pin 1 of a No. 15 single-pole double-throw controllable relay through a positive pole BR + of a twisted pair;

a tested DUT (device under test) is respectively connected with a pin 3 of a No. 13 single-pole double-throw controllable relay, a pin 3 of a No. 11 single-pole double-throw controllable relay, a pin 3 of a No. 14 single-pole double-throw controllable relay and a pin 1 of a No. 16 single-pole double-throw controllable relay through a negative pole BR < - >;

pin 1 of No. 12 single-pole double-throw controllable relay is connected with a power supply VCC, pin 1 of No. 10 single-pole double-throw controllable relay is grounded GND, pin 1 of No. 13 single-pole double-throw controllable relay is connected with the power supply VCC, and pin 1 of No. 11 single-pole double-throw controllable relay is grounded GND;

pin 2 of No. 15 single-pole double-throw controllable relay is connected with pin 1 of No. 1 single-pole double-throw controllable relay;

pin 2 of No. 16 single-pole double-throw controllable relay is connected with pin 1 of No. 2 single-pole double-throw controllable relay;

pin 2 of the No. 1 single-pole double-throw controllable relay is connected with pin 2 of the No. 3 single-pole double-throw controllable relay;

pin 2 of No. 2 single-pole double-throw controllable relay is connected with pin 2 of No. 4 single-pole double-throw controllable relay;

a near-end anode BR + of the external cable is connected with a pin 3 of a No. 1 single-pole double-throw controllable relay, a near-end cathode BR-of the external cable is connected with a pin 3 of a No. 2 single-pole double-throw controllable relay, a far-end anode BR + of the external cable is connected with a pin 3 of a No. 3 single-pole double-throw controllable relay, and a far-end cathode BR + of the external cable is connected with a pin 3 of a No. 4 single-pole double-throw controllable relay;

the physical layer chip interface LP of the test equipment is respectively connected with a pin 1 of a No. 9 single-pole double-throw controllable relay, a pin 3 of a No. 7 single-pole double-throw controllable relay, a pin 3 of a No. 5 single-pole double-throw controllable relay and a pin 1 of a No. 3 single-pole double-throw controllable relay through a positive pole BR + of a twisted pair;

the physical layer chip interface LP of the test equipment is respectively connected with a pin 3 of a No. 9 single-pole double-throw controllable relay, a pin 3 of a No. 8 single-pole double-throw controllable relay, a pin 3 of a No. 6 single-pole double-throw controllable relay and a pin 1 of a No. 4 single-pole double-throw controllable relay through a negative pole BR < - >;

pin 1 of No. 7 single-pole double-throw controllable relay is connected with power VCC, pin 1 ground GND of No. 5 single-pole double-throw controllable relay, pin 1 of No. 8 single-pole double-throw controllable relay is connected with power VCC, and pin 1 ground GND of No. 6 single-pole double-throw controllable relay.

In the error simulation circuit, 16 single-pole double-throw controllable relays No. 1-16 are included. The DUT and the chip interface LP of the physical layer of the testing equipment are respectively connected with a twisted pair (a differential signal wire, the positive pole is BR +, the negative pole is BR-) and 16 single-pole double-throw controllable relays. The external cable can be a real-vehicle twisted-pair cable or a customized twisted-pair cable, BR + and BR-at a near end (close to one end of a tested device DUT) and BR + and BR-at a far end (close to one end of a physical layer chip interface LP of the testing equipment) are sequentially connected with the controllable relays of No. 1, No. 2, No. 3 and No. 4 single-pole double-throw, and the pull-in of the controllable relays of the 4 single-pole double-throw is controlled by the central processing unit to realize the function of connecting/disconnecting the external cable.

Through the control of the central processing unit, the free switching and cable error simulation of the conditions of no external cable and external cable can be realized. The related single-pole double-throw controllable relay has two pull-in states: a default attracting state (namely attracting pin 1 and pin 2) and a controlled attracting state (namely attracting pin 1 and pin 3). Under the condition of no cable error, the No. 1-16 single-pole double-throw controllable relay is in a default pull-in state, and a twisted pair connecting the testing equipment and the tested piece belongs to the condition of passage. When the cable error needs to be simulated, the central processing unit sends a control signal to the corresponding single-pole double-throw controllable relay through the I/O port, and the single-pole double-throw controllable relay is switched to a controlled attraction state from a default attraction state.

Taking the open circuit error simulation as an example, in order to realize the near end BR + open circuit under the condition of no external cable, the central processing unit needs to control the No. 15 single-pole double-throw controllable relay to be switched from the default pull-in state to the controlled pull-in state (as shown in fig. 4), so that the BR + connected between the No. 15 relay pin 1 and the No. 15 relay pin 2 is made to have open circuit. When an external cable needs to be connected and a near-end BR + circuit is manufactured (as shown in FIG. 5), besides the controllable relay of No. 15 single-pole double-throw is required to be controlled to be in a controlled pull-in state, the controllable relays of No. 1, No. 2, No. 3 and No. 4 single-pole double-throw are also required to be controlled to be in a controlled pull-in state, so that an external twisted pair is introduced. Similarly, the No. 1 single-pole double-throw controllable relay is responsible for the remote circuit break of BR +; no. 16 and No. 2 single-pole double-throw controllable relays are respectively responsible for the near-end and far-end circuit breaking of BR-.

Taking short-circuit error simulation as an example, realizing BR + and BR-double-wire pair electricity (VCC) short circuit under the condition of no external cable, controlling the controllable relay of No. 12 and No. 13 single-pole double-throw to be switched from the default pull-in state to the controlled pull-in state (as shown in figure 6), so as to manufacture the pin 1 and the pin 3 of the controllable relay of No. 12 single-pole double-throw and the controllable relay of No. 13 single-pole double-throw to be communicated, thereby realizing pair electricity short circuit. When BR + and BR-double-wire pair electrical short circuit is manufactured while an external cable is required to be connected (as shown in fig. 7), besides the controllable relays of the single-pole double-throw type 12 and the single-pole double-throw type 13 are required to be controlled to be in a controlled pull-in state, the controllable relays of the single-pole double-throw type 1, the single-pole double-throw type 2, the single-pole double-throw type 3 and the single-pole double-throw type 4 are required to be controlled to be in a controlled pull-in state. Similarly, the No. 10 and No. 11 single-pole double-throw controllable relays are responsible for short circuit of BR + and BR-near-end double lines to the Ground (GND); the No. 14 single-pole double-throw controllable relay is responsible for short circuit between a BR + double wire and a BR-double wire at a near end; no. 5 and No. 6 single-pole double-throw controllable relays are responsible for short circuit of BR + and BR-near-end double lines to the ground; no. 7 and No. 8 single-pole double-throw controllable relays are responsible for BR + and BR-far-end double-line to electric short circuit; the relay No. 9 is responsible for short circuit between remote terminals BR + and BR-double wires.

The equipment needs to simulate 12 the type of cable fault according to the test requirements. After the circuit is applied, the free switching of 12 cable error types under the condition of existence of an external cable can be realized. The relationship between the error type of the cable and the label of the single-pole double-throw controllable relay which is correspondingly required to be in the controlled pull-in state is shown in table 1:

TABLE 1 relationship between cable error types and corresponding single-pole double-throw controllable relay labels required to be in controlled pull-in state

To sum up, through having used the utility model discloses switching circuit, various cable error conditions of simulation that test equipment can be automatic have improved the accuracy and the efficiency of test effectively. The device is not only adaptive to test implementation under the condition of no external cable, but also adaptive to test implementation under the condition of an external real vehicle cable or other customized cables, so that the device can be applied to each stage of vehicle test, and the flexibility of the use of the device is improved.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. The utility model provides a vehicle-mounted Ethernet interconnection intercommunity testing arrangement which characterized in that includes: the device comprises a test equipment physical layer chip interface, a central processing unit and an error simulation circuit; wherein:

the central processing unit is connected with the error simulation circuit and controls the error simulation circuit to carry out error simulation;

the error simulation circuit is connected with the tested piece;

and the physical layer chip interface of the test equipment is connected with the error simulation circuit.

2. The apparatus of claim 1, wherein the error simulation circuit comprises: the device comprises an external cable, a test cable switching module and a cable error injection module; wherein:

the external cable is connected with the test cable switching module;

the test cable switching module is connected with the central processing unit and switches the external cable to be connected or disconnected based on the control of the central processing unit;

the cable error injection module is connected with the central processing unit and switches the error type of the cable based on the control of the central processing unit.

3. The apparatus of claim 2, wherein the external cable comprises: either a real twisted pair or a custom twisted pair.

4. The apparatus of claim 3, wherein the test cable switching module and the cable fault injection module in the fault simulation circuit are comprised of a plurality of single pole double throw controllable relay connections.

5. The apparatus of claim 4, wherein the test device physical layer chip interface and the device under test are connected to single pole double throw controllable relays in the test cable switching module and the cable fault injection module, respectively, by twisted pair wires.

6. The apparatus of claim 5, wherein the test cable switching module and cable fault injection module are comprised of 16 single pole double throw controllable relay connections, wherein:

the tested part is respectively connected with a pin 3 of a No. 12 single-pole double-throw controllable relay, a pin 3 of a No. 10 single-pole double-throw controllable relay, a pin 1 of a No. 14 single-pole double-throw controllable relay and a pin 1 of a No. 15 single-pole double-throw controllable relay through a positive pole BR + of a twisted pair;

the tested piece is respectively connected with a pin 3 of a No. 13 single-pole double-throw controllable relay, a pin 3 of a No. 11 single-pole double-throw controllable relay, a pin 3 of a No. 14 single-pole double-throw controllable relay and a pin 1 of a No. 16 single-pole double-throw controllable relay through a negative pole BR < - >;

pin 1 of the 12 th single-pole double-throw controllable relay is connected with a power supply, pin 1 of the 10 th single-pole double-throw controllable relay is grounded, pin 1 of the 13 th single-pole double-throw controllable relay is connected with the power supply, and pin 1 of the 11 th single-pole double-throw controllable relay is grounded;

pin 2 of the No. 15 single-pole double-throw controllable relay is connected with pin 1 of the No. 1 single-pole double-throw controllable relay;

pin 2 of the No. 16 single-pole double-throw controllable relay is connected with pin 1 of the No. 2 single-pole double-throw controllable relay;

pin 2 of the No. 1 single-pole double-throw controllable relay is connected with pin 2 of the No. 3 single-pole double-throw controllable relay;

pin 2 of the No. 2 single-pole double-throw controllable relay is connected with pin 2 of the No. 4 single-pole double-throw controllable relay;

a near-end positive pole BR + of the external cable is connected with a pin 3 of the No. 1 single-pole double-throw controllable relay, a near-end negative pole BR + of the external cable is connected with the pin 3 of the No. 2 single-pole double-throw controllable relay, a far-end positive pole BR + of the external cable is connected with the pin 3 of the No. 3 single-pole double-throw controllable relay, and a far-end negative pole BR + of the external cable is connected with the pin 3 of the No. 4 single-pole double-throw controllable relay;

the physical layer chip interface of the test equipment is respectively connected with a pin 1 of a No. 9 single-pole double-throw controllable relay, a pin 3 of a No. 7 single-pole double-throw controllable relay, a pin 3 of a No. 5 single-pole double-throw controllable relay and a pin 1 of a No. 3 single-pole double-throw controllable relay through a positive electrode BR + of a twisted pair;

the physical layer chip interface of the test equipment is respectively connected with a pin 3 of a No. 9 single-pole double-throw controllable relay, a pin 3 of a No. 8 single-pole double-throw controllable relay, a pin 3 of a No. 6 single-pole double-throw controllable relay and a pin 1 of a No. 4 single-pole double-throw controllable relay through a negative pole BR < - >;

pin 1 of No. 7 single-pole double-throw controllable relay is connected with the power supply, pin 1 of No. 5 single-pole double-throw controllable relay is grounded, pin 1 of No. 8 single-pole double-throw controllable relay is connected with the power supply, and pin 1 of No. 6 single-pole double-throw controllable relay is grounded.

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