CN210926020U - Layered pixel compensation circuit - Google Patents
Layered pixel compensation circuit Download PDFInfo
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- CN210926020U CN210926020U CN201922235305.1U CN201922235305U CN210926020U CN 210926020 U CN210926020 U CN 210926020U CN 201922235305 U CN201922235305 U CN 201922235305U CN 210926020 U CN210926020 U CN 210926020U
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Abstract
A layered pixel compensation circuit comprises a lower thin film transistor area, an upper thin film transistor area and an insulating layer, wherein the lower thin film transistor area and the upper thin film transistor area are arranged on a substrate, the insulating layer is arranged between the upper thin film transistor area and the lower thin film transistor area, an electrode of the upper thin film transistor area is connected with an electrode of the lower thin film transistor area through a connecting wire penetrating through the insulating layer, an organic light emitting diode is further patterned in the upper thin film transistor area, and a thin film transistor in the upper thin film transistor area and a thin film transistor in the lower thin film transistor area are connected to form the compensation circuit of the organic light emitting diode; be different from prior art, above-mentioned technical scheme is through the lower floor film transistor area in district and the upper strata film transistor area in district that the design base plate is last different, finally through the area that a plurality of film transistors of reducing pixel compensation circuit in vertical direction occupy for the area occupied of single pixel reduces, finally improves the resolution of screen.
Description
Technical Field
The utility model relates to a pixel compensation circuit's design especially relates to a novel pixel compensation circuit design of upper and lower layering.
Background
Nowadays, with the continuous improvement of the technology level, the demand for the display screen is also increasing, i.e. the demand for high resolution is increasing, for example, the resolution of VR, AR, MR and other displays is as high as 2000PPI or more. For the OLED panel, the luminance of the panel is not uniform due to the influence of Vth drift in the in-plane 2T1C Pixel circuit, and the compensation circuit is required to improve the display effect of the panel, and in order to achieve better compensation effect, the compensation circuit has a plurality of TFTs, which may have 4T, 5T, and 6T …, so that the area occupied by the pixels is increased due to too many TFTs, and the number of pixels contained in the panel is reduced, that is, the resolution is low, and the requirement of high resolution cannot be met.
Nowadays, the level of display quality demand on the panel is higher and higher, and it is important to improve the resolution of the display. It is known that for an OLED panel, due to the influence of the manufacturing process and aging, such as Vth shift, the display effect of the panel is greatly affected, in order to eliminate the influence, a Pixel circuit of the OLED panel usually adds a TFT as a compensation circuit, and generally, the better the compensation effect is, the more the TFTs are, which results in an overlarge Pixel occupied area and reduced resolution; if the Driving TFT in the Pixel compensation circuit is replaced with an LTPS TFT with higher electron mobility, that is, an LTPO (Low temperature polycrystalline Oxide) structure, the size of the TFT can be reduced, the resolution can be increased, and the circuit is layered, the original 6T1C Pixel circuit can be divided into an upper layer and a lower layer, namely, an upper layer 3 Oxide TFTs and a lower layer 3 LTPS TFTs, so as to further reduce the Pixel area and increase the resolution, and meanwhile, the practical LTPO can have the advantages of high LTPS electron mobility and small IGZO leakage current.
Therefore, it is an important issue to improve the resolution of the OLED panel, and to manufacture an OLED panel with a good compensation effect and an ultra-high resolution.
Disclosure of Invention
Therefore, it is desirable to provide a new layered pixel compensation circuit, which achieves the technical effects of reducing the TFT layout area and improving the panel resolution.
In order to achieve the above object, the inventor provides a layered pixel compensation circuit, which includes a lower thin film transistor region, an upper thin film transistor region, and an insulating layer disposed between the upper thin film transistor region and the lower thin film transistor region, wherein the lower thin film transistor region and the upper thin film transistor region are disposed on a substrate;
the lower thin film transistor region comprises thin film transistors T1, T2, T4 and a capacitor C; the upper thin film transistor region comprises T3, T5 and T6; the source electrode of the T1 is connected with Vdata, the grid electrode is connected with a first scanning signal, and the drain electrode is connected with the source electrode of the T2 and one end of a capacitor C; the grid electrode of the T2 is connected with a third scanning signal, and the drain electrode of the T2 is connected with the drain electrode of the T4;
the grid of the T4 is further connected with the drain of the T3 through a first upper and lower layer wiring, the grid of the T3 is connected with a first scanning signal, the source of the T3 is connected with the drain of the T5, the grid of the T5 is connected with a second scanning signal, the source of the T5 is connected with an on-chip voltage VDD, and the source of the T3 is further connected with the source of the T4 through a second upper and lower layer wiring; the drain of the T2 is further connected to the drain of the T6 and the anode of the pixel through a third upper and lower layer connection line, the gate of the T6 is connected to the first scan signal, and the source of the V6 is connected to the reference voltage Vref.
Furthermore, the lower thin film transistor is a polysilicon thin film transistor, the lower thin film transistor region comprises a polysilicon active layer connected with the metal electrode, the polysilicon active layer is coated with a barrier layer, the barrier layer is provided with a first gate layer, the polysilicon active layer, the metal electrode and the first gate layer are patterned into a plurality of polysilicon thin film transistors,
the upper thin film transistor area comprises an oxide active layer, and the upper thin film transistor area is patterned with oxide thin film transistors and AMOLED pixels;
the pixel compensation circuit further comprises a connecting wire, and the polycrystalline silicon thin film transistor is connected with the oxide thin film transistor through the connecting wire to form the pixel compensation circuit.
Specifically, the barrier layer and the first gate layer are further coated with a dielectric layer, and the dielectric layer is arranged below the insulating layer.
Optionally, the dielectric layer is hydrogenated amorphous silicon nitride.
Specifically, the barrier layer is a silicon oxide or aluminum oxide film.
Specifically, a flat layer is further arranged on the insulating layer, and the flat layer is an organic insulating material film.
Specifically, the insulating layer is a silicon oxide film.
Specifically, the pixel is an LTPO pixel.
Optionally, the substrate is a glass substrate.
Be different from prior art, above-mentioned technical scheme is through the lower floor film transistor area in district and the upper strata film transistor area in district that the design base plate is last different, finally through the area that a plurality of film transistors of reducing pixel compensation circuit in vertical direction occupy for the area occupied of single pixel reduces, finally improves the resolution of screen.
Drawings
FIG. 1 is a prior art pixel compensation circuit according to an embodiment;
FIG. 2 is a schematic diagram of a hierarchical pixel compensation circuit according to an embodiment;
FIG. 3 is a diagram illustrating a compensation circuit for pixels in different processes according to one embodiment;
FIG. 4 is a diagram illustrating the operation state of the Reset phase according to an embodiment;
FIG. 5 is a schematic diagram illustrating an operating state of the compensation phase according to an embodiment;
FIG. 6 is a schematic diagram illustrating the operation of the hold phase according to an embodiment;
fig. 7 is a schematic diagram of the working state of the light-emitting stage according to the embodiment.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1, a conventional 6T1C compensation circuit is shown in fig. 1, and although the compensation effect is good, pixels occupy a large area and have low resolution; to improve PPI, an LTPO compensation circuit architecture is invented as shown in fig. 2, LTPO can be understood as LTPS + Oxide, the upper layer includes three Oxide TFTs and an organic light emitting diode, the lower layer includes three LTPS TFTs and two capacitors, and the circuit architecture is divided into two parts, namely an upper layer and a lower layer, by using dotted lines to reduce Pixel occupation area; the layer diagram of the TFT is shown in fig. 3, and for convenience of description, only the layer diagrams of two TFTs are shown, which are an upper-layer Oxide TFT and a lower-layer LTPS TFT.
A layered AMOLED pixel compensation circuit is disclosed, as shown in FIG. 3, in the pixel compensation circuit, including a lower thin film transistor region and an upper thin film transistor region arranged on a substrate buffer, an insulating layer (Insulator 1) is further arranged between the upper thin film transistor region and the lower thin film transistor region, and the insulating layer can be a thin film made of silicon oxide. The electrodes of the upper thin film transistor region and the lower thin film transistor region are connected by a connection line 100 passing through the insulating layer, the upper thin film transistor region further patterns an organic light emitting diode (not shown), and the thin film transistor of the upper thin film transistor region and the thin film transistor of the lower thin film transistor region are connected to form a compensation circuit of the organic light emitting diode. The thin film transistors on the upper and lower layers are designed in the pixel compensation circuit, the thin film transistors on the lower layer can be selected in different patterning modes according to the actual connection relation of the pixel compensation circuit, the manufactured thin film transistors on the lower layer are fully covered by the insulating layer, the situations of electric leakage and the like are prevented, the thin film transistors on the upper layer and the related organic light emitting diodes, namely AMOLED pixels, are arranged above the insulating layer, and the thin film transistors on the upper layer and the lower layer are designed, so that the area required by tiling arrangement of the pixel compensation circuit relative to a single layer can be reduced, and the area required by the pixel compensation circuit is increased.
In other aspects, the LTPS process requires laser irradiation of amorphous silicon (a-si), and the a-si absorbs laser energy and then transforms into a polysilicon structure (poly-si), which is completed at 600 ℃. The metal-oxide semiconductor has unstable characteristics and is easily damaged by high temperature, light, water and oxygen to cause the failure of the TFT. Therefore, in some further embodiments, referring to fig. 1, the lower thin film transistor is a polysilicon thin film transistor, the lower thin film transistor region includes a polysilicon active layer (p-si), the polysilicon active layer is connected to the metal electrode, the polysilicon active layer is covered with a barrier layer (Insulator 2) for gate insulation, the barrier layer is provided with a first gate layer, the polysilicon active layer, the metal electrode and the first gate layer are patterned into a plurality of polysilicon thin film transistors, in alternative embodiments, the barrier layer is used for isolating the gate metal and the metal electrode, and the material may be silicon oxide or aluminum oxide thin film.
The upper thin film transistor region comprises an oxide active layer, and the medium of the active layer can be an oxide semiconductor, such as IGZO. In this embodiment, a dielectric layer is further disposed on the first gate layer, the dielectric layer is disposed below the insulating layer, and the dielectric layer is used to isolate the upper and lower thin film transistors, and the material of the dielectric layer may be hydrogenated amorphous silicon nitride, such as a-SiNx: H. The dielectric layer covers the barrier layer and the first gate layer. Patterning oxide thin film transistors and AMOLED pixels above the insulating layer; the thin film transistor above the insulating layer is an Oxide transistor adopting Oxide process, and the thin film transistor further comprises a connecting wire, and the polycrystalline silicon thin film transistor is connected with the Oxide thin film transistor through the connecting wire to form a pixel compensation circuit.
By the scheme, the LTPS thin film transistor is arranged on the lower layer, so that the LTPS manufacturing process and the Oxide manufacturing process can be compatible, the advantages of high resolution, high reaction speed, high brightness, high aperture opening ratio and the like of the LTPS manufacturing process can be compatible in the AMOLED pixel compensation circuit, the electron mobility can be improved, and the area can be reduced.
In some other further embodiments shown in fig. 3, a planarization layer (Insulator 3) is disposed on the insulating layer, and it can be seen that the planarization layer is disposed on the insulating layer to provide a flat upper surface for the upper thin-film transistor layer, and the planarization layer is an organic insulating material thin film.
Some examples of the fabrication of the pixel compensation circuit are provided below based on the main concept of a layered pixel circuit, where the lower tft region includes tfts T1, T2, T4 and a capacitor C; the upper thin film transistor region comprises T3, T5 and T6; the source electrode of the T1 is connected with Vdata, the grid electrode is connected with a first scanning signal, and the drain electrode is connected with the source electrode of the T2 and one end of a capacitor C; the grid electrode of the T2 is connected with a third scanning signal, and the drain electrode of the T2 is connected with the drain electrode of the T4;
the grid of the T4 is further connected with the drain of the T3 through a first upper and lower layer wiring, the grid of the T3 is connected with a first scanning signal, the source of the T3 is connected with the drain of the T5, the grid of the T5 is connected with a second scanning signal, the source of the T5 is connected with an on-chip voltage VDD, and the source of the T3 is further connected with the source of the T4 through a second upper and lower layer wiring; the drain of the T2 is further connected to the drain of the T6 and the anode of the pixel through a third upper and lower layer connection line, the gate of the T6 is connected to the first scan signal, and the source of the V6 is connected to the reference voltage Vref.
The peripheral wiring and the working principle of the pixel compensation circuit are similar to those of the prior art, and the following are introduced:
as shown in FIG. 4, during the first phase Vref, Scan1 and Scan2 inputs high voltage, T5 and T3 are turned on, VGVDD, T6 open, VSWhen T4 is turned on, T1 is turned on, data is written, VA＝Vdata。
As shown in FIG. 5, in the second stage of compensation, high voltage is inputted into Scan1, low voltage is inputted into Scan2, T1 and T6 are turned on, and V isA＝Vdata，VSWhen Vref is reached, T3 is turned on and the voltage at point G drops from VDD to Vref + VTHAt time T4 closed, i.e. VG＝Vref+VTH。
As shown in FIG. 6, in the third stage of voltage holding stage, low voltage is written in Scan1, Scan2 and Scan3, TFT is turned off, and the original voltage, i.e. V, is maintained at the G point, the S point and the A point at the G point due to the holding voltage of the capacitorG＝Vref+VTH，VS＝Vref，VA＝Vdata。
As shown in fig. 7, a fourth stage of light emission, VS＝VOLEDScan3 input high Voltage, T2 open, VA＝VOLEDThe voltage at point A is changed from Vdata to VOLEDThe voltage at the G point is changed into Vref + V by the capacitanceTH+VOLEDVdata, i.e. VG＝Vref+VTH+VOLEDVdata, then VGS＝VG-VS＝Vref+VTHVdata, substituting into the saturation region current formula IOLED＝1/2μnCOXW/L(VGS-VTH)2To obtain IOLED＝ 1/2μnCOXW/L(Vref-Vdata)]2(Note. mu.)nIs field effect mobility, COXAn insulating layer capacitor per unit area; W/L is TFT channel width to length).
The OLED luminous current formula can be used for knowing that the OLED current is only related to Vdata and Vref, other parameters are relatively fixed, and the compensation effect is good; the LTPO is adopted, so that the high electron mobility is achieved, and the power consumption is saved; the layered framework can reduce the occupied area of pixels, further improves the resolution, and therefore the design purpose of us is achieved through the design, the utility model discloses can use littleer Pixel area to reach the compensation effect to can finally improve the resolution of panel.
It should be noted that, although the above embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications of the embodiments described herein, or the equivalent structure or equivalent process changes made by the contents of the specification and the drawings of the present invention, directly or indirectly apply the above technical solutions to other related technical fields, all included in the scope of the present invention.
Claims (9)
1. A layered pixel compensation circuit is characterized by comprising a lower thin film transistor area, an upper thin film transistor area and an insulating layer, wherein the lower thin film transistor area and the upper thin film transistor area are arranged on a substrate;
the lower thin film transistor region comprises thin film transistors T1, T2, T4 and a capacitor C; the upper thin film transistor region comprises T3, T5 and T6; the source electrode of the T1 is connected with Vdata, the grid electrode is connected with a first scanning signal, and the drain electrode is connected with the source electrode of the T2 and one end of a capacitor C; the grid electrode of the T2 is connected with a third scanning signal, and the drain electrode of the T2 is connected with the drain electrode of the T4;
the grid of the T4 is further connected with the drain of the T3 through a first upper and lower layer wiring, the grid of the T3 is connected with a first scanning signal, the source of the T3 is connected with the drain of the T5, the grid of the T5 is connected with a second scanning signal, the source of the T5 is connected with an on-chip voltage VDD, and the source of the T3 is further connected with the source of the T4 through a second upper and lower layer wiring; the drain of the T2 is further connected to the drain of the T6 and the anode of the pixel through a third upper and lower layer connection line, the gate of the T6 is connected to the first scan signal, and the source of the V6 is connected to the reference voltage Vref.
2. The layered pixel compensation circuit of claim 1, wherein the lower TFT is a polysilicon TFT, the lower TFT comprises a polysilicon active layer connected to a metal electrode, the polysilicon active layer is covered with a barrier layer, the barrier layer is provided with a first gate layer, the polysilicon active layer, the metal electrode and the first gate layer are patterned into a plurality of polysilicon TFTs,
the upper thin film transistor area comprises an oxide active layer, and the upper thin film transistor area is patterned with oxide thin film transistors and AMOLED pixels;
the pixel compensation circuit further comprises a connecting wire, and the polycrystalline silicon thin film transistor is connected with the oxide thin film transistor through the connecting wire to form the pixel compensation circuit.
3. The layered pixel compensation circuit of claim 2, wherein the barrier layer and the first gate layer are further covered with a dielectric layer disposed under the insulating layer.
4. The layered pixel compensation circuit of claim 3, wherein the dielectric layer is hydrogenated amorphous silicon nitride.
5. The layered pixel compensation circuit of claim 2, wherein the blocking layer is a silicon oxide or aluminum oxide film.
6. The layered pixel compensation circuit of claim 1, wherein a planarization layer is further disposed on the insulating layer, and the planarization layer is a thin film of organic insulating material.
7. The layered pixel compensation circuit of claim 1, wherein the insulating layer is a silicon oxide film.
8. The hierarchical pixel compensation circuit of claim 1, wherein the pixel is an LTPO pixel.
9. The layered pixel compensation circuit of claim 1, wherein the substrate is a glass substrate.
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| CN201922235305.1U CN210926020U (en) | 2019-12-13 | 2019-12-13 | Layered pixel compensation circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048561A (en) * | 2019-12-13 | 2020-04-21 | 福建华佳彩有限公司 | Layered pixel compensation circuit |
| CN112382233A (en) * | 2020-11-19 | 2021-02-19 | 福建华佳彩有限公司 | Internal compensation circuit and control method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111048561A (en) * | 2019-12-13 | 2020-04-21 | 福建华佳彩有限公司 | Layered pixel compensation circuit |
| CN112382233A (en) * | 2020-11-19 | 2021-02-19 | 福建华佳彩有限公司 | Internal compensation circuit and control method thereof |
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